JPH04175946A - Multiprocessor data processing system and cache device used therein - Google Patents

Abstract

PURPOSE:To shorten a mean data access time by enabling a user to set a cache memory so that the cache memory is used as a local memory. CONSTITUTION:A main memory 5 is divided into a shared area that plural processors 1 and 2 and an input/output device 6 access for writing and plural private areas that the processors 1 and 2 access for writing. Plural cache devices 3 and 4 are equipped with area decision circuits which decide whether addresses generated by the processors 1 and 2 indicate access to the shared area or private areas, and operate according to a write through system or copy-back system when the shared area is accessed or as if they were local memories when the private areas are accessed. Consequently, the mean access time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor data processing system and a cache device used therein.

[Conventional technology]

In processor systems, in order to fill the gap between the processor's machine cycle time and the main memory's operating time, there is a known technology that improves system performance by placing a cache memory that operates at high speed between the processor and main memory. ing. Conventional cache storage methods are described in NCM, Computing Survey, Volume 14, Number 3, September, 1982, pages 500 to 502 (A
CM, Computing, 5urveys, VoQ
, 14, N13.

September 1982. pp, 500-5
As described in 02), there are write-through and copy-back methods.

The former write-through method is a method in which when a processor performs a write operation, if the cache is hit, the processor writes to both the cache and main memory, so that the contents of the cache and main memory always match. In the latter copy-back method, if a cache is hit when a processor writes, the write is not performed to the main memory, but only to the cache. For example, US Patent Application No. 1 filed on September 1, 1971 is related to this copy-back method.
79,376 as the basis for claiming priority
-49535 is mentioned.

However, from a performance perspective, the copy-back method does not write to the main memory when a cache is hit, so the time required to write to the main memory can be omitted, which has an advantage over the write-through method in terms of performance. . Further, by omitting the writing time to the main memory, there is an advantage that the throughput required for the main memory is reduced. Particularly in multi-processor systems, reducing memory throughput is an important point in improving system performance.

On the other hand, U.S. Patent No. 4,264,953 describes multiple processors communicating with one main memory, multiple cache memories corresponding to the multiple processors, and virtual addresses (logical addresses) from the multiple processors A multiprocessor data processing system is disclosed that has a plurality of address translation mechanisms that translate addresses into physical addresses, and an input/output device. In the system disclosed by this US patent, in order to avoid the problem that when data in a shared area of main memory is stored in the cache, the data stored in the cache no longer corresponds to updated data in the shared area of main memory. To avoid the problem that when data in the shared area of the main memory is prohibited from being written to the cache and data in the Iroka device is stored in the cache, the data stored in the cache does not correspond to the updated data of the input/output device. Therefore, the data of the input/output device is invalidated (purged) in the cache.

Conventionally, registers have been used as high-speed memories that do not guarantee consistency with the main memory.

Registers are memory specific to processors, and although they have a small capacity, they can operate at particularly high speeds.

[Problem to be solved by the invention] Conventionally, cache memory guarantees consistency with main memory, so if the amount of data to be handled exceeds the cache capacity or the data to be accessed is not in the cache, access to main memory is interrupted. This can cause performance deterioration.

However, in a multiprocessor system, it is necessary to ensure consistency when accessing the shared memory space, but it is necessary to ensure consistency when accessing the memory space that each processor uses individually. There isn't.

This point has not been taken into account in the prior art.

In the case of registers, set the register space to an appropriate size according to the user application,
It is not possible to have a register space larger than can fit within a single microprocessor. Furthermore, even in the instruction code, accesses to memory and registers are distinguished. Therefore, users and system designers cannot freely specify which data should be placed in which position on the memory hierarchy.

An object of the present invention is to provide a memory system suitable for a multiprocessor system by making use of the characteristics of a cache memory and allowing a user to set a local memory space like a register.

[Means to solve the problem]

To achieve the above objective, the memory space is divided into multiple stages. At a level where it is desired to differentiate each stage, an area determination circuit is provided to determine whether or not the access is to an area that should be consistent with the memory on the lower (main memory) side than that level.

For example, in a multiprocessor system in which a plurality of processors each having a cache device are coupled to a main memory via a system bus, the following will occur. That is, the main memory is divided into a shared area that is write-accessed by a plurality of processors and input/output devices, and a plurality of private areas that are write-accessed by each of the plurality of processors. The plurality of cache devices include an area determination circuit that determines whether an address generated from a processor accesses either a shared area or a private area. If the access from the processor is a shared area, the cache device operates according to the write-through method or the copy-back method. On the other hand, if the access from the processor is a private area, the cache device operates as if it were local memory.

Further, the cache device includes an invalidation control circuit that invalidates the data stored in the cache when the data in the shared area of the main memory is rewritten by another processor or input/output device.

[Effect] At a certain level of the physical memory hierarchy, if it is determined that the access is to an area that does not require guaranteeing consistency with the lower memory, that access will prevent access to the lower memory. Don't cause it.

Therefore, the user divides the physical memory space into multiple stages according to the physical memory hierarchy. A memory space physically located at a higher level is allocated to an area located at a logically higher level. As a result, in the worst case, the time required to access an area located logically higher is shorter than the time required to access an area located lower. Furthermore, if the user intentionally places frequently accessed data in a higher level area, the average access time will be reduced.

For example, in the case of the above-mentioned multiprocessor system, it is determined whether the address of the processor accessing the main memory or cache accesses either the shared area or the private area, based on the output of the area determination circuit.

In the former case (shared area access), the cache device operates according to the write-through method or the copy-back method according to the output of the area determination circuit. Therefore,
The consistency of the data stored in the cache and main memory is guaranteed, and other processors or input/output devices can read and access the data stored in the main memory, allowing data communication between processors or between processors and output devices. Become. If the copy-back method is used and another processor or input/output device performs a write operation to the same address in main memory, the data stored in the cache and main memory will no longer match, so invalidation control is required. The circuit invalidates the data stored in the cache.

In the latter case (private area access), the cache device operates as a local memory according to the output of the area determination circuit. In other words, if the write access address from the processor hits the cache, the write data from the processor is not written to the main memory but only to the cache, so the write operation can be completed in a short time. It becomes possible.

Other objects and features of the invention will become apparent from the following examples.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 2 shows the configuration of a shared memory type multiprocessor system according to an embodiment of the present invention. Processors 1, 2 each have a cache 3, 4 associated with it. The caches 3 and 4 are connected to the main memory bus 7,
It is connected to main memory 5 which stores instructions and data. An input/output device 6 is also connected to the main memory bus 7, and data is exchanged via the main memory bus 7.

An address translation table 8.9 exists in the processors 1 and 2, and is used for address translation from a logical address to a physical address when the processors 1 and 2 access data. The physical address after address translation is sent to the interface 14-15 between the processor 1-2 and the caches 3 and 4.

Within caches 3 and 4 there are address arrays 10.11 and data arrays 12.13. The data array 12.13 can be used as a temporary storage location for data in the main memory 5 and can also be used partially or completely as a local memory independent of the main memory 5. Address array 10.11 is data array 12.1
It holds the physical address of the data stored in 3.

FIG. 1 shows the internal structure of the cache 3.

Note that the internal configuration of the cache 4 is also the same as that of the cache 3. Throughout this embodiment, a word represents data that is 4 bytes long. 14 is a group of interface signals between the processor 1 and the cache 3, and a 4-byte wide data line 14-1
, a 24-bit wide address line 14-2 indicating an address,
and a control line 14-3. The cache 3 is also connected to the main memory path 7. The main memory bus 7 includes a 4-byte wide data line 7-1, a 22-bit wide address line 7-2 indicating a word address, and a control line 7-3.
Consists of.

The cache of this embodiment uses a direct map method with a block length of 4 bytes. Address array 10 consists of a two-vote RMA (R
andom Access Memory). The 10 bits consist of a 9 bit address tag,
This is one valid bit. Data array 12 is 8
It consists of 192 columns x 32 bits RAM. The data array 12 is a temporary storage location for data, and when valid data is stored in a certain column of the data array 12, the upper 9 bits of the address of the data are stored in the same column of the address array 10. is stored as an address tag, and the valid bit is turned on (1).

FIG. 3 shows a 24-bit address field. The 0th bit is the most significant bit and the 23rd bit is the least significant bit. The ○th bit to the 8th bit are the address tag field, and the address array 10
This is information stored in . The 9th bit to the 21st bit are column fields, and the address array 10,
Or column selection of data array 12, i.e. R
Used for AM addresses. Also, from the Oth bit to the 1st
One bit is also a region determination field and is used to determine the region. The 22nd and 23rd bits are a byte field indicating the byte position within the word.

Column field 33 of address line 14-2 from processor 1 and column field 34 of address line 7-2 of main memory bus 7 are used as addresses in the RAM of address array 10 in FIG. . 3
2.35 is the tag field of 14-2 or 7-2 and is input to the address tag comparator 22.23.

the other input of address tag comparator 22.23;
The forces are address tags 41, 42 read from two ports of address array 10.

The comparison results are reported to the cache control circuit 21 as hit/miss signals 43 and 44. 38 is the address tag field of 14-2.

Further, 36 is a path connecting the address line 14-2 on the processor side and the address line 7-2 on the main memory side.

Address 37 of data array 12 is connected to address line 14.
-2 column fields are used.

A write/read path 39 to the data array 12 connects to a data line 14-1 on the processor side and an address line 7-1 on the main memory side.

20 is an area (consistency guarantee area) for maintaining the consistency of the data between the cache memory 3.4 and the main memory 5;
This is an area determination circuit for determining an area where consistency is not guaranteed (consistency non-guaranteed area). The input to the area determination circuit 20 is the area determination field 12 of the address line 14-2.
bit (signal 30) and 12 bits (signal 46) of the area determination field of address line 7-2, and the determination results are reported on signal lines 31 and 45, respectively. Signal line 31.
45, when the value is 1, it indicates a consistency non-guaranteed area, and 0
When , it indicates a consistency guaranteed area.

The signal line 31 is input to the cache control circuit 2■, and becomes an input to the state machine 120. In addition, main memory 5
When data is transferred from the cache 3 to the caches 3 and 4, the value of the signal line 31 is set as the area identification bit of the data array 10 of the cache 3. On the other hand, the signal line 4S is used to control the invalidation of columns in the cache 3.

FIG. 4 is a diagram showing the internal configuration of the area determination circuit 20.

50 and 51 are registers each having a length of 12 bits,
50 contains the top 12 upper limit addresses of the copy back area.
A register 51 is used to set the upper 12 bits of the lower limit address of the copy back area. The value A of the upper 12 bits 30 of the address line 14-2 from the processor l and the values U and L in the register 50.51 are large lJ
It is compared in the X comparison circuit 52, and if L≦A≦U, the value of the area determination signal 31 becomes l (indicating a consistency non-guaranteed area), and when A (L or U)A, the value of the signal 31 becomes O
(indicates a consistency guaranteed area).

(Similarly, the address tag field value 46 on the main memory bus 7 is compared with the value in the registers 50 and 51. The result is reflected in the signal 45,
When the value is between L and U, the value of the signal 45 becomes 1.

) FIG. 5 is a diagram showing region division of memory space.

Memory space is hexadecimal from ooooooo to FFFFFF
It is possible to address up to Of these, ooooo
The area from o to FFFFFF is a consistency guaranteed area 60.

Further, from FF8000 to FFFFFF is a consistency non-guaranteed area of 61°62.63. In the consistency guaranteed area 60 of the main memory, processors 1. Write accesses from processor 2 and input/output device 6 occur. On the other hand, only write access from the input/output device 6 occurs to the consistency non-guaranteed area 61 of the main memory. In memory spaces FF7FFF to FFFFFF, write access from processor 1 occurs only to cache memory 3, and write access from processor 2 occurs only to cache memory 4. Consistency non-guaranteed area 62.6 from processor 1゜2
Write access to 3 is not performed to main memory. These access controls are performed by address translation table 8 or 9 in processor 1 or processor 2. For example, when the processor 1 accesses data, its logical address is translated into a physical address in the main memory 5, but the address after the translation falls within the address range of the consistency guaranteed area 60 or the consistency non-guaranteed area 62. The contents of the address translation table are set so that

Consistency non-guaranteed area 61° which is a private area accessed only by the input/output device 6; Consistency non-guaranteed area 62 which is a private area accessed only by the processor 1. The addresses of the consistency non-guaranteed area 63, which is a private area accessed only by the processor 2, overlap in the address space, but since they are each private areas, these consistency addresses corresponding to the same address in this overlapping address space Non-guaranteed area 61.
There is no need to guarantee the mutual consistency of data between 62 and 6.3. Therefore, these areas 61, 62, and 63 are the input/output devices 6. Processor l.

It can be used as an address space area for local memory for 2.

The register 50 in FIG. 4 is used to determine the above area.
A hexadecimal number U is set in the register 51, and a hexadecimal number U is set in the register 51. As a result, when the processor 1 accesses the consistency non-guaranteed area 62, the signal line 31
If the value of is 1, the cache control circuit 21 treats the cache 3 as a local memory.

However, there is one problem here. That is, all the data in the consistency non-guaranteed area must fit in the caches 3 and 4. Therefore, registers 5o and 5
The size of the consistency non-guaranteed area set using 1 is limited by the cache capacity, and in this embodiment, the maximum size is 32 kBytes.

FIG. 6 is a diagram showing the internal configuration of the cache control circuit 21 that controls the above operations. 120 is a state machine that controls read/write operations to the consistency guaranteed area and read/write operations to the consistency non-guaranteed area;
0 is a circuit that controls the invalidation operation of the address array by monitoring the main memory bus.

Inputs to the state machine 120 include a set of state signals 110 indicating the current state, a hit/miss signal 43 that reports the result of comparing the address tag on the processor side with the tag in the address array 10 read from the address array 10; The updated valid bit signal 100-a, the updated bit signal 100-b, and the area determination result report signal 31. Interface control input signal group 1, 4-3-a between processor and cache, memory bus control signal 7-3-a
It is. The interface control input signal 14-3-a consists of an access start signal indicating that the processor has started access, and a read/write identification signal. The memory bus control signal 7-3-a is a signal that reports the end of the memory bus cycle.

The output of state machine 120 is stored in address array 10 . Internal control signal group 130 that controls read/write of data array 12, memory bus control signal group 7-3-b, interface control output signal 1
4-3-b.

The memory bus control signal group 7-3-b consists of a memory bus cycle start signal and a read/IF write instruction signal. Further, the interface control output signal 14-3-b is an access completion signal for the processor.

State machine 120 responds to each input signal to provide an output signal that implements the control operation. In particular, this state machine 120 includes a region determination result report signal 31.
is input, the control operation for access to both the consistency guaranteed area and the consistency non-guaranteed area is realized only by this state machine 120 based on this determination result.

Circuit 140 for controlling invalidation operation of address array 10
The input is a hit/dot that reports the result of comparing the address tag on the main memory bus with the tag in the address array.
A miss signal 44 and a signal 4 that also reports the area determination result of the address tag field value on the main memory bus 7
5. A valid bit signal 100-c read from the address array according to an address on the main memory bus, and a group of memory bus control signals 7. -3- b. The memory bus control signal group 7-3-b consists of a memory bus start signal and a read/write instruction signal.

The circuit 140 has memory bus control signal group 7-3--from which data is written to the main memory from another mask on the main memory bus. Recognizing that, the signal 44 at that time
and 100-c, it sends an invalidation control signal 150 for invalidating the address array.

The control operation of the cache control circuit 21 of the cache memory 3 will be explained below with reference to the flowcharts of FIGS. 7, 8, and 9.

■, Cache by processor 1 3. main memory 5
Read: It is determined whether the address signal generated from the processor 1 is an access to a consistency guaranteed area or a consistency not guaranteed area (step 700 in FIG. 7).

(1) Read from consistency guaranteed area.

Write access is performed in the consistency guaranteed area using a write-through method.

In step 700 of FIG. 7, the value A of the upper 12 bits of the address signal generated from the processor
Alternatively, when the access point is USA, the value of the area determination signal 31 of the comparison circuit 52 in FIG. This area determination signal 3
While 1 is being output from the comparator circuit 52, the process moves to the cache search operation of step 701 in FIG.

In the cache search operation of step 701, the address array 10 of the cache 3 is searched, and if the result is a hit (that is, the value 32 of the address tag field of the access address and the value read from the address array 10). If the value 41 matches, a hit signal 43 is generated.
is asserted and the valid bit read at the same time as the address tag is 1), the state machine 120 of the cache control circuit 21 of the cache 3 outputs the consistency guaranteed area determination signal 31. In response to the hit signal 43, etc., the process moves to step 702 in FIG.

In this step 702, data is read out from the data array 12 onto the data line 14-1 at high speed according to the column field of the address signal generated from the processor l, and this read data is transferred to the processor l. .

On the other hand, in the cache search operation at step 701,
If there is no hit as a result of the search, the state machine 120 of the cache control circuit 21 of the cache 3 moves the process to step 703 in FIG. 7 in response to the consistency guaranteed area determination signal 31, miss signal 43, etc.

In this step 703, address array 12
The valid bit and area identification bit read from the area are determined. Data read from address array 12 is accessed using only the column field of address signal 14-2 on the processor side. Therefore, even if a cache miss is determined in step 701, valid data with a different address tag field value may be held in that column.

The fact that the valid bit read from the address array 12 at the time of a cache miss read is 1 and the area identification bit is 1 means that the cache 3 stores data corresponding to the column field of the address signal from the processor 1. Indicates that the data is in a non-consistent area. In this case, it is necessary to hold/retain the data held in the cache memory, and the process moves to step 705 in FIG. On the other hand, if the valid bit is 0 (that is, invalid data is stored) or the area identification bit is O
(That is, the data is in the consistency guaranteed area), the data in that column in the cache memory can be updated, and the process moves to step 704 in FIG.

In this step 704, the state machine 12
0 starts a memory bus cycle and the address from processor 1 is provided via signal line 36 to address line 7-2 of main memory bus 7. According to this address,
The data in the main memory 5 is read and the data line 7-1
At the same time that data is written to data array 2 via data line 14-1, the data is transferred to processor 1 via data line 14-1. On the other hand, address array 1o
The address tag is written in the corresponding column and
1 is written to the valid bit and O is written to the area identification bit.

Meanwhile, in step 705, the state machine 12
0 starts a memory bus cycle and the address from processor l is applied via signal line 36 to address M7-2 of main memory bus 7. According to this address,
The data in the main memory 5 is read and the data line 7-1
The data is transferred to the processor 1 via the data line 14-1. However, in step 705, step 7
Unlike 04, writing to cache 3 is not performed.

(2) Reading from a non-consistent area: When the value A of the upper 12 bits of the address signal generated from the processor 1 is L≦A≦U in step 700 of FIG. 7, the comparison shown in FIG. The value of the area determination signal 31 of the circuit 52 becomes 1, indicating that the access is to the consistency non-guaranteed area 62. While this area determination signal 31 is being output from the comparison circuit 52, the process shifts to the cache search operation of step 706 in FIG.

In the cache search operation in step 706, the address array 10 of the cache 3 is searched, and if the result is a hit, the state machine 120 of the cache control circuit 21 of the cache 3 sends the consistency non-guaranteed area determination signal 31. In response to the hit signal 43, etc., the process is shifted to the above-described step 702 in FIG.

On the other hand, in the cache search operation at step 706,
If there is no hit as a result of the search, the state machine 120 of the cache control circuit 21 of the cache 3 moves the process to step 707 in FIG. .

In this step 707, temporary data is transferred from the cache 3 to the processor 1. The temporary data may be 0 or a value read from the data array 12 of the cache 3. This is because a cache miss occurs when attempting to read data from an area where consistency is not guaranteed (step 7o7), which means that an attempt is made to read data that has not been set in the first place. This is because it can be determined that there is an error in the program.

■, Cache by processor 1 3. main memory 5
Write to: It is determined whether the address signal generated from the processor 1 is an access to a consistency guaranteed area or a consistency not guaranteed area (step 800 in FIG. 8).

(3) Writing to the consistency guaranteed area: In step 800 of FIG. 8, the value A of the upper 12 bits of the address signal generated from the processor 1 is
Alternatively, when U<A, the value of the area determination signal 31 of the comparison circuit 52 in FIG. 4 becomes O, indicating that the access is to the consistency guaranteed area 60. This area determination signal 3
While 1 is being output from the comparator circuit 52, the process moves to the cache search operation of step 801 in FIG.

In the cache search operation of step 801, the address array 10 of the cache 3 is searched, and if there is a hit as a result (that is, the value 32 of the address tag field of the access address and the address array 10 are read out). If the value 41 matches, a hit signal 43 is generated.
is asserted and the valid bit read at the same time as the address tag is 1), the state machine 120 of the cache control circuit 21 of the cache 3 outputs the consistency guaranteed area determination signal 31. In response to the hit signal 43, etc., the process moves to step 802 in FIG.

In this step 802, write data is written to the data array 12 of the cache 3 according to the address signal generated from the processor 1. On the other hand, the state machine 120 starts a memory bus cycle and writes write data to the main memory 5 as well.

On the other hand, in the cache search operation at step 801,
If there is no hit as a result of the search, the consistency guaranteed area determination signal 31 of the state machine 120 of the cache control circuit 21 of the cache 3 is output. In response to the miss signal 43, etc., the process moves to step 803 in FIG.

In step 803, write data is not written to the data array 12 of the cache 3. Meanwhile, state machine 120 starts a memory bus cycle and writes write data to main memory 5 according to the address from processor 1.

(4) Write to consistency non-guaranteed area: In step 800 of FIG. 8, the value A of the upper 12 bits of the address signal generated from the processor 1 is L≦A.
When ≦U, the value of the area determination signal 31 of the comparison circuit 52 in FIG. 4 becomes 1, indicating that the access is to the consistency non-guaranteed area 62. In this case, the process moves to step 804 in FIG.

In step 804, write data from processor 1 is written to data array 12 of cache 3. At this time, the write data from the processor 1 is not written to the main memory 5, so the write operation can be completed in a short time. Furthermore, since the data to be rewritten at this time cannot be accessed directly from other devices, there is no need to input an address to the address line 7-2 in order to perform invalidation processing, which will be described later. the result,
The bus traffic of the memory bus 7 is reduced, and the processing of other devices is not adversely affected.

(2) Processing for memory write by another processor 2 or input/output device 6: After the processor 1 writes the same data to the cache 3 and the write-through area 60 of the main memory 5, the other processor 2 or input/output device 6 may write other data to the main memory 5 at the same address location as the address of the above data. In this case, cache 3
Since the correspondence between the stored data and the main memory 5 is no longer guaranteed, it is necessary to invalidate the data stored in the cache 3.

For this purpose, the address array 10 of the cache 3 monitors the write address to the main memory 5 from the processor 2 or the input/output device 6 via the main memory bus 7.

The write address is the address line 7-2 on the main memory side.
, and its column field goes into one boat address 34 of address array 10. The control circuit 140 of the cache control circuit 21 of the cache 3 determines whether or not writing has been done to the main memory 5.
is done by monitoring control line 7-3-b.

Comparator 23 compares address tag 42 read from address array 10 with the value of address tag field 35 of address line 7-2.

If these values match, bit signal 44 is asserted, and the valid bit read at the same time is 1, this valid bit is sent via control signal line 150 to disable that column. Write 0. These operations are controlled by the cache control circuit 21.

The flow of the above invalidation process is shown in the flowchart of FIG.

When a write address is supplied from the address line 7-2 on the main memory side, the process moves to step 900,
In this step 900, a cache search of the address array 10 based on the write address is performed.

As a result of this search, the hit signal 44 is detected from the output of the comparator 23.
When is output, the process moves to the invalidation process of step 901. In this step 901, the address
O is written to the valid bit of the corresponding column of array 10. On the other hand, if the cache search result in step 900 is a miss, the process is ended without going through step 901 for invalidation. This operation causes the write
Cache in the through area 3. The consistency of data in cache 4 and main memory 5 is maintained.

The present invention is not limited to the above embodiments, and various modified embodiments can be adopted.

For example, in FIG. 2, the number of processors 1, 2 and caches 3, 4 is not limited to two, but three.
Needless to say, data processing capacity can be enhanced by connecting more than one. In FIG. 2, processor 1 and cache 3 are formed in one microcomputer chip, and processor 2 and cache 4 can be formed in another microcomputer chip. Furthermore, it is also possible to form all the components shown in FIG. 2 in one microcomputer chip.

In this example, the consistency guaranteed area and consistency non-guaranteed area are set to 1.
However, if the cache memory is divided into multiple parts and it is possible to independently enable, clear, and control whether or not to use them locally, it becomes possible to handle multitasking. If the cache memory is of a set-associative type with multiple ways, these controls can be performed for each way, for example. In that case, some ways are used as local memory and the rest are used as regular cache memory. When switching tasks, the operating system saves the states of these ways and manages them so that different tasks do not accidentally use the same local memory. When resuming task processing, the local memory can be used again based on the saved information.

In addition, in this embodiment, the write-through method is used for all consistency guaranteed areas, but this area is further divided into an area controlled by the write-through method and an area controlled by the copy-back method. Is possible. In that case, the area determination circuit distinguishes between the consistency non-guaranteed area, the consistency guaranteed area (copy-back area), and the consistency guaranteed area (write-through area), and the cache memory is controlled according to the determination result. It turns out. In this way, accesses to the main memory can be further reduced by placing data that is shared among multiple processors but rarely accessed by other devices in the copy back area.

[Prior Art] According to the present invention, a user can set a cache memory that can be accessed at high speed to be used as a local memory. As a result, average data access time is reduced, path traffic is reduced, and system performance is improved.

The effects of the present invention are more noticeable in multiprocessor systems. System performance is improved because accesses to local memory space do not affect the cache processing of other processors. In addition, the local space used by each processor (consistency-unguaranteed area)
Since the same address can be specified in the memory space, programs can be standardized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the internal configuration of a cache device according to an embodiment of the present invention, FIG. 2 is a block diagram of a multiprocessor data processing system according to an embodiment of the present invention, and FIG. 3 is a block diagram according to an embodiment of the present invention. FIG. 4 is a block diagram of an area determination circuit in a cache device according to an embodiment of the present invention; FIG. 5 is a diagram showing area division of main memory in the system of FIG. 2. , FIG. 6 is a block diagram of a cache control circuit in a cache device according to an embodiment of the present invention, FIG. 7 is a flowchart explaining a read operation of a multiprocessor data processing system according to an embodiment of the present invention, and FIG. 8 is a block diagram of a cache control circuit in a cache device according to an embodiment of the invention. FIG. 9 is a flowchart illustrating the write operation of the multiprocessor data processing system according to the embodiment of the present invention. FIG. 9 is a flowchart illustrating the invalidation operation of the multiprocessor data processing system according to the embodiment of the present invention. 1.2... Processor, 3, 4... Cache, 5
... Main memory, 6... Iroka device, 7...
・Memory bus, 8, 9...address converter, 10.1
1...Address array, 12.13...Data array, 14゜15...Processor-cache signal line, 14-1...Data line, 14-2, Address line, 1
4-3... Control line, 30... Area determination field (
processor), 31... area determination signal (processor)
, 45... area determination signal (main memory), 46...
- Area determination field (main memory), 5o... Upper limit address register, 51... Lower limit address register, 52... Size comparator, 120... State machine, η2[2]! ti3 (2) 'fJ40 VI5 TaY z 口5q Figure f37 口 口 口 口

Claims (1)

[Claims] 1. A multiprocessor data processing system comprising: (1) first and second processors that generate addresses; (2) a bus; and (3) a main unit coupled to the bus. (4) an input/output device coupled to the bus; (5) a first cache device coupled between the first processor and the bus; (6) the second processor. and a second cache device coupled between the main memory and the bus, the main memory being a shared area that is write accessed by the first processor, the second processor, and the input/output device. and a private area that is write-accessed by the first or second processor, and each of the first and second cache devices is divided into: (A) a private area that is write-accessed by the first or second processor; an area determination circuit that determines whether the generated address accesses either the shared area or the private area; (B) data to the cache device and the main memory in response to the output of the area determination circuit; and a cache control circuit that controls storage, and when an address generated from the first or second processor accesses the shared area, the output of the cache control circuit is written to the cache device. A data write operation is performed using a through method or a copy back method, and when an address generated from the first or second processor accesses the private area, the output of the cache control circuit is used to write data to the cache device. A multiprocessor data processing system characterized by having data write operations performed as a local memory. 2. The multiprocessor data processing system according to claim 1, wherein when the second processor or the input/output device rewrites the data in the shared area of the main memory, the A multiprocessor data processing system, wherein a cache control circuit invalidates data stored in the shared area of the first cache device. 3. first and second processors that generate addresses; a bus; a main memory coupled to the bus; and an input/output device coupled to the bus; A shared area that is write accessed by a processor, the second processor, and the input/output device, and a shared area that is write accessed by the first or second processor.
A cache device for use in a multiprocessor data processing system comprising: a first cache coupled between the first processor and the bus; a second cache device coupled between the second processor and the bus, each of the first and second cache devices comprising: (A) a second cache device coupled between the second processor and the bus; (B) an area determination circuit that determines whether the address generated from the area accesses either the shared area or the private area; and a cache control circuit that controls data storage, and when an address generated from the first or second processor accesses the shared area, the output of the cache control circuit is written to the cache device. - A data write operation is performed using a through method or a copy back method, and when an address generated from the first or second processor accesses the private area, the output of the cache control circuit is transmitted to the cache device. A cache device characterized in that a cache device is configured to perform a data write operation as a local memory. 4. The cache device according to claim 3, wherein the second
When the processor or the input/output device rewrites data in the shared area of the main memory, the cache control circuit of the first cache device invalidates the data stored in the shared area of the first cache device. A cache device characterized by: