JPH04163966A - Vertical eeprom and its writing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a vertical (or NAND type) EEPROM and its writing method, and relates to a technique that is effective when used in, for example, a device with a large storage capacity. It is.

[Conventional technology]

N formed by connecting nonvolatile memory transistors in series
EEPROMs having an AND (NAND) structure are known.

The NAND structure memory cell has two selection MOS F
It is composed of an ET and a plurality of nonvolatile memory transistors sandwiched between the ET. There are eight storage transistors, usually arranged in series. Source side selection MO5FET
is provided to cut off the through current during writing.

One erase/write cycle consists of one block-batch erase and several page writes.

Input data is launched into a launch circuit and then written. - Bulk erase requires high voltage (
For example, this is done by supplying 17■) and supplying Ov to the via line. As a result, electrons are injected into the floating gate, increasing the threshold voltage of the nonvolatile storage transistor. Write operations are performed from the source side. Ov is supplied to the control gate of the selected cell, OV is supplied to the control gate of the non-selected storage cell which is provided on the source side of the selected cell and has been written, and OV is provided to the control gate of the unselected memory cell which is provided on the drain side of the selected cell and which has not yet been written. A high voltage (for example, 22
■) Supply. Then, when writing data "1", an intermediate potential (for example, 11V) is applied to the bit line.

In this case, there is no movement of electrons in the floating gate, and the threshold voltage remains high. When writing data "0", a high voltage (for example, 22 V) is applied to the bit line. In this case, electrons are emitted from the floating gate to the drain side by a tunnel current, and the threshold voltage is lowered. Reading of the above memory cell is performed using vertical type R.
This is performed in the same manner as the OM read operation.

Regarding such a NAND structure EEPROM, 1
989 Institute of Electronics, Information and Communication Engineers Technical Report SDM89-9~1
8, pages 55-60.

[Problem to be solved by the invention]

In the above-mentioned EEPROM, writing is performed using a tunnel current, and bit defects are likely to occur due to destruction of the relatively thin tunnel insulating film, which poses reliability problems. Furthermore, when a memory cell whose tunnel insulating film is destroyed is selected and a write operation is performed, a relatively high voltage is applied between the control gate and drain of the unselected memory cell, which is provided on the source side and has already been written. There is a possibility that the correct stored information written above may be destroyed.

The purpose of this invention is to develop a vertical EEPRO that achieves high reliability.
The goal is to provide M.

Another object of the present invention is to provide a writing method for a vertical EEPROM that can prevent erroneous writing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an ECC circuit is built into a vertical EEPROM consisting of a memory array in which nonvolatile storage transistors that can be electrically written and erased are connected in series. In addition, in a write operation to a memory array in which non-volatile memory transistors that can be electrically written and erased are connected in series, the word line to which the non-volatile memory transistors are connected immediately after writing is completed is connected to the memory array. A predetermined intermediate voltage is applied while writing to the nonvolatile storage transistor on the drain side.

[For production]

According to the above-mentioned means, even if a poor focus occurs, it can be corrected by incorporating the ECC. Also,
By supplying an intermediate potential to the control gate of an unselected cell on the source side of the selected cell during writing, a large voltage can be generated between the gate and drain of the unselected cell even if the tunnel insulating film is broken in the selected cell. Since it is not supplied, erroneous writing can be prevented.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a vertical EEPROM according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The memory array is divided into four memory array MARY1.
It is composed of MARY4. Upper memory array MARY1. MARY2 and lower memory array MARY
3. Row decoder XDCRI, XD between MARY4
CR2 is placed.

The left memory array MARYI, MARY3 and the right memory array MARY2. A sense amplifier SA and a column decoder YDCRI are connected to MARY4.

YDCR2 is placed. In the same figure, these two blocks are combined into one block SA&YDCR1°SA&YDC
It is expressed as R2.

The peripheral circuit includes a Nando cell control port for generating block erase pulses and continuous programming pulses! INc
c, a booster circuit VPPG for obtaining a high voltage during erase/write operations, a row address buffer XADB, a column address buffer YADB, a control circuit C0NT, an input/output cover sofa ■OB, and an error detection/output correction circuit ECC.
(hereinafter simply referred to as an ECC circuit) is provided.

Row address buffer XADB receives address signal A O
-A7, the lower three bits of address signals AO to A2 are supplied to the NAND cell control circuit NCC and used to generate continuous programming pulses.

The remaining address signals mentioned above are sent to the row decoder XDCR1,
The signal is supplied to XDCR2 to form a word line selection signal in units of 8 words. The column address buffer YADB receives an 11-bit address signal consisting of address signals A8 to A18, and outputs the column decoders YDCR1 and YDCR.
2. Forms an internal address signal that is supplied to

The control circuit C0NT generates necessary control signals and timing signals according to the operation mode specified by the chip enable signal C.

The input/output circuit 10B inputs write data during a write operation, and outputs a read signal during a read operation.

The ECC circuit generates a parity bit for write data based on a certain logical operation formula, and causes the write data and parity bit to be written into a memory cell as one word. Then, using the parity focus read together with the stored data, error detection and correction of the stored data is performed, and the data is output.

FIG. 2 shows a circuit diagram of a main part of an embodiment of the memory array MARY.

The vertical structure memory cell has two selection MOSFETs Q1
It is composed of eight nonvolatile memory transistors Qm sandwiched between Q2 and Q2. For example, when data is written and read in units of 8 bits (1 byte), the bit lines are composed of 8 bit lines BO to B7, but as in this embodiment, an ECC circuit is built in and In order to also store the parity bits generated by , a bit line for 4 bits is added. In other words, when performing error detection and correction on 1 bit out of 8-bit data, in other words, when using a 1-bit correction simple Hamming code method, 4 parity bits are required, and the total number of bits is 12 bits consisting of 8 information bits and 4 check bits, such as lines BO to Bll, are stored in the memory array MARY as one word (IW).

FIG. 3 shows a cross-sectional view of an element structure in the bit line direction of an embodiment of a memory cell having a vertical structure.

The first gate oxide film of the nonvolatile memory transistor Qm is
It is composed of a tunnel insulating film with a film thickness of about 10 (runs). Although not particularly limited, the above selected MO3FETQI
, Q2 and the nonvolatile memory transistor Qm are formed on a P-type substrate (P-3UB), and a wiring layer made of aluminum or the like is formed on the above-mentioned series memory cells in parallel to connect them to other focus lines. It runs as a bit line.

FIG. 4 shows a timing diagram for explaining the erase/write operation to the vertically structured memory cell.

In the EEPROM of this embodiment, an erase operation is performed prior to a write operation.

That is, if writing is instructed by a combination of signals CE and OE, an erasing operation is automatically performed. Ov is supplied to the bit line BL, and selection M on the bit line BL side
A high voltage such as about 17V is supplied to the selection gate line S01 to which the gate of the OS FETQ 1 is connected. Control gate line (word line) cci to CG8 to which the control gate of the nonvolatile memory transistor is connected
is supplied with a high voltage such as 17V similar to the above.

A relatively low potential such as 5V is supplied to the selection gate line SG2 to which the gate of the selection MO3FET Q2 on the ground potential side is coupled.

As a result, a high voltage is supplied to the control gate of the nonvolatile storage transistor Qm, so a tunnel current flows from the substrate toward the floating gate, and electrons are injected into the floating gate. In response to this, the threshold voltage of storage transistor Qm increases to have a high threshold voltage.

A write operation is performed subsequent to the above-mentioned batch erase operation. A write operation is performed from the source side of storage transistor Qm. Writing is first performed to the storage transistor Qm on the ground potential side. In other words, the storage transistor coupled to the control gate line CG8 has a logic "
When writing 1'', an intermediate voltage such as IIV is supplied to the bit line BL.A high voltage such as 22V is supplied to other non-selected cells (control gates of memory transistors Qm) ICGI to CG7. Ru.

As a result, an intermediate voltage such as IIV on the pin 1-line BL is transmitted to the selected MO3FET QI and the drain of the storage transistor Qm coupled to the control gate line CG8 through the unselected cell. Since the control gate line CG8 is supplied with OV when it is selected, no tunnel current flows because a high electric field does not act between the floating gate and the drain.

That is, storage transistor Qm maintains a high threshold voltage. Note that the selection MO3FET Q2 on the ground potential side is turned off in response to the selection gate line SG2 being set to 0. This prevents current from flowing from the focus line toward the ground potential during the write operation.

Next, writing is performed on the storage transistor coupled to control gate line CG7. When writing logic “0” to this storage transistor, the bit line BL is
An intermediate voltage such as 2V is supplied. Other unselected cells (
Storage transistor) Qm control gate line CGI
~CG6 is supplied with a high voltage such as 22V. As a result, a high voltage such as 22V on the pinto line BL is transmitted to the drain of the storage transistor Qm coupled to the control gate line CG7 through the selected MOS FETQ1 and the unselected cells. Since Ov is supplied to the control gate line CG7 when it is selected, a high electric field acts between the floating gate and the drain, a tunnel current flows, and electrons from the floating gate are emitted. That is, the storage transistor Qm changes from a high threshold voltage (positive threshold voltage) to a low threshold voltage (negative threshold voltage) due to the emission of electrons from the floating gate.

At this time, in the conventional vertical EEPROM, 0 is supplied to the control gate line CG8, which has already been written. If Ov is supplied to the control gate line CG8 after writing has been completed in this manner, the following problem occurs. As mentioned above, the first gate oxide film of a memory transistor is extremely thin, and repeated erasing and writing several times can cause breakdown of the insulation film and short circuit between the drain and floating gate. Highly sexual. If there is such a defective cell, a high voltage for writing is transmitted to the drain side of the storage transistor after the writing has been completed, and a tunnel current flows, resulting in a logic "1".
The memory of is inverted to look like logic "0".

Therefore, in the write method of this embodiment, the potential of the control gate line CG8 immediately after the write is set not to Ov but to an intermediate potential such as 11V. By doing this, even if gate insulating film breakdown occurs in the selected cell coupled to the control gate line CG7,
Erroneous writing as described above will not occur.

Note that the information stored in the storage transistor that has undergone dielectric breakdown as described above is output as an error as it is, but in the vertical EEPROM of this embodiment, error detection and correction are performed by the ECC circuit described above. be.

Thereafter, the write operation is similarly performed in the order of the source side, and when writing to the storage transistor of the control gate line CG6, the potential of the control gate line CG7 to which the storage transistor provided on the source side is coupled is set to an intermediate level. The potential is set to 11■, and since the storage transistor to which this intermediate potential is applied has a voltage clamping effect, the control gate 1cG8 to which the storage transistor to which writing has been completed before is connected is set to a potential such as Ov. It is. Thereafter, writing is similarly performed in the order of control gates CG5 to CGI.

FIG. 5 shows a timing diagram for explaining the read operation from the vertically structured memory cell.

The read operation of the vertical EEPROM of this embodiment is basically the same as that of a vertical mask ROM, and the control gate line CG6 corresponding to the memory cell to be selected is set to Ov, and other unselected cells are controlled. Gate line CGI
~CG5 and CO2° Set to high level such as CG8t-5V. An unselected cell is turned on regardless of stored information in response to the control gate line corresponding to it being set to a high level such as 5V. When logic "1" is written to the storage transistor connected to the control gate line CG6 as described above, the storage transistor is turned off because it has a high threshold voltage (enhancement mode). As a result, a current path is not formed in the series cells, so the precharge potential vP of the bit line VL remains at a high level (precharge level). When a logic "0" is written, the storage transistor is turned on because it has a low threshold voltage (depletion mode). As a result, a current bus is formed in the series cells, and the precharge potential vP of the bit line VL is
A sense amplifier (not shown) senses and outputs the high level and low level. 6 shows a block diagram of an embodiment of the input/output cover sofa IOB and the ECC circuit.

The input/output buffer IOB is composed of an input buffer IB and an output buffer sofa. The input terminal of the input buffer IB and the output terminal of the output buffer sofa OB are connected to corresponding data terminals DO to D7, respectively.

On the other hand, 8-bit write data input from input buffer IB is supplied as is to write circuit WAI. On the other hand, the write data is supplied to a parity bit generation circuit PBG, where 4 parity bits are generated.

Parity bits D8 to Dll are generated by the following equations (1) to (4), respectively.

D8 = DOeD1eD269D3eD5 --
...(t)D9 = DOofEEID169D2eD4
ΦD5eD6 ・---・(21D10=DOeD1
$D3$D4eD6eD7 - ・--(3)D11
=DO■D2eo3$D4eo7 − ・・−(
4) The four bits consisting of parity bits D8 to Dll generated according to the above equations (1) to (4) are used by the write circuit W.
A2 is supplied. When performing a continuous 8-byte (word) write operation as described above, the write circuit WAI
and WA2 are provided with a latch circuit for 8 words, and write data "0" and "1" of the output signal of this latch circuit are provided.
” and in synchronization with the selection timing of the control gate line, apply a high voltage or intermediate voltage to the bit lines BO to Bl.
1. In addition, a configuration may be adopted in which write data is input from the outside in synchronization with the selection timing of the control gate line. In this case, considering the signal delay due to the operation of the parity bit generation circuit PBG,
The selection timing of the control gate line may be controlled in synchronization with the input of write data including the parity bit.

By the read operation, the stored data and the parity bit are outputted through sense amplifiers SAI and SA2, respectively. The storage data consisting of 8 bits and the parity bit consisting of 4 bits are referred to as parity check circuit P.
It is input to CK. This parity check circuit PCK forms parity check bits e1 to e4 according to the following logical formulas (5) to (8).

e 1 =DO■DI(iEID2fE9D3(E)D
5ΦD8...(5)e2=DO■D1fEEI
D2(f)D4e)D5(3)D6eD9...(
61e 3 =DOeD169D3eD469D6C9
D71E9D10 ・ ・ ・(7) e 4 = DO
$D2eD3eD469D7eD11 ・ ・
(8) The correspondence between the parity check bits e1 to e4 and defective bits is shown in Table 1 below.

Table 1 The above parity check bits e1 to e4 are supplied to a defective bit detection circuit ERR, and defective bit detection signals bO to b7 are formed according to Table 1 above. That is, when there are no defective bits, all of the detection signals bO to b7 become 0, and the stored data read out through the sense amplifier SA1 is directly transmitted to the output buffer sofa OB through the error correction circuit EC consisting of an exclusive OR circuit. When there is a 1-bit defect, the defective bit detection signals bO to b7
The corresponding focus becomes 1, and the data read from the sense amplifier SAI is inverted and corrected by the corresponding exclusive OR circuit.

The defective rate of a chip without a built-in ECC circuit is determined by the following equation (9).

Here, the storage capacity is assumed to be 1M bits, and the probability that a particular bit becomes defective is assumed to be Q.

p o = 1(t −Q ) I (14@S 'F
h (9) On the other hand, when an ECC circuit is built in, there is a case where there are two or more defective bits in the same row or column among 8×12=96 bits. If the probability that the above 96 bins become defective is Qa, then Qa=1 (I Q) 9h qic+・Q(
I Q)"Cq6Cz 1zCt" *C2-@C
I'IzC1)XQ"-(1-Q)"
-...Ql) Therefore, the chip failure rate Pa is expressed as the following formula αυ.

Pa =1- (1-Qa) ””'-
--・--(Conventional vertical EE without built-in IDECC circuit)
If the PROM defect rate is 10%, a vertical EEPROM with a built-in ECC circuit as in this example will have o,
t p p m is greatly improved. In particular, although the above-mentioned vertical EEPROM is suitable for increasing storage capacity due to its structure, since erasing and writing are performed by tunnel current, the first gate insulating film is inevitably formed thin, resulting in gate dielectric breakdown. This tends to cause a large number of chip failures, leading to a large problem in terms of yield. However, with the built-in ECC circuit as described above, while taking advantage of the large storage capacity of the vertical EEPROM,
A nonvolatile storage device with high reliability can be obtained. Considering that the incidence of defective bits is relatively high as mentioned above, the use of the above writing method can prevent writing errors caused by defective focusing. It can further improve reliability and reduce the defective rate of chips.

The effects obtained from the above examples are as follows. That is, by incorporating the (11ECC circuit), it is possible to achieve the effect of improving reliability and yield while making use of the large storage capacity that is a feature of vertical EEPROM.

(2) As a writing method for a memory array in which nonvolatile storage transistors that can be electrically written and erased are connected in series, the word line to which the nonvolatile storage transistors are connected immediately after writing is completed is By supplying a predetermined intermediate voltage while writing is being performed to the next nonvolatile memory transistor provided on the drain side of the nonvolatile memory transistor, even if there is a gate insulating film defect in the selected cell during the writing, Since a high electric field that would cause a tunnel current to flow between the gate and drain of the non-selected cell for which the writing has been completed does not occur, it is possible to prevent erroneous writing.

(3) The effects of (1) and (2) above work synergistically to create a vertical EE with high reliability against data rewriting.
The effect is that a PROM can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say. For example, a parity bit is added to the 8-bit unit of data, but it is also possible to write and read multiple bytes of data in a memory array such as 16 bits or 32 bits, and add a parity bit to these. You can.

By doing so, the ratio of parity bits to unit data can be reduced, so that the actual storage capacity of the memory array can be increased. Even when the above-mentioned writing method is adopted, data may be input/output to/from the outside in units of 8 bits. In other words, when writing, data is written in units of pages consisting of the above-mentioned multiple bytes, and reading from the memory array is performed in units of pages, but when outputting to the outside, a specific byte is selected and output. The specific configuration and layout of the memory array and its peripheral circuits can take various embodiments.

The present invention can be widely used as a vertical EEPROM and its writing method, and the vertical EEPROM may be installed in various digital integrated circuits such as microcomputers and custom LSIs.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, with the built-in ECC circuit, vertical EEPRO
It is possible to improve reliability and yield while taking advantage of the large storage capacity that is a feature of M. In addition, vertical EEPR
The OM write method uses a predetermined period of time while writing is being performed to the next nonvolatile storage transistor provided on the drain side of the word line to which the nonvolatile storage transistor is connected immediately after writing is completed. By supplying an intermediate voltage, even if there is a defect in the gate insulating film in the selected cell during the writing process, a high electric field is applied that causes a tunnel current to flow between the gate and drain of the non-selected cell after the writing process has been completed. This prevents erroneous writing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a vertical EEPROM according to the present invention, FIG. 2 is a main circuit diagram showing an embodiment of a memory array MARY, and FIG. 3 is a memory having a vertical structure. FIG. 4 is a sectional view of the element structure in the bit line direction showing one embodiment of the cell; FIG. 4 is a timing diagram for explaining erase/write operations to the vertically structured memory cell; FIG. A timing diagram to explain the read operation from the memory cell of the structure,
FIG. 6 is a block diagram showing one embodiment of the input/output buffer IOB and the ECC circuit. MARYI~MARY4...Memory array, XDCRl
, XDCR2...Row decoder, SA...Sense amplifier, YDCR1, YDCR2...Column decoder, XAD
B: Row address buffer, YADB: Column address buffer, NCC: NAND cell control circuit, VPP
G: Boost circuit, C0NT: Control circuit, IOB: Input/output cover sofa, ECC: Error detection and correction circuit, IB...
Input cover sofa, OB...output cover sofa, PBG...parity bit generation circuit, WAI, WA2...write circuit, PCK...parity check circuit, ERR...defective bit detection circuit, EC...error correction circuit, Ql, Q2・−
Select MO3FET, Qm...Nonvolatile memory transistor.

Claims (1)

[Claims] 1. A vertical EE comprising a memory array in which non-volatile storage transistors that can be electrically written and erased are arranged in series, and an ECC circuit.
PROM. 2. Claim 1, wherein the memory array stores data bits and parity bits added to the data bits in a plurality of memory cells connected to the same word line. Vertical type E described in section
EPROM. 3. A memory array is provided in which non-volatile memory transistors that can be electrically written and erased are connected in series, and an intermediate potential and a high voltage according to the written data are applied to one end of the series-type non-volatile memory transistors. The potential of the word line to which the control gate is connected is lowered in order from the nonvolatile storage transistor on the source side among the nonvolatile transistors in the series configuration, and writing is performed, and the nonvolatile storage transistor immediately after writing is completed. A vertical EEPROM characterized in that a predetermined intermediate voltage is supplied while writing is being performed to the next nonvolatile memory transistor provided on the drain side of the word line to which the word line is coupled. writing method. 4. Prior to the write operation, a low potential is supplied to one end of the non-volatile memory transistors in series, and a relatively high potential is supplied to all word lines to which the control gates of the non-volatile memory transistors are connected, all at once. 2. The vertical EEPROM writing method according to claim 1, wherein the writing method is for performing an erasing operation.