JPH04169937A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve the efficiency of a program memory and to shorten the interrupt handling time by providing an interrupt control circuit with a multiplexer which inputs the output of a means, which sets an interrupt address to an area other than an instruction memory with respect to each interrupt factor, to a program counter. CONSTITUTION:This processor is provided with a program counter 1, a stack 2, an instruction ROM 3, an instruction decoder 4, an interrupt detecting circuit 5, an interrupt control register 6, a stack pointer 7, an address setting circuit 8, and a multiplexer 9. The address setting circuit 8 consists of a read only memory including addresses ADD.1, ADD.2,...ADD.K, and ADD.n and sets an interrupt address for each interrupt factor. The multiplexer 9 uses the interrupt factor detected by the interrupt detecting circuit 5 as a select signal to input the output of the address setting circuit 8 to the program counter 1. Thus, the efficiency of the program memory is improved and the interrupt handling time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to microprocessors, and particularly to a microprocessor having a function of detecting the occurrence of an interrupt factor and controlling execution of interrupt processing.

[Conventional technology]

In conventional microprocessors, the start of interrupt processing is determined by a process stored in memory at an address specified for each interrupt factor, whether it is an externally caused interrupt caused by an interrupt input terminal or an internally caused interrupt caused by a timer, etc. Generally, it is executed from an instruction.

When the interrupt detection circuit in the microprocessor detects that an interrupt factor has occurred, if the interrupt caused by the factor is enabled, multiple interrupts are disabled, the return address is stored in the stack, and the stack The interrupt address, which is the 0 branch destination after updating the pointer and branching to the interrupt address, is a value unique to the microprocessor that is determined by hardware for each interrupt factor.

In the case of a microprocessor in which interrupt addresses are concentrated in a narrow space, an instruction to branch to an interrupt processing program is executed at the interrupt address, and the interrupt processing program is generally expanded over a wide space. A memory map of a typical microprocessor is shown in FIG. Furthermore, in the case of a microprocessor in which interrupt addresses are distributed, it may be possible to develop an interrupt processing program from the interrupt address.

A typical microprocessor memory map is shown in FIG.

To return from interrupt processing, use the interrupt return instruction.
The stack pointer is updated, the stack returns to the return address, etc., and a branch is made to the return address.

On the other hand, for non-interrupt branches, in addition to directly specifying the branch destination, a microcontroller with the function of specifying the value set in a specific register as the branch destination is used to enable multiple branches.・The processor also exists.

[Problem to be solved by the invention]

The above-mentioned conventional microprocessors have the disadvantage that program memory is consumed to execute branch instructions, which increases the time required for interrupt processing.Also, since the space between interrupt addresses is fixed, It is difficult to effectively use the program memory before the interrupt address, and the problem is that it is likely to become invalid space.

[Means to solve the problem]

The microprocessor of the present invention includes an interrupt detection circuit that detects the occurrence of an interrupt factor, and an interrupt control register that controls interrupt processing. the address setting means for setting an interrupt address for each interrupt cause; and a multiplexer for inputting the output of the address setting means to a program counter using the interrupt cause detected by the interrupt detection circuit as a selection signal. configured.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a program counter 1, a stack 2, an instruction ROM 3, an instruction decoder 4, an interrupt detection circuit 5,
It is comprised of an interrupt control register 6, a stack pointer 7, an address setting circuit 8, and a multiplexer 9.

In FIG. 1, program counter 1 is a register indicating the address of instruction ROM 3,
It has functions such as increment operation, rewriting by instructions, saving data to the stack 2, and restoring data from the stack 2. Instruction R
OM3 is a memory that stores micro programs.
It functions to output the contents of the address specified by the program counter 1 to the instruction decoder 4.

The instruction decoder 4 decodes the microprogram input from the instruction ROM 3 and outputs control signals for each unit within the microprocessor. The interrupt detection circuit 5 is a circuit that detects the occurrence of an interrupt factor, and the interrupt control register 6 is a register that holds the state of interrupt prohibition/permission. Stack pointer 7 is an increment/decrementable counter that points to a level in stack 2. The address setting circuit 8 is
DD, l, ADD, 2. −・, ADD, −= ,
It is composed of a read-only memory including ADD, n, and data is written therein together with the instruction ROM 3 using a mask. The multiplexer 9 selects writable data corresponding to the interrupt factor from among the data in the address setting circuit 8, and sets this data in the program counter 1.

As shown in FIG. 1, the interrupt detection circuit 5 detects the occurrence of an interrupt factor at INT, and if the interrupt is enabled in the interrupt control register 6, , the contents of interrupt control register 6 are changed to prohibit multiple interrupts, the value of program counter 1 is saved to stack 2, and stack pointer 7 is updated. In the address setting circuit 8, ADD,k is selected by the multiplexer 9, set in the program counter 1, and interrupt processing is started.0 A typical microprocessor memory map corresponding to this embodiment is shown. It is shown in Figure 3.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram of a second embodiment of the invention. As shown in FIG.
O, stack 11, instruction RAM
12, an instruction decoder 13, an interrupt detection circuit 14, an interrupt control register 15, a stack pointer 16, an address setting circuit 17, and a multiplexer 18.

In FIG. 2, the main operations of this embodiment are the same as those of the first embodiment described above.
The difference from the second embodiment is that an instruction RAM 12 is provided in this embodiment instead of the instruction ROM 3 in the first embodiment. A feature of this embodiment is that the instruction RAM 12 and address setting circuit 17 are configured to be rewritable. With this configuration, even if the interrupt processing address is changed by rewriting the instruction RAM 12, the data in the address setting circuit 17 can be simply rewritten by the program via the data hash 101. It is possible to deal with this by processing the following. Further, in the case of this embodiment, when cyclic processing is executed by interrupt processing, there is an advantage that a counter and a decoder are not required, and processing time is shortened. The memory map of a typical microprocessor of this embodiment is shown in FIGS. 4 and 5.

〔Effect of the invention〕

As described above, the present invention includes an address setting means for setting an interrupt address for each interrupt cause in an area other than the instruction memory in an interrupt control circuit.

By providing a multiplexer that uses the factor detected by the interrupt detection circuit as a selection signal and inputs the output of the address setting means to the program counter, consumption of program memory required for branch instructions can be suppressed, and program memory This has the effect of increasing the efficiency of program memory and shortening interrupt processing time by deleting invalid space.

[Brief explanation of the drawing]

1 and 2 are block diagrams of the first and second embodiments of the present invention, respectively, FIG. 3 is a memory map of the program of the first embodiment, and FIGS. 4 and 5 are block diagrams of the first and second embodiments of the present invention. 2
FIGS. 6 and 7 are memory maps of a conventional microprocessor program. In the figure, 1, 10...program counter, 2, 11-...stack, 3...instruction ROM, 4.13...instruction decoder, 5, 14... Interrupt detection circuit, 6, 15... Interrupt control register, 7.16... Stack pointer, 8,
17...--Address setting circuit, 9, 18...
...Multiplexer.

Claims (1)

[Scope of Claims] In a microprocessor equipped with an interrupt control circuit having an interrupt detection circuit that detects the occurrence of an interrupt factor and an interrupt control register that controls interrupt processing, for an area other than the instruction memory, The present invention is characterized by comprising: address setting means for setting an interrupt address for each interrupt cause; and a multiplexer for inputting the output of the address setting means to a program counter using the interrupt cause detected by the interrupt detection circuit as a selection signal. microprocessor.