JPH04164348A - Trimming data storage circuit - Google Patents

Abstract

PURPOSE:To restrain the increase of circuit scale when the bit number of trimming data is increased, by using constitution wherein, when data in the state of writing exist, clear signal is generated to clear a latching circuit, the output of a nonvolatile storage element and the output of the latching circuit are logically summed, and the results are supplied to a trimming circuit. CONSTITUTION:Each bit of inputted trimming data is taken in a latching circuit 1 of an each bit data storage circuit. When inputted trimming data are suitable, a writing power supply voltage VDD is applied to each nonvolatile storage element 2 and a writing detection circuit, the output data of each latching circuit 1 are written in a corresponding nonvolatile storage element 2, and data of active level (power supply voltage VDD) are written in a detection circuit 20. Thereby a clear signal CLR is outputted from the detection circuit 20, the output of each latching circuit 1 turns to low level, so that the output of each OR gate becomes the output data of the corresponding nonvolatile storage element 2. In this manner, suitable trimming data are stored in each nonvolatile storage element 2, and said stored data are supplied to the trimming circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a trimming data storage circuit, and more particularly to a trimming data storage circuit equipped with a nonvolatile storage element that holds data for trimming an analog circuit or the like.

[Conventional technology]

LS including analog circuits such as amplifiers and reference voltage generation circuits
I may not be able to obtain the desired characteristics due to manufacturing variations, so a non-volatile memory element is provided inside the LSI,
A trimming means is provided for writing data for correcting the characteristics of the analog circuit into this memory element and using this data to bring the characteristics closer to desired characteristics. A trimming data storage circuit stores this trimming data, and a circuit as shown in FIG. 3 has been used to confirm the suitability of the trimming data.

This trimming data storage circuit is constituted by a bit-by-bit data storage circuit IJx provided corresponding to each bit of N-bit trimming data TDJ (J=1 to N, the same applies hereinafter).

Each bit data storage circuit IJx stores a corresponding bit (I
DJ), and when a write power supply voltage Vpp is applied as a write signal, the output data of the latch circuit 1x is memorized and output, and the circuit enters a write state, and the write power supply voltage VPP is never applied. The output of the electrically writable non-volatile memory element 2 is at an inactive level (low level) when it is in a non-writing state, and the output of the latch circuit 1x or the non-volatile memory element 2 is selected by the selection signal SEL. 1 bit of trimming data T D J
The configuration includes a switching circuit 4 that outputs as follows.

Next, the operation of this circuit will be explained.

First, the input trimming data is taken into the latch circuit 1x, and whether or not the taken-in data is valid as trimming data is checked by actually supplying it to the trimming circuit.

At this time, the switching circuit 4 selects the output of the latch circuit 1x.

If this trimming data is valid, apply the write power supply voltage VPP to each nonvolatile memory element 2, write the output data of the corresponding latch circuit 1x to the nonvolatile memory element 2,
The output of the nonvolatile memory element 2 is selected by the switching circuit 4 by inverting the level of the selection signal SEL.

In this way, appropriate trimming data is stored in each nonvolatile storage element 2, and this stored data is supplied to the trimming circuit.

The switching circuit 4 is specifically a circuit as shown in FIG. 4, and in this example, it is composed of three NAND gates 01 to G3 and one inverter Vl.

[Problem to be solved by the invention]

The above-described conventional trimming data storage circuit has a configuration in which a bit-specific data storage circuit IJx is provided corresponding to each bit of the trimming data, and each of these bit-specific data storage circuits IJx is provided with a switching circuit 4. Therefore, this switching circuit 4 connects three NAND gates 0
Since it is composed of 1 to G3 and one inverter ■1,
There is a drawback that as the number of bits of trimming data increases, the circuit scale also increases, making it difficult to miniaturize the LSI.

SUMMARY OF THE INVENTION An object of the present invention is to provide a trimming data storage circuit that suppresses an increase in circuit scale even when the number of bits of trimming data increases and facilitates miniaturization of an LSI.

[Means to solve the problem]

The trimming data storage circuit of the present invention is provided corresponding to each bit of trimming data, latches and outputs the corresponding bit of the inputted trimming data by a latch signal, and sets the output to an inactive level by a clear signal. an electrically writable nonvolatile memory element that stores and outputs the output data of the corresponding latch circuit when a write signal is applied, becomes in a write state, and has an output at an inactive level in a non-write state; and a bit-by-bit data storage circuit comprising an OR circuit that performs a logical sum of the output of the corresponding latch circuit and the corresponding output of the non-volatile storage element, and a non-volatile storage element of the one bit-based data storage circuit. and a write detection circuit that detects whether or not there is a write state and outputs the clear signal when there is a write state.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

Bit-by-bit data storage circuit IJ (J=1 to N, the same applies below)
is provided corresponding to each bit of the trimming data, and latches and outputs the corresponding bit D of the input trimming data by the latch signal CK, and sets the output to an inactive level (low level) by the clear signal CLR. latch circuit 1 and write power supply voltage Vpp of the write signal.
an electrically writable non-volatile memory element 2 which stores and outputs the output data of the corresponding latch circuit 1 when is applied and enters a write state, and whose output is at an inactive level (low level) in a non-write state; The configuration includes an OR gate 3 that performs the logical sum of the output of the corresponding latch circuit 1 and the output of the corresponding non-volatile memory element 2 and outputs 1-bit TDJ of trimming data.

The write detection circuit 20 detects the write power supply voltage V of the write signal.
When pp is applied, it stores active level data (high level of power supply voltage VDD) and outputs a clear signal CLR to enter the write state, and in the non-write state it is an output or inactive level. Non-volatile memory element 2 of the bit-based data memory circuit IJ
It detects whether or not there is a write state in the write state, and outputs a clear signal CLR when there is a write state in the write state.

Next, the operation of this embodiment will be explained.

First, each bit IDJ of the input trimming data is taken into the latch circuit 1 of each bit-specific data storage circuit IJ. At this time, each nonvolatile memory element 2 is in a non-writing state, so their outputs are at a low level.
Therefore, the output (TD, +) of each OR gate 3 becomes the output data (I D , +''') of the corresponding latch circuit 1.

These output data are supplied to the trimming circuit and checked to see if they are valid as trimming data.

As a result, if the input trimming data is valid, the write power supply voltage VPP is applied to each nonvolatile memory element 2 and the write detection circuit, and the output data of each latch circuit 1 is written to the corresponding nonvolatile memory element 2. At the same time, data at an active level (power supply voltage VDD) is written to the write detection circuit 2o, thereby causing the write detection circuit 20 to output a clear signal C.
LR is output.

When the clear signal CLR is output, the output of each latch circuit 1 becomes low level, and therefore the output of each OR gate (TDJ
) is the output data of the corresponding nonvolatile memory element 2.

In this way, appropriate trimming data is stored in each nonvolatile storage element 2, and this stored data is supplied to the trimming circuit.

In this embodiment, the portion corresponding to the conventional switching circuit 4 is one OR gate 3, and therefore the area of this portion is approximately 1/4. In addition, since the write detection circuit 2o, which was not found in the conventional example, has one nonvolatile memory element,
The area including these is significantly smaller in the present invention,
The difference increases as the number of bits of trimming data increases. Moreover, the selection signal S required in the conventional example
EL becomes unnecessary.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the write detection circuit 2oA is constituted by an OR gate that ORs the outputs of the nonvolatile memory elements 2 of all the bit-by-bit data storage circuits IJ (1.2 in this embodiment) and generates a clear signal CLR. The basic operation and effects are the same as in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention detects whether or not there is a nonvolatile memory element in a bit-by-bit data storage circuit in a write state, and when there is a nonvolatile memory element in a write state, a clear signal is generated to clear the latch circuit. By taking the logical sum of the output of the non-volatile memory element and the output of the latch circuit and supplying it to the trimming circuit, the output of the non-volatile memory element of each bit-based data storage circuit and the output of the latch circuit are Since only one OR gate is required for switching between output and output, it is possible to suppress an increase in circuit scale even if the number of bits of trimming data increases, and this has the effect of facilitating miniaturization of LSI. This effect increases as the number of bits of trimming data increases.

Another advantage is that the selection signal generation circuit that was conventionally required is no longer necessary.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing first and second embodiments of the present invention, respectively, and FIGS. 3 and 4 are circuit diagrams showing an example of a conventional trimming data storage circuit, respectively, and this example. FIG. 2 is a circuit diagram showing a specific example of a switching circuit. 1.1x...Latch circuit, 2...Nonvolatile memory element, 3...OR gate, 4...Switching circuit, 11~IN
, IJx...Bit-specific data storage circuit, 20゜\20^...Write detection circuit, Gl~G3...NAN
D gate, IVI...inverter.

Claims (1)

[Claims] 1. Provided corresponding to each bit of the trimming data, latches and outputs and clears the corresponding bit of the trimming data inputted by a latch signal, and sets the output to an inactive level by the signal. an electrically writable nonvolatile memory element that stores and outputs the output data of the corresponding latch circuit when a write signal is applied, becomes in a write state, and has an output at an inactive level in a non-write state; and a bit-by-bit data storage circuit including an OR circuit that takes the logical sum of the output of the corresponding latch circuit and the corresponding output of the non-volatile storage element, and writing to the non-volatile storage element of the bit-based data storage circuit. 1. A trimming data storage circuit comprising: a write detection circuit which detects whether or not there is a data in a write state and outputs the clear signal when there is a data in a write state. 2. When a write signal is applied, the write detection circuit stores data at an active level and outputs a clear signal to become a write state. In a non-write state, the output is an inactive level. Electrically writable nonvolatile memory. 2. The trimming data storage circuit according to claim 1, wherein the trimming data storage circuit comprises an element. 3. The trimming data storage circuit according to claim 1, wherein the write detection circuit is constituted by an OR circuit which takes the logical sum of the outputs of the nonvolatile storage elements of all the bit-based data storage circuits and generates a clear signal.