JPH04132976A - Test mode generating circuit - Google Patents

Abstract

PURPOSE:To specify numerous modes without need of addition of an external terminal by supplying data of test mode specification by series data and setting a test mode only when the data contains a specific pattern. CONSTITUTION:An LSI 1 is equipped with an internal input terminal 4, from which input data Din being series data is supplied via an input buffer 5 to a logic circuit 2 and a test mode generating circuit 3. When the series input data Din contains a specific pattern which does not appear during normal operation, a test mode detecting means detects this. In this case since the specific pattern is not detected during normal operation, the terminal 4 for use during normal operation can serve in common. In addition since a test mode is set by utilizing a pattern of parallel data which is an output of an S/P conversion means at the time of detecting the specific pattern, one external terminal 4 to be required is sufficient. Therefore numerous test modes can be specified without need of an external terminal added especially.

Description

[Detailed Description of the Invention] [Field of Application of M Collection] The present invention relates to a test mode generation circuit for setting a test mode when testing an LSI, and particularly relates to a test mode generation circuit for setting a test mode when testing an LSI.
The present invention relates to a test mode generation circuit for setting a test mode.

[Prior Art] In recent years, as the integration density of LSIs has improved, tests performed in the final inspection process have become more and more complex, for example, tests are performed for each functional block or are performed by changing the properties of test patterns in various ways. It has become diverse. An LSI having such a wide variety of test modes requires an external terminal for specifying the test mode from outside the LSI.

[Problems to be Solved by the Invention] However, providing a test mode designation terminal that is not used in normal operating conditions among the limited number of external terminals leads to an increase in cost due to an increase in the size of the LSI package. Undesirable. In particular, as the number of test modes increases, the number of external terminals required to specify the test mode also increases, resulting in a problem that the LSI package becomes larger and larger.

Therefore, the test mode is set by writing data that specifies the type of test mode from the outside into a dedicated test register provided inside the LSI via the data terminal and address terminal for the CPU interface. There are also known ones that did this.

However, with this test mode setting method, the CP
It cannot be applied to LSIs that do not have data terminals, address terminals, etc. for the U interface. Furthermore, even in such an LSI, an external terminal is still required to specify writing to a dedicated test register, and at least one external terminal is still required to specify the test mode. .

The present invention has been made to solve these problems, and an object of the present invention is to provide a test mode generation circuit that does not require any external terminals for testing and is capable of specifying a large number of test modes. With the goal.

[Means for Solving the Problems] A test mode circuit according to the present invention includes a serial-to-parallel conversion means for converting serial data inputted from a specific external input terminal into parallel data, and a specific information that does not appear in the parallel data during normal operation. a test mode detecting means for detecting that a pattern is included; and a test mode setting means for setting a test mode according to the pattern of the parallel data when the specific pattern is detected by the test mode detecting means. It is characterized by being equipped.

[Operations] According to the present invention, if data serially input through a specific external input terminal includes a specific pattern, the test mode detection means detects this. Here, since the specific pattern is a pattern that does not appear during normal operation, the test mode is not detected during normal operation. Therefore, the specific external input terminal used for designating the test mode can be shared with the external input terminal used for normal operation.

Further, according to the present invention, the test mode is set using the pattern of parallel data that is the output of the serial/parallel converter when the specific pattern is detected. Since the pattern is externally given as serial data, one external terminal is sufficient regardless of the number of bits required to specify the test mode.

In this way, in this invention, only one external terminal is required to specify the test mode, and this external terminal can also be used in common with the external terminal used in normal operation. It becomes possible to specify a large number of test modes without adding any external terminals for mode specification.

[Embodiments] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an LSI incorporating a test mode generation circuit according to an embodiment of the present invention.

That is, the LSII incorporates a logic circuit 2, which is a functional section of the original LSII, and a test mode generation circuit 3, which specifies a test mode. The LSII is also provided with an external input terminal 4, from which input data DIN, which is serial data, is supplied to the logic circuit 2 and test mode generation circuit 3 via an input buffer 5. ing.

Test mode generation circuit 3 is configured as follows.

That is, the input data DtN serially input via the external input terminal 4 and the input buffer 5 is input to the first stage delay circuit 11 of the eight one-clock delay circuits 11 to 18 connected in series.

The delay circuits 11 to 18 constitute serial-to-parallel conversion means, and are connected to a master clock φ. The frequency-divided clock φ is divided by 1/2. In synchronization with , input data DIN is sequentially shifted from the delay circuit 11 side to the delay circuit 18 side.

The output of the first-stage delay circuit 11 is input to a first rising differentiator 21. Further, the output D8 of the final stage delay circuit 18 is input to the second rising differentiator 22. These differentiators 21 and 22 are connected to a master clock φ. The rising edge of input data Dxs is detected in synchronization with . Rising detection outputs DIF, DI from the rising differentiators 21 and 22
F2 is input to the AND gate 24, and this AN
The output of the D gate 24 is supplied to a set terminal S as a set signal SET of a static latch circuit 23, which will be described later. These differentiators 21, 22 and the AND gate constitute test mode detection means.

Also, each output D3. of the third to sixth stage delay circuits 13, 14, 15°16. D, ,Del,D, are input to the static latch circuit 23. A set terminal S of the static latch circuit 23 is supplied with a set signal SET which is an output of an AND gate 24. Further, the reset terminal R of the static latch circuit 23 is supplied with an initial clear signal IC.

The 4-pit data output from the static latch circuit 23 is test mode data DAtDB, Do, and D.
It is input to the decoder 25 as D. Decoder 2
5 are input test mode data DA, D8 . Do
, DD and test flag T. - Activate any one of T15. In this case, since the input data to the decoder 25 is 4 bits, the number of test mode flags that can be specified is 16. Also, AND
The set signal SET output from the gate 24 is input to the set terminal S of a set/reset flip-flop (hereinafter abbreviated as 5R-FF) 26.
The output of the R-FF 26 is supplied to the output enable terminal OE of the decoder 25 as an enable signal EN. Further, an initial clear signal IC is supplied to the reset terminal R of the 5R-FF2B. These static latch circuits 23 and decoders 2
5 and 5R-FF26 constitute a test mode setting means.

Next, the operation of the LSII configured in this manner will be explained.

Figure 2 shows the LSI in test mode, Figure 3 shows the LSI in normal operation.
FIG. 3 is a waveform chart showing the operation of I.

In the test mode shown in FIG. 2, input data D
The data input period TT of IN is set to 1/2 the period during normal operation, that is, twice the period of the master clock φ0 and the same period as the period of the divided clock φ6. When specifying the test mode, the input data Dts includes a pattern of successive rising edges in the 7-frequency divided clock as a specific pattern for detecting the test mode. From the timing delayed by 2 clocks with respect to the edge, it is also 6
Four 1-bit data D, C input during the period up to the timing delayed by the divided clock.

B and A are included as data specifying the type of test mode.

When the input data DIN including such a pattern is input, the first rising edge of the input data DIN is delayed by the frequency divided by 8 clock, and the output data D8 from the delay circuit 18 is delayed.
At the time when the output data D1 is output from the delay circuit 11, the output data D1 also rises.

Therefore, the rising detection outputs DIFI and DIF2 from the rising differentiators 21 and 22 rise simultaneously, and the AND gate 2
The set signal SET from 4 becomes active.

Also, at this point, the delay circuits 13, 14, 15, 16
As output data, data A and B shown as D in FIG.
, C, and D are output, which are latched by the static latch circuit 23 and supplied to the decoder 25 as its input data DAIDBtDcsDo. Also, at this time, 5R-FF2B outputs the set signal SE
Since the decoder 25 is in the state set by T, the decoder 25 is in the output enable state, and the test flag T0
~T't5, one flag determined by data DA*DB+DctDD becomes active.

As a result, a test is executed according to the activated test flag.

On the other hand, in the normal mode shown in FIG. 3, the data input period TN of the input data DIN is 2
double the period, that is, the master clock φ. 4 times the period of the divided clock φ. is set to twice the period of . Such a data input period T.

If set to will always be shifted by one frequency-divided clock, and both image powers will never change at the same time. In other words, during normal operation, the specific pattern of successive rising edges in the divided-by-7 clock is not included in the input data DIN, and the output DIF of the rising differentiators 21 and 22 is not included in the input data DIN.
l and DIF do not rise at the same time.

Therefore, during normal operation, the SET signal is not output from the AND gate 24, and the test flag T is not output.

-T15 is never activated. As a result,
Test mode generation circuit 3 does not affect the operation of logic circuit 2 at all.

In this way, the test mode generation circuit 3 according to this embodiment
According to , the external input terminal 4 for specifying the test mode can be shared with the input terminal for normal operation,
Moreover, when specifying the test mode, the test mode is specified based on the serially input signal, so in the above example, 16 test modes can be specified from one external input terminal.

Note that this invention is not limited to the embodiments described above. In the above embodiment, the test mode detection means and the test mode setting means are provided separately, but they may be implemented together using a ROM table or the like, for example. In this case, the contents of the ROM table are determined so that a predetermined test flag is output only when the 9-bit input data to the ROM table includes a specific pattern "oi-1---ot". Just leave it there.

[Effects of the Invention] As described above, according to the present invention, the data specifying the test mode is supplied as serial data.
Only one external input terminal is required, and the test mode is set only when the serial data contains a specific pattern that does not occur during normal operation. It is possible to use commonly used external terminals. Therefore, according to the present invention, it is possible to designate a large number of test modes without specifically adding any external terminals for designating test modes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an LSI having a test mode generating circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the test mode generating circuit in the test mode, and FIG. 3 is a block diagram of the same test mode generating circuit. FIG. 3 is a waveform diagram showing the operation during normal operation. 1: LSI, 2: Logic circuit, 3: Test mode generation circuit, 4: External input terminal, 5: Input buffer, 11 to 18;
1 clock delay circuit, 21, 22; rising differentiator, 2
3; Static latch circuit, 24; AND gate,
25; Decoder, 26; 5R-FF -4'/

Claims (1)

[Claims] (1) Serial-to-parallel conversion means for converting serial data input from a specific external input terminal into parallel data; and test mode detection means for detecting that the parallel data includes a specific pattern that does not appear during normal operation. and test mode setting means for setting a test mode according to the pattern of the parallel data when the specific pattern is detected by the test mode detection means.