JPH04134976A - Television receiver - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by realizing a ghost cancel function and a down convert function with a common hardware. CONSTITUTION:In a program memory 86, a program for realizing at least the ghost cancel function and the down convert function is stored. In this case, a switching means applies the program stored in the program memory to a digital signal processor 84 selectively based on a switching signal. And the digital signal processor executes a process based on the program applied by the switching means. For example, providing DSP groups D1-D16 arranged at an array form, the program for a GC process or the program for a down convert process is applied to these DSP groups D1-D16 selectively by a manual switch circuit 87. Thus, the ghost cancel function and the down convert function are realized, and since the independent hardware is not constituted to realize the both functions, the circuit scale can be reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a television receiver, and particularly to a television receiver suitable for having a ghost canceling function and a MUSE signal down-converting function. Regarding.

(Prior Art) FIG. 11 is a block diagram showing a conventional digital television receiver equipped with a ghost cancellation function. The part surrounded by the broken line is the ghost cancellation processing section 1
3 is shown.

The television radio frequency (RF) signal induced in the antenna 1 is given to the tuning section 2.0 The tuning section 2 is given a tuning signal from the CPU 3 via the interface 4.
The channel selection section 2 selects a channel based on the channel selection signal, converts it into an intermediate frequency (IP) signal, and supplies the signal to the IF section 5 . The IF section 5 detects the IF multiplied signal and outputs a baseband video signal.

The audio intermediate frequency signal included in the video signal from the IP unit 5 is applied to an audio intermediate frequency amplification/detection circuit 6 where it is detected, and then converted into a digital signal by an A/D converter 7. This digital audio signal is subjected to various processes such as audio multiplexing, volume, tone quality, and balance in the audio signal processing circuit 8, and then converted to an analog signal in the D/A converter 9. This analog signal is the drive circuit 1
0 to the speaker 11 for audio output.

On the other hand, the baseband video signal from the IF section 5 is sent to the A/D
The signal is converted into a digital signal by the converter 12 and then provided to the ghost cancellation processing section 13 . The ghost cancellation processing unit 13 transmits the ghost-removed video signal to the luminance signal processing circuit 14 by a ghost removal operation to be described later.
, is output to the color signal processing circuit 15 and the synchronization separation circuit 16.

The luminance signal processing circuit 14 performs contrast adjustment, image quality adjustment, etc. of the input video signal, and outputs a luminance signal to the matrix circuit 17. The 0-color signal processing circuit 15 performs color demodulation of the video signal, and also performs color contrast adjustment and image quality adjustment. A color signal is output to the matrix circuit 17 after processing such as hue adjustment. The matrix circuit 17 outputs R and G from the input luminance signal and color signal.

A digital signal of B is created and output to the D/A converter 18. The D/A converter 18 has analog R,,G.

Convert it to a B signal and send it to the CRT 20 via the drive circuit 19.
give to

On the other hand, the synchronization separation circuit 16 performs processing such as horizontal synchronization playback and vertical synchronization playback. The deflection processing circuit 21 generates a horizontal deflection signal, a vertical deflection signal, left and right rask distortion correction signals, etc. based on the output of the synchronization separation circuit 16.

Each deflection signal from the deflection processing circuit 21 is applied to the CRT 20, and the R, G, and B signals from the drive circuit 19 are displayed on the screen.

The CPU 3 is connected to a program ROM 22 and an arithmetic RAM 23 via a data bus. The CPU 3 is connected to each block via an interface 4 and controls each block. For example, the CPU 3 controls reception channels for the channel selection section 2, volume control for the audio signal processing circuit 8, and brightness for the luminance signal processing circuit 14. Control and color tone control for the color signal processing circuit 15 are performed. These controls are normally performed based on user operations using an input device (not shown) such as a remote control.

Next, the operation of the ghost cancellation processing section 13 will be explained with reference to FIGS. 12 and 15.

A digital video signal from the A/D converter 12 is applied to a transversal filter (hereinafter referred to as TF) 24 and an input waveform memory 25. As shown in FIG. 12, the TF 24 includes multipliers Mo to M, delay circuits Do to Do with a delay time of T seconds, and adders A1 to A. A video signal from the A/D converter 12 is applied to each of the multipliers Mo to M via an input terminal 31.

Tap coefficients Co to Cs are applied to each multiplier M0 to M from the CPU 3 via an interface 26, respectively.

Multipliers Mo to M each apply a tap coefficient C to the input video signal.
The outputs of the 0 multipliers Mt to M, which multiply and output the multipliers o to C0, are given to the adders A1 to A1, respectively. Multiplier N
The output of o is delayed by a delay circuit Do and sent to an adder A1.
given to. Further, the outputs of the adders A+ to Aゎ are delayed by delay circuits D1 to D5, respectively, and are applied to the next-stage adders A2 to A7 and the output terminal 32, and the multiplication results from the multipliers Mo to M are The delayed signals are added and output from the output terminal 32. In this way, a video signal whose waveform has been equalized based on the tap coefficients is output to the output terminal 32.

The tap coefficients Co to c1 are modified at predetermined intervals based on the flowchart of FIG.

That is, first, waveform capture is performed in step S1. An OCR signal is inserted into the input video signal as a reference signal for ghost removal.

The OCR signal is inserted into the 18th H and 281H within the vertical blanking interval, and is composed of a 5inx/x bar waveform and a pedestal waveform.

The 5inx/x bar waveform and the pedestal waveform are inserted in an 8-field sequence, as shown in the waveform diagram in Fig.
/x bar waveform (Ss, S).

S6. Ss) is inserted, and the pedestal waveforms (Sz, S4, Ss) are inserted in the 2.4 and 5.7 fields.

S)) has been inserted. The input waveform memory 25 uses the arithmetic unit 27 to calculate an 8-field sequence shown in equation (1) below and captures a 5inx/x bar waveform. Similarly, the 5inx/x bar waveform included in the output signal of the TF 24 is captured by the output waveform memory 28.

5OCR=1/4 ((SI 85) + (S6
S2 ) + (Sv -37) + (Ss -34
) )...(1> In the next step S2, a difference calculation is performed. The arithmetic unit 27 calculates the difference between the outputs of the input and output waveform memories 25 and 28, respectively, and generates the input difference signal shown in FIG. 15(a). and an output difference signal are obtained. In the next step S3, peak detection is performed. The peak position of the input difference signal is determined to obtain a time reference. In the next step S4, error calculation is performed based on this time reference.

The reference signal shown in FIG. 15(b) is stored in the reference waveform ROM 29, and the arithmetic unit 27 calculates the peak position of the output difference signal based on the time reference, matches the timing of the peak position, and outputs the reference signal. Perform subtraction with the difference signal.

In the next step S5, the tap coefficients are corrected from the error signal obtained in step S4 and the input difference signal. That is, the calculator 27 performs the correlation calculation shown in equation (2) below.

CI new ”” C1, old (ZΣx
,, ++ −(2)ek Here, CI indicates the i-th tap coefficient, and the subscript ne
w and old indicate after and before modification, respectively. Further, Xm is an input difference signal, ek is an error signal, and α is a positive minute amount.

In the next step S6, the modified tap coefficients are sent to each multiplier Mo of the TF24 via the interface 26.
to M1. The TF 24 performs waveform equalization on the input video signal based on the new tap coefficients and outputs the video signal.

Thereafter, steps S1 to S6 are repeated. Through these steps S1 to S6, a tap coefficient, that is, a tap coefficient such that the error signal converges to O, is generated based on the magnitude of the error signal, and the input video signal is waveform-equalized. In this way, an output video signal from which ghosts have been removed is obtained from the TF 24.

Figure 16 shows the MU that converts the MUSE signal to an NTSC signal.
1 is a block diagram showing a conventional television receiver having an SE/NTSC converter (hereinafter referred to as a down converter).

The MUSE signal transmitted from the satellite is tuned by a BS tuner (not shown) and subjected to FM detection. The detection output is input via the terminal 35 and is passed through a low-pass filter (hereinafter referred to as
After passing through a LPF (referred to as LPF) 36, it is applied to a clamp circuit 37 where the DC component is regenerated. Furthermore, this MUSE
The signal is converted into a digital signal by an A/D converter 38 and provided to a video signal processing section 39.

The video signal processing section 39 includes a scanning line number conversion circuit 40. It is composed of a D/A converter 41 and an LPF 42.

The scanning line number conversion circuit 40 converts the scanning line 112 of the MUSE signal.
Out of the 5, extract the 1050 in the center and add this 1
050 scanning lines are converted into 525 scanning lines.

FIG. 17 is a block diagram showing a specific configuration of this scanning line number conversion circuit 40.

The MUSE signal is subjected to non-linear emphasis on the transmitting side in order to improve the S/N ratio.

On the receiving side, components having a predetermined amplitude or higher among the high-frequency components of the input MUSE signal are subjected to non-linear processing to further increase the amplitude, and then provided to the non-linear de-emphasis circuit 61 via the input terminal 60.

The non-linear de-emphasis circuit 61 is composed of a 7-tap digital filter, and the input MU
De-emphasis is applied to the SE signal and the time axis conversion circuit 62
Output to.

The time axis conversion circuit 62 reads the input MUSE signal according to the signal from the write address counter 63, converts the time axis of the read data according to the signal from the read address counter 64, and outputs the converted data. The write address counter 63 operates with a clock with a sampling frequency of 16.2 MHz from the terminal 65, and the time axis conversion circuit 62 operates with a clock having a sampling frequency of 16.2 MHz from the terminal 65.
480 samples are sampled per line of the USE signal, and about 50 lines out of 525 scanning lines are written.

Further, the read address counter 64 receives 5 bits from the terminal 66.
．． The time axis conversion circuit 62 operates with a clock having a sampling frequency of 0.4 MHz, and converts the time axis of 320 samples per line corresponding to an aspect ratio of 4.3 out of the read MUSE signal and outputs the converted signal. In this way, the time axis conversion circuit 62 outputs signals of 525 scanning lines.

In this time axis conversion, the luminance signal Y and the color signal C are processed separately. FIG. 18 is an explanatory diagram for explaining this processing operation, and FIGS. 18(a) and 18(b) show the input and output of the time axis conversion circuit 62, respectively.

As shown in FIGS. 18(a) and 18(b), for the luminance signal Y, 256 samples out of 347 samples in one line of the MUSE signal are output.

Regarding the color signal C, 64 samples out of 94 samples in one line of the MUSE signal are output. At the time of output, the time axis is converted and the MUSE signal is converted to the scanning line 525.
Stretched by the book signal.

The signal whose time axis has been converted in this way is filtered by a vertical filter 67.
69. Vertical filters 67 to 69 are used for luminance signal Y, color difference signal RY, and color difference signal B-Y, respectively.
It is a two-dimensional digital filter for interpolating input signals. That is, the vertical filter 67 for the luminance signal Y is composed of three taps in the vertical direction, and has one vertical band.
/2 to thin out the scanning lines of the MUSE signal one by one. In this case, the tap coefficients are changed between the first field and the second field of NTSC. On the other hand, the vertical filters 68 and 69 for R-Y and B-Y are configured with two taps and three taps in the vertical direction, respectively. Since the color signal of the MUSE signal is time-compressed to 1/4, the R-
The vertical filters 68 and 69 for Y and B-Y first perform time expansion, return to the original time, and then perform interpolation processing.

Note that the PLL circuit 70 detects the frame pulse and horizontal synchronization signal of the MUSE signal inputted through the terminal 60, and generates a 16.2MH2 signal locked to the phase of the MUSE signal.
The clock is supplied to a control signal generator 71 that provides a control signal to the time axis conversion circuit 62 and a PLL circuit 72. Further, the PLL circuit 72 is given a clock of 16.2 MHz corresponding to 1125 scanning lines, and has a frequency of 10.08 MHz which is an integer ratio of 45:28 to this clock frequency.
Generates H2 tarokku. This clock is supplied to a control signal generator 73 which provides control signals to the vertical filters 67 to 69.
is supplied to.

In this way, the scanning line number conversion circuit 40 has a scanning line number of 1125.
This converts the book signal into a signal with 525 scanning lines and outputs it. The luminance signal Y and color difference signals R-Y and B-Y from the scanning line number conversion circuit 40 are converted into digital signals by the D/A converter 41, and then the high-frequency components are cut by the LPF 42 and sent to the respective output terminals 43. 45.

On the other hand, the audio signal processing section 46 includes an audio signal processing circuit 47, digital filters 48a, 48b, D/A converters 49a, 49b, LPF 50a,
50b. Audio signal processing circuit 47
After deinterleaving the input digital signal number ↓, performs NI-DPCM demodulation to reproduce the A-mode and B-mode audio data. The reproduced A-mode and B-mode audio data are applied to filters 48a and 48b corresponding to these modes, respectively, to remove unnecessary high-frequency components. Digital filters 48a, 48
The outputs of signal b are converted into analog signals by D/A converters 49a and 49b, respectively, and then outputted from output terminals 51 and 52 via LPFs 50a and 50b.

By the way, conventionally, when configuring a television receiver having the above-mentioned ghost cancellation function and down-conversion function, the hardware shown in FIGS. This results in a configuration of

(Problems to be Solved by the Invention) As described above, in the conventional television receiver described above, when configuring a television receiver having a ghost canceling function and a down-converting function,
Since the hardware for realizing each function is complicated, there is a problem in that the configuration becomes extremely large-scale.

The present invention has been made in view of such problems, and includes:
By making the ghost cancellation function and down-conversion function possible with common hardware,
An object of the present invention is to provide a television receiver whose circuit scale can be reduced.

[Structure of the Invention] (Means for Solving the Problems) A television receiver according to the present invention includes a digital signal processor that is given a predetermined program and realizes a predetermined function based on the program, and at least a ghost canceling function and a digital signal processor. A program memory that stores a program for realizing a down-conversion function in the digital signal processor, and a switching means that selectively reads a predetermined program from the program memory and applies it to the digital signal processor based on a switching signal. It is a servant.

(Function) In the present invention, a program for realizing at least a ghost cancel function and a down conversion function is stored in the program memory. The switching means selectively provides the program stored in the program memory to the digital signal processor based on the switching signal. The digital signal processor performs processing based on a program given by the switching means.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention. In FIG. 1, the same components as in FIG. 11 are given the same reference numerals.

The RF multiplied signal induced in the antenna 1 is given to the tuning section 2. The channel selection section 2 is given a channel selection signal from the CPU 81 via the interface 4, and the channel selection section 2 selects a channel based on the channel selection signal, converts it into an intermediate frequency (IF) signal, and sends it to the IF section 5. give. The IF section 5 detects the IF signal and outputs a baseband video signal.

The audio intermediate frequency amplification/detection circuit 6 performs audio detection on the audio intermediate frequency signal included in the video signal from the IF section 5 and outputs it to the A/D converter 7 . The A/D converter 7 converts the audio detection output into a digital signal and outputs it to the audio signal processing circuit 8.

The audio signal processing circuit 8 performs audio multiplexing, volume, tone quality, balance, and other processing, and outputs the audio signal to the D/A converter 9. The D/A converter 9 converts the audio signal from the audio signal processing circuit 8 into an analog signal and outputs the analog signal to an output terminal 82.

On the other hand, the video signal from the IP section 5 is sent to the A/'D converter 1.
2 is also given. The A/D converter 12 converts the analog video signal into a digital signal and outputs it to the selector 83 and the input waveform memory 25. The selector 83 is also provided with a MUSE signal from the A/D converter 38. That is, a MUSE signal is inputted to the input terminal 35 from a BS tuner (not shown), and high-frequency components are removed through the LPF 36, clamp circuit 37, and A/D converter 38, which have the same configuration as the conventional one. A digital MUSE signal with a regenerated DC component is applied to the selector 83. The selector 83 is a DS to be described later.
It is controlled by a P control circuit 84 to apply one of the two human powers to the DSP group D1 of the DSP array group 85. The DSP array group 85 is composed of 16 DSP groups D1 to D16 arranged in a 4×4 array.

2 to 5 and 6 show the DSP array group 85, respectively.
FIG. 2 is a block diagram and an explanatory diagram for explaining each DSP group. These block diagrams and explanatory diagrams are from the document rA GE
NERAL PURPO3E PROGRAHHABL
EVIDEO5IGNAL PROCESSORJ
(IEEE Transactions Con
5ui+er Electronics Vol, 35
No. 3 AUGUST 1989”).

FIG. 2 shows a DSP chip 100 for video. D
The SP chip 100 is a DSP chip that has five data ports to enable interconnection between multiple DSPs.
101. Clock generator 102
creates an internal clock based on an external clock. The initial controller 103 is given initial data and a reset signal, and when given a chip address indicating this DSP chip 100, performs predetermined initial settings.

FIG. 6 is an explanatory diagram for explaining the architecture of the DSP.

The DSP has three systems of ALE (Arithm
etic and Logic Element) and
2 systems that make up the memory + 7) M E (Melory
Element) and 5 systems of OB (Output I/
buffer). 3 systems ALE, 2 systems M
E and 5-line OB are programs P1 to P10, respectively.
controlled by.

FIG. 3 shows the configuration of ALE.

The ALE has boats 105 to 107 that take in data, and data A, B, and C input via each boat 105 to 107 are sent to the ALU (logical logic unit) via shifters 108 to 110 and multiplexers 111 to 113, respectively. (arithmetic unit) 114.

FIG. 4 shows the configuration of the ME.

The address data is given to an adder 116 via a port 115, added to a predetermined value, and further added to a multiplexer 117.
to RAM 118 via.

On the other hand, data is input via port 119 and provided to RAM 18 via multiplexer 120.

RAM 18 is a 512x12 static memory.

FIG. 5 shows a DSP chip 121 composed of three DSPs 122 to 124. Each DSP
122 to 124 are mutually connected using a data boat, and each DSP 122 to 12
4 each have one system of data ports for data transfer with the outside.

In FIG. 1, each DSP group D1 of the DSP array group 85
As described above, each of D16 to D16 has an internal memory (not shown) and has a processing function based on data from the DSP control circuit 84. This DSP control circuit 84 is provided with a program for ghost cancellation processing or a program for down conversion processing from a program memory 86. This program switching is performed based on a switching signal from the manual switch circuit 87.

FIG. 7 shows a DSP control circuit 84 and a program memory 86.
FIG. 2 is a block diagram showing a specific configuration.

The DSP control circuit 84 includes a ghost cancellation (GC) program counter 131, a down-conversion program counter 132, an inverter 133, and a switch 13.
It is composed of 4. In addition, program memory 8
6 has a GC program area 138 that stores a program for ghost cancellation processing, and a down-conversion program area 139 that stores a program for down-conversion processing. These areas 138
, 139 each consist of, for example, 32 words, assuming that the capacity of the program memory 86 is 64 words. The start address of the GC program area 138 is ooooooo
”, and the down conversion program area 139
The starting address is "1oooooo".

The GC program counter 131 and the down-conversion program counter 132 are reset by a reset signal from the terminal 136, count the clock from the terminal 137, and send the count output to the program memory 86.
are applied to terminals a and b of the switch 134 as addresses, respectively. The GC program counter 131 is reset by a reset signal, and the count output is a binary value.
It becomes ooooooo°°.

Further, the down-conversion program counter 132 is reset by the reset signal, and the count output becomes the binary value "100000".

A switching signal is input to the terminal 138 from the manual switch circuit 87. This switching signal is applied to the control end of the down-conversion program counter 132 and the switch 134, and is also applied to the control end of the GC program counter 131 via the inverter 133. When the switching signal is at a low level (hereinafter referred to as "L"), the switch 134 selects terminal a, and the count output of the GC program counter 131 whose control terminal becomes "H" is stored in the program memory 86 as an address. given as. Further, when the switching signal is at a high level (hereinafter referred to as "H"), the switch 134 selects the terminal, and the control terminal is "H".
” down-conversion program counter 13
A count output of 2 is provided to program memory 86 as an address. Program memory 86 is switch 13
4, and the program data stored at this address is supplied to each DSPDI to D16 of the DSP array group 85 via the DSP control circuit 84.

When the GC processing program from the GC program area 138 is given to the DSPD1 to D16, the DSP
ffDl selects the signal input via the selector 83 for each D
The DSP group D5 takes in the input waveform and outputs the DS
P group D6 takes in the output waveform, and DSP group D10 and DS
The P group D9 performs differential calculation processing, the DSP group D13 performs peak detection, the DSP group D14 performs error calculation based on peak information, and the DSP group D12 performs correlation calculation to obtain new tap coefficients. The DSP groups D2, D3, D7 and D8 constitute a transversal filter. In this case, the video signal from which the ghost has been removed is output from the DSP group D16 to the output terminal 98 via the D/A converter 93.

On the other hand, when the down-conversion processing program from the down-conversion program area 139 is given to the DSPDl to D16, the DSP group D2 and the DSP group D
3 have the same functions as the PLL 70 (1125 system) and control signal generator 71 in FIG. , DSP group D10
has the same function as counters 63 and 64, and D S P
WD 1 functions as a non-linear de-emphasis circuit 61, DSP groups D5, D6, D9 constitute a time axis converter 62, DSP groups D8, D12 . D16 exhibits the functions of vertical filters 67 to 69, respectively. DS
The outputs from P groups D8, D12° and D16 are respectively D/
The signals are output from output terminals 95 to 97 via A converters 90 to 92.

Furthermore, in this case, the DSP group 13 performs deinterleave processing and N I-DPCM demodulation of the audio signal, and
The P group 14.15 constitutes the LPF, and the DSP group D15 constitutes the D
An audio signal is output from an output terminal 99 via a /A converter 94.

Note that the timing circuit 88 receives M from the A/D converter 38.
Based on the USE signal, the frequency is 16.2MHz, 5
．． 04MHz clock is generated and the DSP array group 85
It is designed to be given to In addition, the output waveform memory 28
, the configurations of the calculation RAM 23 and the reference waveform ROM 29 are the same as before, and the CPU 81 has the program ROM 89.
Each part is controlled based on a program stored in the . Further, the DSP control circuit 84 causes the selector 83 to select the output of the A/D converter 12 and the interface 4 when the switching signal is "L", and causes the selector 83 to select the output of the A/D converter 38 when the switching signal is "H". It is designed to let you choose.

Next, the operation of the embodiment configured as described above will be explained in the eighth section.
This will be explained with reference to the flowchart shown in FIG.

Now, assume that a ghost cancellation (GC) processing function is realized. In this case, the operation is based on the flowchart in FIG. That is, step S1 in FIG.
1, the manual switch circuit 87 applies an "L" switching signal to the DSP control circuit 84. Then, D
The switch 134 in the SP control circuit 84 selects the terminal a, and the count output of the GC program counter 131 is given to the program memory 86 as an address. G.C.
The initial count value of the program counter 131 for
ooo", and from the GC program area 138
A program code (opcode) for C processing is read out and given to each DSPD1 to D16 of the DSP array group 85 (step 512).

The processing for the audio intermediate frequency signal from the IF section 5 is the same as in the conventional case, and an audio output is obtained at the output terminal 82.

On the other hand, the video signal from the IF section 5 is also provided to the selector 83 and the input waveform memory 25 via the A/D converter 12. In step S13, the DSP control circuit 84 causes the selector 83 to select the outputs of the A/D converter 12 and the interface 4. As a result, the A/D converter 12
The video signal from the input/output waveform memory 25.28 is applied to the DSP array group 85, and the input/output waveform from the input/output waveform memory 25.28 is applied to the 052714 group 85 via the interface 4.

In the next step S14, the DSP group D1 provides these signals to each DSP group. In the next step S15, the DSP
Group D5 utilizes an internal memory (not shown) to capture the input waveform and detect OCR signal components, and in step S16,
SP group D6 utilizes internal memory to capture the output waveform and detect OCR signal components.

Then, in step S17.818, each DSP
A difference calculation is performed using mD9 and Dlo to obtain an input difference signal and an output difference signal. Next step S19
Then, DSPI\DI3 performs peak detection based on the difference data of the input waveform. Based on this peak information, in the next step S20, DSP$¥D14
calculates the error between the difference data of the output waveform and the reference waveform data.

In the next step S21, a correlation calculation is performed by the DSP group D12. The DSPI\D12 stores tap coefficients in its internal memory, and after multiplying the error calculation result by a predetermined constant, performs subtraction with the coefficient data in the internal memory to obtain new tap coefficient data. Next, in step S22, the new tap coefficient data is sent to the DSP groups D2, D3, D, which constitute the transversal filter.
7, is transferred to the DS, and in the next step S23, the DSP
! A video signal whose waveform has been equalized is output from the \ID16. This video signal is converted into an analog signal by a D/A converter 93 and output from an output terminal 98.

Thereafter, steps S15 to S23 are repeated, and the video signal from which the ghost has been removed is output from the output terminal 98.

On the other hand, when down-conversion processing is to be realized, in step S30 of FIG. 9, the manual switch circuit 87
A switching signal of "H" is output from.

A switch 134 in the DSP control circuit 84 selects the terminal, and the count output from the down-conversion program counter 132 is given to the program memory 86 as an address. The initial value of the down-conversion program counter 132 is “100000”, and the down-conversion program area 13 of the program memory 86
The down-conversion processing program from 9 is read out and given to the 052714 group 85 (step 531
).

The MUSE signal input via the input terminal 35 is L
P F 36 removes unnecessary high-frequency components of 8.1 MHz or higher, and clamp circuit 37 regenerates the DC component, which is then converted into a digital signal by A/D converter 38 and provided to selector 83 .

In the next step S32, the DSP groups D2 and D3 are set to the 17th DSP groups by the down-conversion processing program.
PLL 70 (1125 system) and control signal generator 71 in the figure
functions as In addition, DSP groups D6 and D7 each have PL
It functions as L72 (525 system) and control signal generator 73. These DSPD2.53D6, D7 have a frequency of 16.2MH2, 5,04M from the timing circuit 88.
H2's near D-lock is provided for operation.

In the next step S33, a clock is supplied from the timing circuit 88 to the DSP group D10, and the clock is supplied to the DSP group D10.
IO operates as a write address counter 63 and a read address counter 64 for the time axis conversion circuit 62.

Next, the selector 83 is controlled by the DSP control circuit 84 to select the output of the A/D converter 38 (step 534),
The MUSE signal is sent to 052714 group 8 via DSP group D1.
5 is input. In the next step S35, the DSP group D1
Non-linear de-emphasis processing is performed.

In the next step 836, the DSP group D5 D6°D9
performs time axis conversion using internal memory.

These DSP groups D5, D6, D941, PL
DS- constituting L70°72 and counter 63.64
P group D2゜D6. It operates under the control of signals from Dlo. Next, in step S37, the DSP groups D8, D12 . D16 functions as a vertical filter for the luminance signal Y, color difference signal RY, and color difference signal B-Y, respectively. In this way, interpolation processing is performed on the video signal whose time axis has been converted.

Next, in step 338, the luminance signal Y and the color difference signal R-
Y and B-Y are applied to D/A converters 90 to 92, respectively, and converted into digital signals, which are output from output terminals 95 to 97.

On the other hand, regarding the audio signal included in the MUSE signal, D
Pass through SP groups DI, D5, and D9 and enter DSP group DI3.
is given, and deinterleave processing and N[-DPCMfi adjustment operation are performed in step S39. In this way, the A mode and B mode audio data are reproduced by the DSP group DI3, and these audio data are L P F
DSP group D14.50a and 50b (see FIG. 16) respectively. D15 to remove unnecessary high frequency components. Next, in step S40, D
The signal is supplied from the SP group D15 to the D/A converter 94, converted into an analog signal, and outputted from the output terminal 99. In this way, the down-conversion function is realized.

As described above, in this embodiment, the DSP groups D1 to D16 arranged in an array are provided, and the GC processing program or the down-conversion processing program is selectively switched between these DSP groups D1 by a manual switch circuit. By applying the signals to D16 to D16, a ghost cancel function and a down contour function are realized. Since independent hardware is not configured to realize both functions, the circuit scale can be significantly reduced.

Note that multiple programs can be executed by storing multiple programs in the program memory, specifying these addresses using multiple program counters, and selectively applying the count output of each program counter to the program memory using a switching signal. It is also possible to have a single DSP array perform it.

FIG. 10 is a diagram showing another embodiment of the present invention.

In this embodiment, instead of the DSP control circuit 84, the DS shown in FIG.
This embodiment differs from the embodiment shown in FIG. 1 in that a P control circuit 140 is employed. The GC program ROM 141 stores a program for GC processing, and the down conversion program ROM 142 stores a program for down converter processing. The loader 143 provides read addresses to these program ROMs 141 and 142 to read the stored data. The loader 143 is controlled by a switching signal from a manual switch circuit 87 (see FIG. 1) inputted through a terminal 138, and selectively accesses one of the program ROMs 141 and 142 to read out program data. is written into the program RAM 144.

The processor 145 constantly supplies a program read address to the program RAM 144, and executes various processes based on the program data stored in the program RAM 144.

In the embodiment configured in this manner, GC processing and down-conversion processing are selected by switching the switching signal of the manual switch circuit 87. When the manual switch circuit 87 generates an "L" switching signal, the loader 143 supplies a read signal to the GC program ROM 141 to read program data for GC processing. Furthermore, the loader 143 has a program RAM
A write address is supplied to 144 to write program data for GC processing. This program data is Bromo
The processor 75 executes a program for GC processing.

Conversely, when an "H" switching signal is applied to the terminal 138,
The loader 143 is a down conversion program RO
A program for down-conversion processing is read from RAM 142 and written to program RAM 144. Thereby, the processor 145 executes a program for down-conversion processing.

Other operations are similar to the embodiment shown in FIG. In this way, a single DSP performs ghost cancellation processing and down-conversion processing.

It is clear that this embodiment also has the same effects as the embodiment shown in FIG.

[Effects of the Invention] As explained above, according to the present invention, when the ghost cancellation function and the down conversion function are realized,
This has the effect that the circuit scale can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention, and FIGS. 2 to 5 are DSPs shown in FIG.
A block diagram for explaining the group, Figure 6 is D in Figure 1.
An explanatory diagram for explaining the SP group, Figure 7 is D in Figure 1.
A block diagram showing the specific configuration of the SP control circuit and program memory, FIGS. 8 and 9 are flowcharts for explaining the operation of the embodiment, and FIG. 10 is a block diagram showing another embodiment of the present invention. , FIG. 11 is a block diagram showing a conventional television receiver, FIG. 12 is a block diagram showing the configuration of a TF, FIG. 13 is a flowchart for explaining a tap coefficient correction method, and FIG. 14 is an OCR signal Figure 15 is a waveform diagram to explain the operation of TF, Figure 16 is a block diagram showing a conventional television receiver, Figure 17 is the number of scanning lines in Figure 16. FIG. 18, a block diagram showing a specific configuration of the conversion circuit, is an explanatory diagram for explaining the operation of time axis conversion. 83...Selector, 85...DSP array group, 84
...DSP control circuit, 86...program memory,
87... Manual switch circuit, to D16... DSP group.

Claims (1)

[Scope of Claims] A digital signal processor that is given a predetermined program and realizes a predetermined function based on the program; and a program that stores a program for realizing at least a ghost cancellation function and a down-conversion function in the digital signal processor. 1. A television receiver comprising: a memory; and switching means for selectively reading out a predetermined program from the program memory and applying it to the digital signal processor based on a switching signal.