JPH04134866A - Field effect transistor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize low resistance of a gate electrode by providing an gate structure which is formed by laminating an insulating film including a silicon nitride film and a metal. CONSTITUTION:An isolation region 1-2 is provided to a surface of a semiconductor substrate 1-1. A gate electrode of a titanium silicide film 1-5 is formed in an element region through a silicon oxide film 1-3 and a silicon nitride film 1-4. Impurities of reverse conductivity of a semiconductor substrate is introduced to the gate and the isolation region selfmatchingly by ion implantation to form a source/drain region 1-6. Although silicide 1-5 is used as a gate, reaction with the silicon oxide film 1-3 is prevented by the silicon nitride film 1-4. Therefore, characteristic of a transistor is not unstabilized. Furthermore, a gate material of high conduction property is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO8 field effect transistor device and a method of manufacturing the same.

(Prior Art) FIG. 2 is a sectional view showing the structure of a MOS-11 field effect transistor according to the prior art. An element isolation region 2-2 is provided on the surface of the semiconductor substrate, and the element region includes:
Poly, 2-4 silico/2-4, and titanium silicide 2-5 are laminated via gate oxide g2-3 to form the gate. Source and drain regions are formed by ion-implanting impurities of the opposite conductivity type to the semiconductor substrate in a self-aligned manner into the gate and element isolation regions. There are three main problems with the conventional technology.

One is the resistance of the gate electrode. Originally policy series, 2-4
, 2-5 The purpose of layering Solicide on Kono is Genotai.

However, in the structure of the conventional technology, the resistance is 1.2-
4 Polysilicon/Polysilicon 2-4 and its resistance is increased by the amount of polysilicon present.

Next is the re-diffusion of impurities in the gate polysilicon. In the prior art, the gate polysilicon 2-4 is doped with about 1020.mu.m of P-type or n-type impurity to control the threshold voltage of the transistor. However, due to the high temperature treatment step after forming the gate silicide 2-5, the impurities escape into the silicide and the impurity concentration in the gate polysilicon 2''''4 decreases. As a result, it becomes impossible to control the threshold voltage of the transistor,
The polysilicon near the gate oxide film becomes depleted during transistor operation, causing a decrease in the transistor's current driving ability.

, 2-4 The third problem is that it is difficult to control the impurity profile of the channel region because the only way to do this is to introduce P-type or n-type impurities into the gate polysilicon core. In other words, for example, if an n-type substrate is used and the gate impurity is n-type, it is difficult to suppress the short channel effect, and if the gate impurity is p-type, the current driving ability of the transistor will be reduced. There's a problem.

In order to solve the above problems, it is desirable that the gate structure has a single layer structure of silicide instead of a multilayer structure of polysilicon and silicide.

In this case, if the gate thickness is the same as in the case of a stacked structure, the resistance will be lower, and if the resistance is the same, the gate electrode can be made thinner, making the subsequent planarization process easier.

Further, impurities are not redistributed during subsequent high-temperature heat treatment, and the work function of silicide is located between that of a p-type semiconductor and an n-type semiconductor, making it easier to control the impurity profile of the channel.

However, if a single-layer silicide gate is used, the silicide and gate oxide film will react and the operation of the transistor itself will become unstable.

(Problem to be Solved by the Invention) In the conventional technology, the resistance of the gate electrode cannot be made sufficiently low. There are problems such as difficulty in determining the impurity profile of the channel, which causes gate impurities to be re-diffused in a subsequent heat treatment process. When trying to solve this problem by using silicide or metal as a gate material, there were problems such as reactions with the gate oxide film, making transistor operation unstable.

[Structure of the Invention (Means for Solving the Problems)] In order to solve the above problems, a silicon nitride film is used as a film to prevent reaction between the gate material and the gate insulating film, either in the gate insulating film or at the interface with the gate material. Alternatively, it is characterized by a structure in which it is located at the interface with the semiconductor substrate and the gate material is metal or silicide.

(Function) When a silicon nitride film is used as the reaction prevention film, the reaction between the gate material and the gate insulating film stops at the upper surface of the uppermost silicon nitride film. Therefore, the operation of the transistor does not become unstable.

In addition, since metal or silicide can be used as the gate material, the resistance of the gate electrode can be reduced, re-applying gate impurities does not affect the Tr characteristics, and the work function is between P+ silicon and n+ silicon. It is easy to control the channel profile.

(Example) FIG. 1 is a sectional view showing the structure of an MO8 field effect transistor showing a first example of the present invention.

An element isolation region 1-2 is provided on the surface of the semiconductor substrate, and a gate electrode of a titanium silicide film 1-5 is formed in the element region via a silicon oxide film 1-3 and a silicon nitride film. A conductivity type impurity opposite to the semiconductor substrate is introduced by ion implantation into this gate and element ■-2 isolation region in a self-aligned manner to form a source.

■-6 A drain region is formed.

■-5 Even though silicide is used as the gate, the silicon nitride film prevents reaction with the silicon oxide film, so the characteristics of the transistor do not become unstable. The advantages of using silicide as the gate material have already been described.

FIG. 3 shows a second embodiment. Silicon nitride film is 2
It has a structure sandwiched between two silicon oxide films 3-3 and 3-5.

3- to In this example, the gate material is a high melting point metal.

The high melting point metal gate material is the silicon oxide film directly below.
Although there is some reaction, it has not reached the level of silicon nitride film.

In this example, the SiO film directly under the gate needs to be quite thick, but since the dielectric constant of the silicon nitride film is sufficiently larger than that of the silicon oxide film, it is effectively equivalent to a thin oxide film, and the transistor The current driving force can be made large.

FIG. 4 shows a third embodiment of the present invention.

The silicon nitride film layer may be at the interface with the semiconductor substrate. Further, by providing a TiN film as a barrier layer on the gate insulating film 4-3, 4-4 and forming a tungsten gate electrode, reaction between the tungsten film 4-6 and the silicon oxide film is prevented.

However, a slight reaction between the TiN film and the silicon oxide film occurs. The effect of the silicon nitride film in this case is as shown in the second embodiment.

A method for manufacturing a gate structure of an MO3 field effect transistor will be described below.

FIGS. 5(a) and 5(b) are cross-sectional views showing the manufacturing process.

The semiconductor substrate is thermally oxidized at 850'C to form a 50A silicon oxide film, then 50 silicon oxide films are deposited by CVD, and further oxidized at 850C to form a 50A silicon oxide film.

Next, polysilicon or amorphous silicon is deposited by CVD.
A thickness of 0.25 μm is formed by the method. Next, Ti is deposited to a thickness of 0.1 μm and a TiN film is deposited to a thickness of 200 by sputtering (FIG. 5(a)).

Next, by annealing in a nitrogen atmosphere at 700°C, 5-6
.

As shown in Fig. 5(b), the reaction between the Ti film and the silicon film is 0.25 μm thick.
115-8 is formed, and Tj which has not reacted with the TiN film on the surface.
However, it can be removed by passing water through it and immersing it in a solution containing ammonia and heating it. On the other hand, when the Tl512 film is formed, it reacts with the underlying oxide film, but at least the silicon nitride film can stop the reaction.

FIGS. 6(a) and 6(b) show another embodiment of the present invention.

6-5, the Ti film and the silicon film are reversed from the embodiment shown in FIG. In this case, there is no need to deposit a TiN film, but if a silicon film is deposited in an oxidizing atmosphere, the Ti film will be oxidized, so it is necessary to select a method that does not use an oxidizing atmosphere, such as sputtering, to deposit the silicon film.

FIGS. 7(a) and 7(b) show another embodiment of the present invention, which involves the formation of a silicon nitride film.

A silicon nitride film can be formed on the surface by thermally oxidizing the semiconductor substrate at 850° C. and then annealing it in an ammonia atmosphere or a nitrogen atmosphere.

The subsequent steps are similar to those in the above embodiment.

Through this process, a thinner gate insulating film can be formed by a simpler process than forming a silicon nitride film.

[Effects of the Invention] According to the present invention, a gate material with high conductivity characteristics can be maintained.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, FIG. 2 is a sectional view of a gate structure, FIGS. 3 and 4 are sectional views showing other embodiments,
FIG. 5, FIG. 6, and FIG. 7 are cross-sectional process diagrams showing a manufacturing method according to an embodiment of the present invention.

Claims (6)

[Claims] (1) Spread at least one silicon nitride film on the semiconductor substrate.
A field effect transistor device with a gate structure consisting of a layered insulating film and a metal layer. (2) The field effect transistor device according to claim (1), wherein the gate metal is a silicide of a high-melting point metal. (3) The field effect transistor device according to claim 1, wherein the gate metal is a TiN, TiW, TiC, WN layer and a high melting point metal layer, or a silicide of a high melting point metal. (4) A field effect transistor device according to any one of claims (1) to (3), characterized in that an insulating film containing at least one silicon nitride film is formed by silicifying the silicon oxide film. Production method. (5) At least one silicon nitride film layer on the semiconductor substrate
An electric field characterized in that it includes a step of forming an insulating film layer having a layer, a step of depositing a polysilicon layer or an amorphous silicon layer, a step of depositing a high melting point metal layer, and a heat treatment step of silicidation. A method for manufacturing an effect transistor device. (6) At least one silicon nitride film layer on the semiconductor substrate
The method is characterized by comprising a step of forming an insulating film layer having a layer, a step of depositing a high melting point metal layer, a step of depositing a polysilicon layer or an amorphous silicon layer, and a heat treatment step of silicidation. A method for manufacturing a field effect transistor device.