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JPH04134853A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH04134853A
JPH04134853A JP25779490A JP25779490A JPH04134853A JP H04134853 A JPH04134853 A JP H04134853A JP 25779490 A JP25779490 A JP 25779490A JP 25779490 A JP25779490 A JP 25779490A JP H04134853 A JPH04134853 A JP H04134853A
Authority
JP
Japan
Prior art keywords
lead
island
wires
wire
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25779490A
Other languages
Japanese (ja)
Other versions
JP2576678B2 (en
Inventor
Yoshihiro Iwase
岩瀬 義裕
Yasuhisa Kobayashi
小林 安久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2257794A priority Critical patent/JP2576678B2/en
Publication of JPH04134853A publication Critical patent/JPH04134853A/en
Application granted granted Critical
Publication of JP2576678B2 publication Critical patent/JP2576678B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce a resin amount flowing between wires in a corner part of a semiconductor element, to reduce wire deformation and to improve reliability and yield of a device by enlarging a width of a hanging lead inside an inner lead. CONSTITUTION:A hanging lead which crosses a resin injection direction among hanging leads between an end part of an inner lead 4 and an island 1 is made a hanging lead 2A which is wider than other parts. Thereby, when a semiconductor element 6 is mounted on the island 1 and the element 6 and the lead 4 are connected by a conductive wire 5, the wide hanging lead 2A is positioned to cover a clearance between two wires a, b and that between c, d; a resin amount flowing between the two wires can be thereby reduced in case of resin sealing. Therefore, deformation of a wire can be prevented and reliability and yield can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関し、特に樹脂
封止型半導体装置用リードフレームの構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and particularly to the structure of a resin-sealed lead frame for a semiconductor device.

〔従来の技術〕[Conventional technology]

従来この種のリードフレームは第4図(a)(b)に示
すように、吊りリードに保持され半導体素子6を搭載す
るアイランド1と、このアイランド1の周囲に設けられ
外部リード3と一体的に形成された内部リード4とから
主に構成されていた。そして、このアイランド1上に半
導体素子6を搭載後、この半導体素子6のポンディング
パッドと内部リード4とを導電性のワイヤー5にて接続
したのち、絶縁性のの樹脂にて封止するのが一般的であ
る。
As shown in FIGS. 4(a) and 4(b), conventional lead frames of this type include an island 1 held by hanging leads and on which a semiconductor element 6 is mounted, and an island 1 provided around this island 1 and integrated with an external lead 3. It was mainly composed of an internal lead 4 formed in the inner lead 4. After mounting the semiconductor element 6 on the island 1, the bonding pad of the semiconductor element 6 and the internal lead 4 are connected with a conductive wire 5, and then sealed with an insulating resin. is common.

しかしながら近年素子が高集積化し、この為半導体素子
が小さくなるので半導体素子と内部り−ド4を接続する
ワイヤー5は長くなる傾向にあった。その反面外部接続
用のリードの数は年々増加する傾向にあるが、内部リー
ド4の先端はワイヤー5の接続の為に最低限の幅を必要
とする為、半導体素子6の1辺当りの長さと、その辺に
対向してワイヤーが接続される内部リード4の先端の総
数の幅は、かなり広くなる傾向にあった。その為増々ア
イランド1と内部リード4の先端との間隔が大きくなる
ので、結果的にはワイヤー5の長さが長くなる傾向にあ
った。
However, in recent years, devices have become highly integrated, and as a result, semiconductor devices have become smaller, so the wires 5 connecting the semiconductor devices and the internal wires 4 have tended to become longer. On the other hand, the number of leads for external connection tends to increase year by year, but since the tip of the internal lead 4 requires a minimum width for connecting the wire 5, the length per side of the semiconductor element 6 is In addition, the width of the total number of tips of the internal leads 4 to which wires are connected to opposite sides tends to be quite wide. As a result, the distance between the island 1 and the tip of the internal lead 4 becomes larger, and as a result, the length of the wire 5 tends to become longer.

また、半導体素子6と内部リード4をワイヤー5にて接
続した場合、半導体素子のコーナ一部に位置するワイヤ
ーは半導体素子のコーナ一部を挟むようになるので、他
の位置のワイヤに比ベワイヤー間隔が広くなる。半導体
素子を樹脂封止した場合は、アイランドの上部の樹脂が
早く充填されるため、樹脂はワイヤー5、内部リード4
及びアイランド1のすき間より矢印のように下部に流れ
る。この時、ワイヤー間隔が広い程ワイヤー間に流れこ
む樹脂量が太くなる為、ワイヤーは変形しやすくなる。
In addition, when the semiconductor element 6 and the internal lead 4 are connected by the wire 5, the wire located at a corner of the semiconductor element will sandwich a part of the corner of the semiconductor element, so the wire will be smaller than the wire at other positions. The spacing becomes wider. When a semiconductor element is encapsulated with resin, the upper part of the island is filled with resin quickly, so the resin is applied to wires 5 and internal leads 4.
and flows downward from the gap between islands 1 as shown by the arrow. At this time, the wider the distance between the wires, the greater the amount of resin that flows between the wires, making the wires more likely to deform.

従ってワイヤー間隔が広い半導体素子6のコーナ一部に
位置するワイヤー5は変形しやすい傾向にあった。
Therefore, the wires 5 located at some corners of the semiconductor element 6 where the wire spacing is wide tend to be easily deformed.

このように近年の高集積化と外部リードの多リード化に
よりワイヤー長は長くなり、またワイヤー間隔と樹脂流
動によるワイヤー変形の関係から、半導体素子のコーナ
一部のワイヤーは変形しやすく、電気的にショートが発
生しやすいという傾向にあった。
As described above, the wire length has become longer due to the recent trend toward high integration and the increase in the number of external leads, and due to the relationship between wire spacing and wire deformation due to resin flow, some wires at the corners of semiconductor devices are easily deformed, causing electrical problems. There was a tendency for short circuits to occur easily.

〔発明が解決しようとする課題〕 上述したように従来の半導体装置用のリードフレームは
、半導体素子の高集積化と外部リード本数の多数ピン化
により、接続されたワイヤーが長くなると共に、ワイヤ
ー間隔と樹脂の流動によるワイヤー変形の関係から、半
導体素子のコーナー部のワイヤーは変形しやすく、ワイ
ヤーが切断したり、電気的にショートしたりして歩留り
が低下するという問題があった。また、ワイヤー変形に
よりワイヤー間隔が極端に狭くなった場合、半導体装置
を使用中にワイヤーが電気的にショートすることもあり
、信頼性上問題があった。
[Problems to be Solved by the Invention] As described above, in conventional lead frames for semiconductor devices, due to the high integration of semiconductor elements and the increase in the number of external leads, the connected wires have become longer and the wire spacing has become shorter. Due to the relationship between wire deformation due to the flow of resin and wire deformation due to the flow of resin, wires at the corner portions of semiconductor devices are easily deformed, causing problems such as wire breakage or electrical short-circuiting, resulting in a decrease in yield. Further, if the wire spacing becomes extremely narrow due to wire deformation, the wires may be electrically shorted during use of the semiconductor device, which poses a reliability problem.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置用リードフレームは、半導体チップ
を搭載するアイランドと、このアイランドを保持する吊
りリードと、前記アイランドの周辺に設けられ外部リー
ドと一体的に形成された内部リードとを有する半導体装
置用リードフレームにおいて、前記内部リードの先端部
からアイランド間の前記吊りリードの幅は他の部分より
広く形成されているものである。
A lead frame for a semiconductor device of the present invention includes an island on which a semiconductor chip is mounted, a hanging lead that holds the island, and an internal lead provided around the island and integrally formed with an external lead. In the lead frame, the width of the hanging lead between the islands is wider than the width of the other part from the tip of the internal lead.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例の平面図である。FIG. 1 is a plan view of a first embodiment of the invention.

第1図においてリードフレームは、半導体チップを搭載
するアイランド1と、このアイランド1を保持する吊り
リード2と、アイランド1の周辺に設けられ外部リード
3と一体的に形成された内部4とから主に構成されてい
るが、特に内部り一ド4の先端部からアイランド1間の
吊りリードのうち、樹脂注入方向を横切る吊りリードを
他の部分より幅の広い吊りリード2人としである。
In FIG. 1, the lead frame mainly consists of an island 1 on which a semiconductor chip is mounted, a hanging lead 2 that holds the island 1, and an inner part 4 provided around the island 1 and integrally formed with an external lead 3. In particular, among the suspension leads between the tip of the inner board 4 and the island 1, the suspension lead that crosses the resin injection direction is made of two suspension leads that are wider than the other parts.

このように構成された第1の実施例によれば、第2図に
示すように、アイランド1に半導体素子6を搭載し、そ
の後導電性のワイヤー5にて半導体素子6と内部リード
4を接続した場合、半導体素子6のコーナ一部に位置す
る2本のワイヤーabおよびc、dの間隙を覆うように
幅の広い吊りリード2Aが位置するので、樹脂封止した
場合にこの2本のワイヤー間に流動する樹脂量を低減さ
せることができる。従ってワイヤーの変形が防止される
According to the first embodiment configured in this way, as shown in FIG. In this case, since the wide suspension lead 2A is positioned so as to cover the gap between the two wires ab, c, and d located at a part of the corner of the semiconductor element 6, when the semiconductor element 6 is sealed with resin, these two wires The amount of resin flowing between the two can be reduced. Therefore, deformation of the wire is prevented.

第3図は本発明の第2実施例の平面図である。FIG. 3 is a plan view of a second embodiment of the invention.

第3図に示したように第2の実施例では、4方向の吊り
リードについて内部リード4の先端より内側に位置する
部分の吊りリード2の幅を広くしたものである。本箱2
の実施例によれば、半導体素子の4つのコーナ一部に位
置するワイヤーの変形を抑制できるという利点がある。
As shown in FIG. 3, in the second embodiment, the width of the suspension lead 2 in the portion located inside the tip of the internal lead 4 is widened for the suspension leads in four directions. Bookcase 2
According to the embodiment, there is an advantage that deformation of the wires located at some of the four corners of the semiconductor element can be suppressed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、内部リードより内側の吊
りリードの幅を広くすることにより、樹脂封止した場合
半導体素子のコーナ一部のワイヤー間に流動する樹脂量
を低減させることができるので、樹脂の流動によるワイ
ヤー変形を従来より低減できるという効果がある。この
ため半導体装置の信頼性及び歩留りを向上させることが
できる。
As explained above, the present invention makes it possible to reduce the amount of resin that flows between the wires at a part of the corner of the semiconductor element when the semiconductor element is sealed with resin by making the width of the suspension lead wider than the internal lead. This has the effect of reducing wire deformation due to resin flow compared to the conventional method. Therefore, reliability and yield of the semiconductor device can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の第1の実施例の平面図及び
半導体素子を搭載した場合の平面図、第3図は本発明の
第2の実施例の平面図、第4図(a)、(b)は従来の
半導体装置用リードフレームに半導体素子を搭載した場
合の平面図及びA−A線断面図である。 1・・・アイランド、2・・・吊りリード、2A・・・
幅の広い吊りリード、3・・・外部リード、4・・・内
部リード、5・・ワイヤー、6・・・半導体素子。
1 and 2 are a plan view of the first embodiment of the present invention and a plan view when a semiconductor element is mounted, FIG. 3 is a plan view of the second embodiment of the present invention, and FIG. a) and (b) are a plan view and a cross-sectional view taken along the line A-A when a semiconductor element is mounted on a conventional lead frame for a semiconductor device. 1...Island, 2...Hanging lead, 2A...
Wide suspension lead, 3...external lead, 4...internal lead, 5...wire, 6...semiconductor element.

Claims (1)

【特許請求の範囲】[Claims]  半導体チップを搭載するアイランドと、このアイラン
ドを保持する吊りリードと、前記アイランドの周辺に設
けられ外部リードと一体的に形成された内部リードとを
有する半導体装置用リードフレームにおいて、前記内部
リードの先端部からアイランド間の前記吊りリードの幅
は他の部分より広く形成されていることを特徴とする半
導体装置用リードフレーム。
In a lead frame for a semiconductor device having an island on which a semiconductor chip is mounted, a suspension lead holding the island, and an internal lead provided around the island and integrally formed with an external lead, the tip of the internal lead A lead frame for a semiconductor device, characterized in that the width of the suspension lead between the island and the island is wider than other parts.
JP2257794A 1990-09-27 1990-09-27 Lead frame for semiconductor device Expired - Fee Related JP2576678B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2257794A JP2576678B2 (en) 1990-09-27 1990-09-27 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2257794A JP2576678B2 (en) 1990-09-27 1990-09-27 Lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH04134853A true JPH04134853A (en) 1992-05-08
JP2576678B2 JP2576678B2 (en) 1997-01-29

Family

ID=17311202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2257794A Expired - Fee Related JP2576678B2 (en) 1990-09-27 1990-09-27 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JP2576678B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19732807B4 (en) * 1997-01-24 2004-11-25 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Integrated circuit component
US8791555B2 (en) 2010-03-29 2014-07-29 Fujitsu Semiconductor Limited Semiconductor device and lead frame

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176260A (en) * 1984-02-23 1985-09-10 Toshiba Corp Manufacture of lead frame for semiconductor device
JPH02142545U (en) * 1989-05-02 1990-12-04

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176260A (en) * 1984-02-23 1985-09-10 Toshiba Corp Manufacture of lead frame for semiconductor device
JPH02142545U (en) * 1989-05-02 1990-12-04

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19732807B4 (en) * 1997-01-24 2004-11-25 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Integrated circuit component
US8791555B2 (en) 2010-03-29 2014-07-29 Fujitsu Semiconductor Limited Semiconductor device and lead frame

Also Published As

Publication number Publication date
JP2576678B2 (en) 1997-01-29

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