[go: up one dir, main page]

JPH04127601U - Chip type positive temperature coefficient thermistor - Google Patents

Chip type positive temperature coefficient thermistor

Info

Publication number
JPH04127601U
JPH04127601U JP4419391U JP4419391U JPH04127601U JP H04127601 U JPH04127601 U JP H04127601U JP 4419391 U JP4419391 U JP 4419391U JP 4419391 U JP4419391 U JP 4419391U JP H04127601 U JPH04127601 U JP H04127601U
Authority
JP
Japan
Prior art keywords
temperature coefficient
positive temperature
type positive
thermistor
coefficient thermistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4419391U
Other languages
Japanese (ja)
Inventor
吉晶 阿部
淳 小島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP4419391U priority Critical patent/JPH04127601U/en
Publication of JPH04127601U publication Critical patent/JPH04127601U/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Thermistors And Varistors (AREA)

Abstract

(57)【要約】 【目的】 チップ型正特性サーミスタの熱応答性を向上
させるとともに、高密度実装への適応性を改善する。 【構成】 サーミスタ素体1を、上側主面1aの表面積
が下側主面1bの表面積よりも小さい上すぼまりの形状
に形成して、その体積と表面積を小さくする。
(57) [Summary] [Purpose] To improve the thermal response of a chip-type positive temperature coefficient thermistor and to improve its adaptability to high-density packaging. [Structure] The thermistor element 1 is formed into an upwardly tapered shape in which the surface area of the upper main surface 1a is smaller than the surface area of the lower main surface 1b, thereby reducing its volume and surface area.

Description

【考案の詳細な説明】[Detailed explanation of the idea]

【0001】0001

【産業上の利用分野】[Industrial application field]

この考案は、チップ型正特性サーミスタに関し、詳しくは、熱応答性に優れ、 かつ、高密度実装が可能なチップ型正特性サーミスタに関する。 This invention relates to a chip type positive temperature coefficient thermistor. The present invention also relates to a chip-type positive temperature coefficient thermistor that can be mounted at high density.

【0002】0002

【従来の技術】[Conventional technology]

従来のチップ型正特性サーミスタとしては、例えば、図9に示すようなチップ 型正特性サーミスタがある。このチップ型正特性サーミスタ50は、薄型の直方 体形状の正特性を有するサーミスタ素体60の両端側に一対の電極70,70を 配設した構造を有している。そして、一対の電極70,70はそれぞれ、サーミ スタ素体60の主面、側面及び端面に形成された主面電極70a,70a、側面 電極70b,70b及び端面電極70cから構成されており、裏面側も図9と同 じ構造になっている。 As a conventional chip type positive temperature coefficient thermistor, for example, a chip as shown in Fig. 9 is used. There is a positive temperature coefficient thermistor. This chip type positive temperature coefficient thermistor 50 is a thin rectangular A pair of electrodes 70, 70 are provided at both ends of a thermistor element body 60 having positive body shape characteristics. It has an arranged structure. The pair of electrodes 70 and 70 each have a thermium Main surface electrodes 70a, 70a formed on the main surface, side surfaces, and end surfaces of the star body 60, and the side surfaces It is composed of electrodes 70b, 70b and an end electrode 70c, and the back side is also the same as in FIG. It has the same structure.

【0003】 このような、チップ型正特性サーミスタ50は、大きな正の抵抗温度係数を有 しており、キュリー温度を越えると抵抗値が急激に増大して、通過する電流量を 減少させることから、回路の過熱保護用や過電流保護用など種々の用途に広く用 いられているが、近年、信頼性を向上させるために、従来以上に熱応答性に優れ たチップ型正特性サーミスタが要求されるようになっており、さらに、機器の小 型化に伴い、高密度の面実装回路に適応できるチップ型正特性サーミスタへの要 求が高まっている。0003 Such a chip-type positive temperature coefficient thermistor 50 has a large positive temperature coefficient of resistance. When the Curie temperature is exceeded, the resistance value increases rapidly, reducing the amount of current passing through it. It is widely used for various purposes such as circuit overheat protection and overcurrent protection. However, in recent years, in order to improve reliability, products with better thermal response than before have been developed. chip-type positive temperature coefficient thermistors are now required, and the equipment is becoming smaller and smaller. With the trend toward new types, the requirements for chip-type positive temperature coefficient thermistors that can be applied to high-density surface-mount circuits have increased. demand is increasing.

【0004】0004

【考案が解決しようとする課題】[Problem that the idea aims to solve]

しかし、上記従来のチップ型正特性サーミスタ50においては、サーミスタ素 体60の体積及び表面積が大きいため、チップ型正特性サーミスタの熱容量が大 きくなるとともに、表面からの放熱量も大きくなり、十分な熱応答性を得ること ができず、信頼性が低いという問題点がある。 However, in the conventional chip type positive temperature coefficient thermistor 50, the thermistor element Since the volume and surface area of the body 60 are large, the chip type positive temperature coefficient thermistor has a large heat capacity. As the temperature increases, the amount of heat dissipated from the surface also increases, ensuring sufficient thermal response. There is a problem that it is not possible to do so and has low reliability.

【0005】 さらに、上記従来のチップ型正特性サーミスタ50においては、図10に示す ように、例えば、チップ型正特性サーミスタ50を基板81に配設し、電極70 をランド82にはんだ付けして接続する場合、上側の主面電極70aから側面電 極70b及び端面電極70cにわたってはんだ83が付着して、大量の溶融はん だ83がはんだ付け部に溜まる。その結果、チップ型正特性サーミスタ50を基 板81上に高密度に実装する場合、上側の主面電極70aなどに付着した溶融は んだ83が隣接するチップ型正特性サーミスタ50に向って流れ込み、回路を短 絡させるため、実装の高密度化が妨げられるという問題点がある。[0005] Furthermore, in the conventional chip type positive temperature coefficient thermistor 50, as shown in FIG. For example, the chip type positive temperature coefficient thermistor 50 is disposed on the substrate 81, and the electrode 70 When connecting by soldering to the land 82, the side electrode is connected from the upper main surface electrode 70a. Solder 83 adheres to the pole 70b and end electrode 70c, and a large amount of molten solder 83 accumulates in the soldering area. As a result, based on the chip type positive temperature coefficient thermistor 50, When mounting on the board 81 with high density, the melt adhering to the upper main surface electrode 70a etc. The solder 83 flows toward the adjacent chip type positive temperature coefficient thermistor 50, shortening the circuit. There is a problem in that high-density packaging is hindered because of the interconnection.

【0006】 この考案は、上記の問題点を解決するものであり、熱応答性に優れているとと もに、高密度実装に適したチップ型正特性サーミスタを提供することを目的とす る。[0006] This invention solves the above problems and is said to have excellent thermal response. Our aim is to provide chip-type positive temperature coefficient thermistors suitable for high-density packaging. Ru.

【0007】[0007]

【課題を解決するための手段】[Means to solve the problem]

上記目的を達成するために、この考案のチップ型正特性サーミスタは、サーミ スタ素体の両端側に一対の電極を設けてなるチップ型正特性サーミスタにおいて 、サーミスタ素体を、上側主面の表面積が下側主面の表面積よりも小さい上すぼ まりの形状に形成したことを特徴とする。 In order to achieve the above purpose, the chip-type positive temperature coefficient thermistor of this invention In a chip-type positive temperature coefficient thermistor that has a pair of electrodes on both ends of a star element, , the thermistor element is placed in a top-bottom configuration in which the surface area of the upper principal surface is smaller than the surface area of the lower principal surface. It is characterized by being formed in the shape of a ball.

【0008】[0008]

【作用】[Effect]

この考案のチップ型正特性サーミスタは、サーミスタ素体が上すぼまりの形状 に形成されているため、上側がすぼめられている分だけ、従来のように上側がす ぼめられていないサーミスタ素体より体積及び表面積が小さくなり、チップ型正 特性サーミスタ全体としての熱容量が小さくなるとともに、放熱量が減少して熱 応答性が向上する。また、この考案のチップ型正特性サーミスタは、上すぼまり の形状を有しており、端面または側面の少なくとも一方は垂直ではなくある程度 の傾きを有しているため、電極上の溶融はんだが流れ落ちにくく、実装時に隣接 する電子部品や線路などへの溶融はんだの流れ込みが抑制され、高密度の面実装 を行なうことが可能になる。 The chip-type positive temperature coefficient thermistor of this invention has a thermistor body that tapers upward. Because the upper side is narrowed, the upper side is not completely closed like the conventional one. The volume and surface area of the thermistor element is smaller than that of a non-concave thermistor element, making it suitable for chip-type positive CharacteristicsAs the heat capacity of the thermistor as a whole decreases, the amount of heat dissipated decreases, causing heat loss. Improves responsiveness. In addition, the chip type positive temperature coefficient thermistor of this invention has a tapered top. , and at least one of the end faces or sides is not vertical but somewhat Because it has a slope of This prevents molten solder from flowing into electronic components and lines, allowing for high-density surface mounting. It becomes possible to do this.

【0009】[0009]

【実施例】【Example】

以下、この考案の実施例を図に基づいて説明する。図1は、この考案の一実施 例にかかるチップ型正特性サーミスタを示す斜視図であり、図2及び図3はその 断面図及び平面図である。これらの図に示すように、このチップ型正特性サーミ スタAにおいて、正特性を有するサーミスタ素体1は図1及び図2に示すように 、上すぼまりで、断面形状が台形状(いわゆる、角すい台形状)であり、その上 面(上側主面)1aの面積は、下面(下側主面)1bの面積より狭くなっている 。そして、サーミスタ素体1の両端側には、電極2,2が形成されており、この 電極2,2は、傾き(θ)を有する端面1cから、上面1a側及び下面1b側に まで回り込んでいる。なお、この電極2,2は、特に図示しないが、オーミック 性を有する下層電極(図示せず)の上にはんだ付け性に優れた上層電極(図示せ ず)を形成することにより形成されている。 なお、上記チップ型正特性サーミスタAの各部の寸法を、例えば、W=1.5 mm,L=3.0mm,L’=2.0mm,T=0.6mm,G=1.0mm,θ=50° と構成する。 Hereinafter, an embodiment of this invention will be described based on the drawings. Figure 1 shows one implementation of this idea. 2 is a perspective view showing a chip-type positive temperature coefficient thermistor according to an example, and FIGS. 2 and 3 are They are a sectional view and a plan view. As shown in these figures, this chip type positive temperature coefficient thermistor In star A, the thermistor body 1 having positive characteristics is as shown in FIGS. 1 and 2. , the top tapers, the cross-sectional shape is trapezoidal (so-called trapezoidal shape), and The area of the surface (upper main surface) 1a is smaller than the area of the lower surface (lower main surface) 1b. . Electrodes 2, 2 are formed on both ends of the thermistor body 1. The electrodes 2, 2 extend from the end surface 1c having an inclination (θ) to the upper surface 1a side and the lower surface 1b side. It goes around to Note that these electrodes 2, 2 are ohmic electrodes, although not particularly shown. An upper layer electrode (not shown) with excellent solderability is placed on top of a lower layer electrode (not shown) with excellent solderability. ). The dimensions of each part of the chip type positive temperature coefficient thermistor A are, for example, W=1.5. mm, L=3.0mm, L'=2.0mm, T=0.6mm, G=1.0mm, θ=50° It consists of:

【0010】 このように構成されたチップ型正特性サーミスタAは、サーミスタ素体1が上 すぼまりの形状に形成されており、上側がすぼめられている分だけ、従来例の上 側がすぼめられていないサーミスタ素体50(図9)より体積及び表面積が小さ いため、正特性サーミスタA全体としての熱容量が小さくなるとともに、放熱量 が減少して熱応答性が向上する。0010 The chip type positive temperature coefficient thermistor A configured in this way has the thermistor body 1 on top. It is formed in a tapered shape, and the upper part is narrower than the conventional model. The volume and surface area are smaller than the thermistor element 50 (FIG. 9) whose sides are not narrowed. Therefore, the heat capacity of the PTC thermistor A as a whole becomes smaller, and the amount of heat dissipated becomes smaller. decreases and improves thermal responsiveness.

【0011】 図4は周囲温度(雰囲気温度)を変化させたときの上記実施例のチップ型正特 性サーミスタAの温度の変化の状態を示す線図であり、横軸の経過時間が0秒の 時点から周囲温度が上昇したことを示している。図4より、上記実施例の正特性 サーミスタA(の温度)は、周囲温度の変化に速やかに追随しており、従来の正 特性サーミスタと比較して熱応答性が著しく向上していることがわかる。[0011] Figure 4 shows the chip type characteristic of the above example when the ambient temperature (atmosphere temperature) is changed. It is a diagram showing the state of temperature change of the thermistor A, and the elapsed time on the horizontal axis is 0 seconds. This indicates that the ambient temperature has increased since then. From FIG. 4, the positive characteristics of the above example Thermistor A (its temperature) quickly follows changes in ambient temperature, and is It can be seen that the thermal response is significantly improved compared to the characteristic thermistor.

【0012】 また、図5は上記実施例のチップ型正特性サーミスタを回路基板に面実装する 場合の状態を示している。この実施例のチップ型正特性サーミスタAは、上すぼ まりの形状を有しており、端面1cが垂直ではなく、傾き(θ)を有しているた め、電極2の溶融はんだ保持能力は大きい。したがって、図5に示すように、溶 融はんだ3が、基板4上のランド5から隣接するチップ型正特性サーミスタBに 向って流れ込んで短絡を生じることを確実に防止することが可能になり、高密度 の面実装を行なうことができる。0012 Moreover, FIG. 5 shows the surface mounting of the chip-type positive temperature coefficient thermistor of the above embodiment on a circuit board. Indicates the state of the case. The chip type positive temperature coefficient thermistor A of this example has an upper It has a round shape, and the end surface 1c is not vertical but has an inclination (θ). Therefore, the electrode 2 has a large ability to hold molten solder. Therefore, as shown in Figure 5, The melted solder 3 is applied from the land 5 on the substrate 4 to the adjacent chip type positive temperature coefficient thermistor B. This makes it possible to reliably prevent short circuits caused by flowing toward the opposite direction. Surface mounting can be performed.

【0013】 なお、上記実施例においては、断面形状が台形のサーミスタ素体1を用い、そ の傾きを有する端面1cから上面1a及び下面1bにかけて電極を形成した場合 について説明したが、サーミスタ素体1の形状及び電極2の形状は上記実施例に 限定されるものではなく、図6〜図8に示すような、種々の形状のサーミスタ素 体1を用いその両端側に電極2を形成したチップ型正特性サーミスタC,D,E はいずれもこの考案の範囲に含まれるものである。すなわち、図6のチップ型正 特性サーミスタCは、端面1cが垂直であるが、側面1dが傾きを有する上すぼ まりの形状のサーミスタ素体1を用い、その垂直の端面1cには電極を形成せず 、上下両面1a,1b及び側面1dに電極2を形成している。また、図7のチッ プ型正特性サーミスタDは、端面1c及び側面1dがいずれも傾きを有する上す ぼまりの形状のサーミスタ素体1を用い、その端面1c,側面1d及び下面1b に電極2を形成している。さらに、図8のチップ型正特性サーミスタEは、端面 1cを凹曲面状に形成した上すぼまりの形状のサーミスタ素体1を用い、その端 面1c及び下面1bに電極2を形成している。[0013] In the above embodiment, the thermistor element 1 having a trapezoidal cross-sectional shape is used. When electrodes are formed from the end surface 1c having an inclination of , to the upper surface 1a and the lower surface 1b However, the shape of the thermistor body 1 and the shape of the electrode 2 are the same as in the above embodiment. Thermistor elements of various shapes, such as but not limited to those shown in FIGS. 6 to 8, can be used. Chip-type positive temperature coefficient thermistors C, D, and E in which electrodes 2 are formed on both ends using a body 1. All of these are included within the scope of this invention. In other words, the chip type positive The characteristic thermistor C has an upper bottom end face 1c that is vertical but a side face 1d that is inclined. A ball-shaped thermistor element 1 is used, and no electrode is formed on the vertical end surface 1c. , electrodes 2 are formed on the upper and lower surfaces 1a, 1b and the side surface 1d. Also, the chip in Figure 7 The double-type positive temperature coefficient thermistor D has an upper end face 1c and a side face 1d both having an inclination. A thermistor body 1 having a hollow shape is used, and its end face 1c, side face 1d, and bottom face 1b are An electrode 2 is formed on the surface. Furthermore, the chip type positive temperature coefficient thermistor E in FIG. A thermistor body 1 having a concave curved shape and tapering at the top is used, and its end Electrodes 2 are formed on the surface 1c and the lower surface 1b.

【0014】 これら図6〜図8に示すチップ型正特性サーミスタC,D,Eについても上記 実施例の正特性サーミスタAと同様の効果を得ることができる。[0014] The chip-type positive temperature coefficient thermistors C, D, and E shown in FIGS. 6 to 8 are also described above. The same effect as the positive temperature coefficient thermistor A of the embodiment can be obtained.

【0015】[0015]

【考案の効果】[Effect of the idea]

上述のように、この考案のチップ型正特性サーミスタは、サーミスタ素体を上 すぼまりの形状に形成しているので、上側がすぼめられている分だけサーミスタ 素体の体積及び表面積が小さくなり、正特性サーミスタ全体としての熱容量が小 さくなるとともに、放熱量が減少して熱応答性が向上する。 As mentioned above, the chip-type positive temperature coefficient thermistor of this invention has a thermistor body on top. Since it is formed in a convergent shape, the thermistor is only as narrow as the upper part. The volume and surface area of the element body are small, and the heat capacity of the positive temperature coefficient thermistor as a whole is small. As the temperature decreases, the amount of heat dissipated decreases and the thermal response improves.

【0016】 また、この考案のチップ型正特性サーミスタは、上すぼまりの形状を有してお り、端面または側面の少なくとも一方は垂直ではなくある程度の傾きを有してい るため、電極の溶融はんだ保持能力が大きく、溶融はんだが流れ出しにくいため 、隣接する電子部品や線路などへの溶融はんだの流れ込みを効果的に防止して、 高密度な実装を行なうことができる。[0016] In addition, the chip-type positive temperature coefficient thermistor of this invention has a shape that tapers upward. Therefore, at least one of the end face or side face is not vertical but has a certain degree of inclination. Therefore, the electrode has a large ability to hold molten solder, making it difficult for molten solder to flow out. , effectively prevents molten solder from flowing into adjacent electronic components, lines, etc. High-density packaging is possible.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】この考案の一実施例にかかるチップ型正特性サ
ーミスタを示す斜視図である。
FIG. 1 is a perspective view showing a chip type positive temperature coefficient thermistor according to an embodiment of the present invention.

【図2】図1のチップ型正特性サーミスタのII−II線断
面図である。
FIG. 2 is a sectional view taken along line II-II of the chip type positive temperature coefficient thermistor of FIG. 1;

【図3】この考案の一実施例にかかるチップ型正特性サ
ーミスタを示す平面図である。
FIG. 3 is a plan view showing a chip type positive temperature coefficient thermistor according to an embodiment of the invention.

【図4】この考案の一実施例にかかるチップ型正特性サ
ーミスタの熱応答性を示す線図である。
FIG. 4 is a diagram showing the thermal response of a chip type positive temperature coefficient thermistor according to an embodiment of the present invention.

【図5】この考案の一実施例にかかるチップ型正特性サ
ーミスタを基板上に実装した状態を示す断面図である。
FIG. 5 is a sectional view showing a state in which a chip type positive temperature coefficient thermistor according to an embodiment of the invention is mounted on a substrate.

【図6】この考案の一実施例にかかるチップ型正特性サ
ーミスタを示す斜視図である。
FIG. 6 is a perspective view showing a chip type positive temperature coefficient thermistor according to an embodiment of the invention.

【図7】この考案の一実施例にかかるチップ型正特性サ
ーミスタを示す斜視図である。
FIG. 7 is a perspective view showing a chip type positive temperature coefficient thermistor according to an embodiment of the invention.

【図8】この考案の一実施例にかかるチップ型正特性サ
ーミスタを示す斜視図である。
FIG. 8 is a perspective view showing a chip type positive temperature coefficient thermistor according to an embodiment of the invention.

【図9】従来のチップ型正特性サーミスタを示す斜視図
である。
FIG. 9 is a perspective view showing a conventional chip type positive temperature coefficient thermistor.

【図10】従来のチップ型正特性サーミスタを基板上に
実装した状態を示す断面図である。
FIG. 10 is a cross-sectional view showing a state in which a conventional chip type positive temperature coefficient thermistor is mounted on a substrate.

【符号の説明】[Explanation of symbols]

A チップ型正特性サーミスタ 1 サーミスタ素体 1a サーミスタ素体の上面(上側主面) 1b サーミスタ素体の下面(下側主面) 2 電極 A Chip type positive temperature coefficient thermistor 1 Thermistor element 1a Upper surface of thermistor element (upper main surface) 1b Lower surface of thermistor element (lower main surface) 2 electrodes

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 サーミスタ素体の両端側に一対の電極を
設けてなるチップ型正特性サーミスタにおいて、サーミ
スタ素体を、上側主面の表面積が下側主面の表面積より
も小さい上すぼまりの形状に形成したことを特徴とする
チップ型正特性サーミスタ。
1. A chip-type positive temperature coefficient thermistor in which a pair of electrodes are provided on both ends of a thermistor element, in which the thermistor element is formed into an upper tapered part in which the surface area of the upper main surface is smaller than the surface area of the lower main surface. A chip type positive temperature coefficient thermistor characterized by being formed in the shape of.
JP4419391U 1991-05-15 1991-05-15 Chip type positive temperature coefficient thermistor Withdrawn JPH04127601U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4419391U JPH04127601U (en) 1991-05-15 1991-05-15 Chip type positive temperature coefficient thermistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4419391U JPH04127601U (en) 1991-05-15 1991-05-15 Chip type positive temperature coefficient thermistor

Publications (1)

Publication Number Publication Date
JPH04127601U true JPH04127601U (en) 1992-11-20

Family

ID=31924385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4419391U Withdrawn JPH04127601U (en) 1991-05-15 1991-05-15 Chip type positive temperature coefficient thermistor

Country Status (1)

Country Link
JP (1) JPH04127601U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873836B1 (en) 1999-03-03 2005-03-29 Parkervision, Inc. Universal platform module and methods and apparatuses relating thereto enabled by universal frequency translation technology
US6879817B1 (en) 1999-04-16 2005-04-12 Parkervision, Inc. DC offset, re-radiation, and I/Q solutions using universal frequency translation technology
US7194246B2 (en) 1998-10-21 2007-03-20 Parkervision, Inc. Methods and systems for down-converting a signal using a complementary transistor structure
US7379883B2 (en) 2002-07-18 2008-05-27 Parkervision, Inc. Networking methods and systems

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7194246B2 (en) 1998-10-21 2007-03-20 Parkervision, Inc. Methods and systems for down-converting a signal using a complementary transistor structure
US6873836B1 (en) 1999-03-03 2005-03-29 Parkervision, Inc. Universal platform module and methods and apparatuses relating thereto enabled by universal frequency translation technology
US6879817B1 (en) 1999-04-16 2005-04-12 Parkervision, Inc. DC offset, re-radiation, and I/Q solutions using universal frequency translation technology
US7379883B2 (en) 2002-07-18 2008-05-27 Parkervision, Inc. Networking methods and systems

Similar Documents

Publication Publication Date Title
JPS6022538Y2 (en) Chip type fuse
JPH04127601U (en) Chip type positive temperature coefficient thermistor
WO2017000897A1 (en) Reflow solderable positive temperature coefficient circuit protective device
US5495223A (en) Hybrid integrated circuit device
JPH0465046A (en) Chip-type fuse resistor
JP2003243812A (en) Electronic component mounting structure
JPS61124071A (en) Electric connector
JPS5843762Y2 (en) Chip type positive temperature coefficient thermistor
JP7802805B2 (en) Multilayer Electrical Devices
JPH0744086Y2 (en) Isolator mounting structure
JP2963278B2 (en) Network element
KR200154810Y1 (en) A structure for protecting a thermistor's leaching
KR100474950B1 (en) Mounting plate
JPH06104558A (en) Mounting structure of electronic component package on wiring board
WO2017000896A1 (en) Reflow solderable positive temperature coefficient circuit protection device
JP2581253B2 (en) Hybrid integrated circuit board
KR100723193B1 (en) Flexible printed circuit board with improved terminal structure
JP2522897Y2 (en) Surface Mount Positive Thermistor
JPH0786001A (en) Variable resistor
KR100673682B1 (en) PCB element and its PCB mounting structure with improved lead structure
JP2006278793A (en) Temperature detection element
JPH10200246A (en) Printed circuit board
US20020180576A1 (en) Chip thermistor and chip thermistor mounting structure
JPH0350616Y2 (en)
JP2681178B2 (en) Transistor mounting method

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19950810