JPH04127601A - Frequency conversion circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for provision of DC balance by applying <=sets of timing pulse to <= sets of switches, applying switching control to each switch so as to output a signal whose frequency is converted into a sum or a difference between an input signal frequency and a local oscillating signal frequency from a low pass filter. CONSTITUTION:A clock signal (e) is fed to a timing pulse generator 11 from an input terminal Ieta2 and the timing pulse generator 11 generates an outputs timing pulses T1-T4 and they are fed to switches S1-S4 respectively, which are on/off-controlled. That is, when each of the timing pulses T1-T4 is at an H level, since the switches S1-S4 are closed, signals (j) are synthesized and the resulting signal is fed to an LPF (low pass filter) 13. A high frequency switching component is eliminated in the LPF 13 and a signal (k) is outputted from an output terminal Out. Thus, a problem of DC balance or linearity or the like is not almost caused.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frequency conversion circuit, and is particularly applicable to various devices in the field of wireless communications, such as SSB communication devices and secret communication devices using frequency inversion of audio signals. The present invention relates to a frequency conversion circuit suitable for this purpose.

[Conventional technology]

A common method for frequency conversion is to perform multiplication using a multiplier or balanced modulator, and convert the sum and difference components of the outputs into P
Alternatively, two balanced modulators can be used to supply the direct signal of the input signal and local oscillation signal, and the +π phase signal of the input signal and local oscillation signal to the balanced modulator. There is a frequency conversion method that eliminates the need for an r-wave generator in principle by adding or subtracting the output of a balanced modulator.

This conventional technique will be explained with reference to FIGS. 2 and 3. FIG. 2 shows a frequency conversion circuit that does not require an LPF (low frequency filter) in principle, and is often used as a modulation/demodulation circuit for SSB communications. Also, Figure 3 (
^) to (H) are signal waveform diagrams of each part of the circuit. If the signal a entering the input terminal In+ is a cosine wave as shown in FIG. be done. These signals a and b are each fed to a multiplier (or balanced modulator) 2
and 4.

On the other hand, from the input terminal 1n2, a carrier signal C as shown in FIG. 0)) is supplied to the multiplier 4. Therefore, in the multiplier 4, the signal d and the signal s are multiplied to produce a double 5ide band signal f as shown in FIG.
is generated, and the multiplier 2 outputs a double-sided band wave signal e as shown in FIG. These sideband signals e and f are added by an adder 4, and an added output signal g (see (G) in the figure) is outputted from an output terminal. Note that instead of using the adder 4, a subtracter may be used to subtract both signals to obtain an output signal. Observing the waveform of signal g, we see that it is a suitable 3I! By removing the switching component using a filter with a cut-off frequency (low-pass P-wave filter), it is possible to obtain a signal whose frequency has been converted compared to the above signal a, as shown in (H) in the same figure. Recognize.

[Problems to be solved by the present invention]

By the way, in a frequency conversion circuit that uses multiple multipliers, the accuracy of the DC balance in multipliers 2 and 4 is an important factor, and if the balance is even slightly disturbed, the waveform of the frequency conversion signal will be distorted or collapsed. The problem arises that the Additionally, multipliers and balanced modulators fundamentally have problems with linearity.

That is, when using a multiplier or balanced modulator as a frequency conversion means, if the DC balance is not set correctly, the resulting converted output signal waveform will be distorted and degraded, resulting in single sideband (
This poses a big problem when used for SSB) communications or frequency inversion of audio signals.

Therefore, there has been a demand for a method that does not require DC balancing.

Furthermore, since the ÷π phase shift circuit 5.6 is generally constructed using multiple resistors and capacitors, the circuit in Figure 2 can be
If you try to use C, the number of pins will increase, making it difficult to make it compact and low cost. In other words, when converting a frequency conversion circuit into a monolithic integrated circuit, the number of capacitors used in filters and phase shifters increases the number of pins of the integrated circuit, so the number of pins must be reduced.

That is, in view of the need for cost reduction, there has been a desire for a frequency conversion method that, in principle, uses fewer capacitors.

[Means to solve the problem]

The frequency conversion circuit of the present invention has a first frequency conversion circuit that performs a phase shift with a phase difference of 1/2π relative to an input signal.
the second phase circuit and the output signals of these phase circuits as n(
n≧2) means for distributing and supplying to the switches; a combining means for combining the outputs of the switches in the hole tube multiple times in the same phase and in opposite phase; and a high-frequency switching component in the output signal of the combining means. A low-frequency r-wave generator that removes m of the local oscillation signal and
It is equipped with a timing pulse generator that inputs a clock signal corresponding to a frequency twice (m≧4) and outputs one type of timing pulse based on the clock signal, and supplies the timing pulse of the hole cylinder to the n-zono switch. The above-mentioned problems can be solved by configuring the low-frequency r-wave generator to output a signal converted to the sum or difference frequency of the input signal frequency and the local oscillation signal frequency by controlling the opening and closing of each switch. The points were resolved.

〔Example〕

A first embodiment of the frequency conversion circuit of the present invention will be described with reference to signal waveform diagrams (timing charts) of FIGS. 1 and 4. FIG. 1 is a block configuration diagram of the frequency conversion circuit 31 of the present invention, in which the phase circuit 8 gives a φ phase to the input signal, and the phase circuit 7 is a phase shifter that gives a (φ102π) phase. . These are constructed by combining phase shift circuits (phase shifters) in multiple stages in order to make the phase difference between the outputs of both phase circuits 8 and 7 a constant π within the audio signal frequency band, for example. 13 is an LPF (low pass filter) for removing high frequency switching components;
14.15 is an inverting amplifier (inverter) with a gain of -1, and 11 is a timing pulse generator, which inputs a clock signal with a repetition rate of four times the carrier signal frequency, and outputs a clock signal with the same frequency as the carrier signal. And H for one cycle of the clock signal (High 1rel)
Four types of timing pulses (71 to T4) are generated. Further, 81 to S4 are switches (switching elements), and these are configured to be closed when the level of the timing pulse supplied to each of them is H.

Now, when the input signal sinωt is supplied from the input terminal 17L1 to the phase circuit 8 and the phase circuit 7, the signals shown in FIG.
) and signals a and d with waveforms as shown in (0). However, here, for convenience, φ=0.

In that case, the phase circuit 8 is not necessary, and the phase circuit 7 has the same function as the π phase circuit N5 in FIG. These output signals a (=Sinωt) and d (=Sin(ωt)) are supplied to switches S, , S, respectively, and are inverted by inverting amplifiers 14 and 15 to produce a signal c (
==-8inωt; Same r:f! 1 (C)) and a signal b (= 5 inches (ω = π); see (8) in the figure), which are supplied to the switch S3 and the switch S2, respectively.

On the other hand, the same [! A clock signal e having a repetition rate of four times the carrier signal frequency as shown in (E) is supplied to the timing pulse generator 11. This timing pulse generator 11 uses timing pulses T1 as shown in FIG.
~T4 is generated and output, and is supplied to the switches 81 to S1, respectively, to control ON/OFF of these. That is,
Since each of the timing pulses T1 to T4 makes each switch 81 to S4 conductive when the level thereof is H, the fourth
1! l (A) to (0) The thickly drawn portions (1') and (0) of each signal waveform shown.

(c), (d), ... pass through each, resulting in the same (
! A signal j as shown in l (J) is synthesized and LPF
(Low frequency waveform unit) 13. In the LPF 13, the high-frequency switching component is removed, and a signal k (see (b) in the same figure) is outputted from the output terminal -.

The composite output signal j shown in FIG. 4 (J) is the composite output signal j shown in FIG.
It corresponds to the addition output signal g of G), and it can be seen that they are similar when compared in terms of waveforms. This means that even if frequency conversion methods are developed, the results obtained will be the same.

Next, regarding the second embodiment of the frequency conversion circuit of the present invention,
This will be explained with reference to the block configuration diagram in FIG. 5 and the signal waveform diagram (timing chart) in FIG. 6. In FIG. 5, the same components as those of the first embodiment 831 shown in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted. Further, each signal line of timing pulses T1 to Tm from the timing pulse generator 11 to each of the switches Sl to S4 is also omitted for convenience. As is clear from comparing FIG. 5 with FIG. 1, in the second embodiment circuit 32, a phase circuit 9 that provides a (φ−−π) phase instead of the phase opening B7
are using. As a result, only one inverting amplifier is required. Note that 22 is an adder, but if a subtracter is used instead of the adder, the inverting amplifier 14 is also unnecessary.

In such a configuration, the input signal si is input from the input terminal in+.
When nωt is supplied to phase circuits 8 and 9, phase circuit 8
, the signal a(=Sin(ω) as shown in Figure 6(^)
φ)) is output to the switches S1 and S3, and the phase circuit 9 outputs a signal b I =si as shown in FIG.
n (ω = 1φ + π) is output to the switch 5QrS&. On the other hand, from the input terminal In2, a clock signal k with a repetition rate of four times the carrier (or local oscillation) frequency as shown in FIG.
1.

Then, timing pulses T1 to Tm as shown in FIGS. 8G to 8J are generated and output, and the switch 8
1 to S4, respectively, to control ON and OFF of these. That is, since each switch 81 to S4 is closed when the level of each timing pulse Tl to T4 is H, the addition (synthesis) output of the switch S I p S 2 is a signal as shown in FIG. C, and switch S'
The combined output of CL S & is the signal d as shown in (0) in the same figure.
becomes. This signal d is inverted by the inverting amplifier 14 and then combined with the signal C by the adder 22, resulting in the result shown in the figure (
The signal e has a waveform as shown in E). This composite output signal e also corresponds to the addition output signal g in FIG. 2 CG),
Comparing the waveforms reveals that they are similar. This is also frequency-converted by the input signal and carrier signal, which means that the obtained results are the same. The high-frequency switching component is removed from this signal e by the LPF 13, resulting in a signal as shown in FIG. 2(F), which is output from the output terminal shaft.

Note that the second embodiment circuit 32 may be configured using a different method of synthesizing the switch outputs.

For example, it can be configured as shown in FIG.
As shown in Figures (C), (D), and (E), LPF1
If you compare the waveform f that passed through 3 with the waveform f shown in Figure 6 (FC diagram), you will see that the frequency is slightly higher, but this is because it has been converted to the frequency of the sum of the input signal and carrier signal. be.

Next, a fourth embodiment of the circuit of the present invention will be described with reference to the block diagram of FIG. 8 and the signal waveform diagram of FIG. 9. In this FIG. 8 as well, the same components as those of each embodiment circuit shown in FIGS. 1, 5, etc. are denoted by the same reference numerals.
A detailed explanation thereof will be omitted. Further, each signal line of timing pulses T, -T4 from the timing pulse generator 11 to each switch 81 -SL is also omitted.

In this fourth example circuit 34, a phase circuit 7 is used in place of the phase circuit 9, as in the first example circuit 31. As a result, the phase relationship between the output signals a and b of each phase circuit 8 and 7 is the relationship shown in FIG. 9 (^) and (B) ((^
) is the same as the phase relationship between are different from those shown in Fig. 6 above, and Fig. 9 (C) to
The waveform shown in FIG. 9E (that is, the same as that of the third embodiment circuit 33) is obtained. Therefore, the signal that has passed through the LPF 13 naturally has the waveform shown in FIG. 9(F).

Next, regarding the fifth embodiment of the frequency conversion circuit of the present invention,
The block configuration diagram in Figure 10 and the signal waveform diagram in Figure 11 (
This will be explained with reference to the timing chart (timing chart). In this fifth embodiment circuit 35, the above-mentioned first to fourth embodiment circuits 3
The greatest feature is that the switching time is halved compared to Nos. 1 to 34, and the switching component of the frequency-converted output signal is reduced to improve the output waveform.

Now, when the input signal sinωt is supplied from the input terminal In+ to the phase circuits 8 and 9, the phase circuits 8 and 9
Signals a and c having waveforms as shown in FIGS. 11(^) and 11(C) are outputted from the circuits. However, here, for convenience, φ=
0 (in that case, the phase circuit 8 is unnecessary, and the phase circuit 7 has the same function as the π phase circuit 5 in FIG. 2).

Each of these output signals a (= sinωt), signal c (
= sin(ωt-4π)) are respectively supplied to the switch SI+33 and added by the adder 23, resulting in Sinωt +5in(cc+t4yr)
=43in(ωt−fx). Since this signal level is twice as high as signals a and c, the level attenuator 25 lowers the transmission level by 1/2 to obtain a signal as shown in FIG. CB. Similarly,
The adder 24 inverts the signal a with the inverting amplifier 16, adds it to the signal C (that is, subtracts it), and obtains 5in(ωt−4yr) −Sinωt=aSin(ω
After obtaining the signal t-1ff), the level attenuator 26 lowers the transmission level by 1/1 to obtain a signal d as shown in FIG. The inverting amplifiers 16 to 19 with a gain of -1 are each connected to a phase circuit 8. Attenuator 251 Phase circuit 9° Attenuator 26
Output signals a, b, c, d (same figure (^) to (D), respectively)
(see (E) in the same figure) by inverting the phase of the signals
After generating (H), it is supplied to switches 85 to S8. Through the above signal processing, eight types of sine wave signals whose phases are shifted by +π can be generated. In addition,
A subtracter may be used instead of the adder 24, and the inverting amplifier 16 may be positioned between the connection point of the subtracter and the phase circuit 8 and the switch S5.

On the other hand, from the input terminal 1n2, a clock signal with a repetition rate of eight times the carrier signal frequency is supplied to the timing pulse generator 12, which outputs timing pulses T1 to T8 as shown in (1) to (P) in the figure, respectively. , are supplied to the switches Sl to S8, respectively, to control ON/OFF of these with the same capacity as in the first embodiment. As a result, the thickly drawn portions of the signal waveforms shown in FIGS. 11 (A) to (H) pass respectively, and as a result, the signal q shown in FIG. 11 (Q) is generated, and the output terminal Output from the shaft. Since the signal q has a fairly precise waveform, it can be used as is, but it is more preferable to remove the high frequency switching component with an LPF.

The phase circuits 7 to 9 used in the above explanation are configured by combining phase shift circuits (phase shifters) in multiple stages, but a specific example of the configuration of such a phase shift circuit is shown in the 12th section.
Shown in Figures (A) and CB). In the figure, 28 is an operational (inverting) amplifier, Q is an NPN transistor, cl and c2 are capacitors, and R1 to R6 are resistors. All of these phase shift circuits include a delay circuit that is a combination of a capacitor and a resistor.

In the above explanation, the frequency of the clock signal is set to be 4 times or 8 times the frequency of the input signal, but the frequency is not limited to this. It is also possible to configure a circuit.

〔effect〕

Since the frequency conversion circuit of the present invention is configured as described above,
It has various features such as:

■Compared to conventional frequency conversion circuits, there are almost no problems with DC balance or linearity.

■If the phase value is set to 0, only one phase circuit is used in the input signal transmission system, and the resistance is reduced.

The number of capacitors etc. used will be reduced.

■It enables frequency conversion with a large dynamic range, low distortion, and high waveform accuracy, which is also advantageous for IC implementation.

■ Not only the audio signal frequency band, but also the H
Application to l-Fi systems is also possible.

■Instead of a phase circuit that gives a (φjūshiπ) phase, (φ−
(Teraπ) Using a phase circuit that provides phase requires only one inverting amplifier, and using a subtracter instead of an adder eliminates the need for an additional inverting amplifier, simplifying the configuration 6 ■ Equally dividing the input signal As the switching time is shortened by increasing the number of switches to be used, the switching component of the frequency-converted output signal becomes smaller, so the output waveform can be improved and a low-pass filter becomes unnecessary.

[Brief explanation of the drawing]

1, 5, 7, 8 and 10 are block diagrams of the first to fifth embodiments of the frequency conversion circuit of the present invention, respectively, and FIG. 2 is a block diagram of a conventional circuit, Figure 3 (A)
- (H) are signal waveform diagrams for explaining the operation of each part of the conventional circuit, No. 4
Figures (A) to (2) and Figures 6 (^) to (2) are signal waveform diagrams for explaining the operation of the first and second embodiments of the circuit of the present invention, respectively.
Timing chart), Figures 9 (A) to (J) and 1st
Figures 1 (A) to (Q) are signal waveform diagrams for explaining the operation of the fourth and fifth embodiments of the circuit of the present invention, respectively, and Figures 12 (^) and (B
) are examples of various configurations of phase shift circuits that constitute phase circuits. 7-9... Phase circuit, 11.12... Timing pulse generator, 13... Low-pass filter, 14-19
...Inverting amplifier, 22-24...Adder, 25゜2
6...Level attenuator, 28...Operation amplifier, 31~
35... Frequency conversion circuit, SI to S8... Switch.

Claims (3)

[Claims] (1) First and second phase circuits that perform a phase shift with a phase difference of 1/2π relative to the input signal, and the output signals of the first and second phase circuits are n(n is a natural number of 2 or more), combining means for combining the outputs of the n switches multiple times in the same phase and in opposite phase; A low-pass filter that removes frequency switching components and a clock signal corresponding to a frequency m times the local oscillation signal (carrier signal) (m is a natural number of 4 or more) are input, and n types of timing are generated based on this input. and a timing pulse generator that outputs pulses, and supplies the n timing pulses to the n switches to control opening and closing of each switch, thereby controlling the input signal frequency and the local frequency from the low-pass filter. 1. A frequency conversion circuit configured to output a signal converted to a frequency that is the sum or difference of an oscillation signal frequency. (2) First and second phase circuits that shift the input signal with a phase difference of 1/2π relative to each other, and the outputs of the first and second phase circuits are connected to two switches, respectively. a supply means for distributing and supplying the signals, two connection means for connecting two output sides of switches connected to mutually different phase circuits, and a synthesis method for combining the outputs of these connection means in opposite phases. means, a low-pass filter for removing high-frequency switching components in the output signal of the synthesis means, and a clock signal corresponding to four times the frequency of the local oscillation signal, and four types of timing based on this input. and a timing pulse generator that outputs pulses, and by supplying the four timing pulses to the four switches in total and controlling the opening and closing of each, the input signal frequency and the local oscillator are output from the low-pass filter. A frequency conversion circuit characterized in that it is configured to output a signal converted to a frequency that is the sum or difference of a signal frequency. (3) Adding and subtracting the outputs of the first and second phase circuits that shift the input signal with a phase difference of 1/2π relative to each other, and the outputs of the first and second phase circuits, respectively. an adder and a subtracter, first and second level attenuators that attenuate the output levels of the adder and the subtracter by predetermined amounts, respectively; outputs of the first and second phase circuits and the adder; first to fourth inverting amplifiers that respectively invert the phase of the output of the subtracter; and a timing pulse generator that inputs a clock signal that is repeated eight times the carrier signal frequency and outputs eight types of timing pulses based on the clock signal. , are controlled ON and OFF by the eight timing pulses, and the output of the first phase circuit, the output of the adder, and the second
first to eighth switches for sequentially and intermittently outputting the output of the phase circuit, the output of the subtracter, or the output signals of the first to fourth inverting amplifiers by 1/2 period, respectively; A frequency conversion circuit comprising: an addition means for adding the output signals of the eighth switch, and configured to generate and output a signal whose frequency is converted with respect to the input signal frequency.