JPH04119011A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04119011A JPH04119011A JP23849390A JP23849390A JPH04119011A JP H04119011 A JPH04119011 A JP H04119011A JP 23849390 A JP23849390 A JP 23849390A JP 23849390 A JP23849390 A JP 23849390A JP H04119011 A JPH04119011 A JP H04119011A
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- Prior art keywords
- output
- current
- current source
- emitter follower
- diodes
- Prior art date
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Abstract
Description
【発明の詳細な説明】
(発明の概要〕
半導体装置特に高速動作化、低消費電力化したエミッタ
ホロア回路に関し、
消費電力の増大を招かずにエミッタホロア出力段の立下
りを速くすることを目的とし、ECL回路本体部と、そ
の出力段の一対のエミッタホロアとを備える半導体装置
において、該−対のエミッタホロアの出力を受け、出力
が立下る側のエミッタホロアの電流源の電流を増加させ
、出力が立上る側のエミッタホロアの電流を減少させる
制御回路を有する構成とする。[Detailed Description of the Invention] (Summary of the Invention) An object of the present invention is to speed up the falling edge of an emitter follower output stage without increasing power consumption in a semiconductor device, particularly an emitter follower circuit with high speed operation and low power consumption. In a semiconductor device comprising an ECL circuit main body and a pair of emitter followers at its output stage, upon receiving the outputs of the pair of emitter followers, the current of the current source of the emitter follower on the side where the output falls is increased, and the output rises. The configuration includes a control circuit that reduces the current of the side emitter follower.
本発明は、半導体装置特に高速動作化、低消費電力化し
たエミッタホロア回路に関する。The present invention relates to a semiconductor device, particularly an emitter follower circuit that operates at high speed and consumes low power.
近年システムの高速化、高集積化の要求に伴って高速で
高集積、低消費電力の半導体回路(LSI)が要求され
ている。2. Description of the Related Art In recent years, as systems have become faster and more highly integrated, there has been a demand for semiconductor circuits (LSIs) that are faster, more integrated, and have lower power consumption.
高速LSIにはECL回路が使用されることが多く、そ
のECL回路の従来例を第4図に示す。ECL circuits are often used in high-speed LSIs, and a conventional example of the ECL circuit is shown in FIG.
T、、T、は差動対を構成するnpn)ランジスタ、R
3−R2はその負荷抵抗、T、とR4は定電流源を構成
するnpn)ランジスタと抵抗である。T, , T are npn) transistors forming a differential pair, R
3-R2 is the load resistance, T, and R4 are the npn) transistor and resistor that constitute the constant current source.
これらがECLの本体部を構成する。T、、T、はnp
nl−ランジスタ、T6とR1,T7とR7は定電流源
を構成するnpnトランジスタと抵抗で、これらT、と
T、とR6,T、とT、とR6はエミッタホロアを構成
する。トランジスタT”4.”T゛。These constitute the main body of the ECL. T, ,T, is np
The nl-transistors, T6 and R1, and T7 and R7 are npn transistors and resistors that constitute a constant current source, and these T, and T, and R6, T, and T, and R6 constitute an emitter follower. Transistor T"4."T゛.
のベースはECL本体部の出力を受け、エミッタホロア
の出力端X、Yが本回路の出力端となる。The base receives the output from the ECL main body, and the output ends X and Y of the emitter follower become the output ends of this circuit.
C,、C,は出力配線につく容量である。C, , C, is the capacitance attached to the output wiring.
差動対トランジスタT、、T、のベースへは差動人力り
、 I)が加わり、D>百ならT1オン、T2オン、
出力Xはし、出力YはHである。逆にDく何ならT、オ
フ、T2オン、出力XはH1出力YはLである。Differential power, I) is added to the base of the differential pair transistors T, , T, and if D > 100, T1 is on, T2 is on,
Output X is high, and output Y is high. Conversely, if D is T, off, T2 is on, output X is H1, output Y is L.
出力XがL−Hに変わるとき配線容量C1が充電される
。正しくは配線容量CIの充電と共に出力XはLからH
へ立上るが、CIの充電は低抵抗であるトランジスタT
4を通して行なわれるので高速である。出力XがH−L
に変わるときは、配線容量C1が放電する。正しくは配
線容量C1の放電と共に出力XはHからLへ立下るが、
この放電は定電流源T&1R5を通して行なわれ、これ
は抵抗が高い(定電流源の出力電流が小さい)ので低速
である。この傾向は配線容量C1が大きい程、定電流源
の電流が小さい程、大きい。これは、出力Yについても
同様である。When the output X changes from L to H, the wiring capacitor C1 is charged. Correctly, the output X changes from L to H as the wiring capacitance CI is charged.
However, CI is charged by the low-resistance transistor T.
4, so it is fast. Output X is H-L
When the voltage changes to , the wiring capacitance C1 is discharged. Correctly, the output X falls from H to L with the discharge of the wiring capacitance C1, but
This discharge occurs through the constant current source T&1R5, which is slow due to its high resistance (the output current of the constant current source is small). This tendency increases as the wiring capacitance C1 increases and as the current of the constant current source decreases. The same applies to the output Y.
従来のECL回路で出力のH−L立下りを速くするには
定電流源の電流(エミッタホロアの電流)を大にすれば
よいが、これは常時流れるものであり、消費電力の増大
を招(。In a conventional ECL circuit, in order to speed up the H-L fall of the output, it is possible to increase the current of the constant current source (emitter follower current), but this constantly flows, leading to an increase in power consumption ( .
本発明はか\る点を改善し、消費電力の増大を招かずに
エミッタホロア出力段の立下りを速くすることを目的と
するものである。The object of the present invention is to improve the above points and to speed up the fall of the emitter-follower output stage without increasing power consumption.
第1図に示すように本発明では、一対の出力段エミッタ
ホロアの出力X、Yを受けて、相手側エミッタホロアの
電流源の電流を制御して、出力立下り時に該電流を大に
する制御回路CCTを設ける。As shown in FIG. 1, in the present invention, a control circuit receives the outputs X and Y of a pair of output stage emitter followers, controls the current of the current source of the emitter follower on the other side, and increases the current when the output falls. A CCT will be provided.
全図を通してそうであるが、他の図と同じ部分には同じ
符号が付しである。出力段エミッタホロアの電流源T6
とR5,T7とR6は、第4図では差動対の電流源T3
とR4と同じ一定電圧■。。As in all figures, parts that are the same as in other figures are given the same reference numerals. Output stage emitter follower current source T6
and R5, T7 and R6 are the current source T3 of the differential pair in FIG.
and the same constant voltage as R4 ■. .
を受けて定電流源を構成するが、第1図では一定電圧■
。、を受けるのは差動対の電流源だけで、エミッタホロ
アの電流源は制御回路CCTの出力を受ける。A constant current source is constructed based on the voltage given by the constant voltage ■
. , only the current sources of the differential pair receive the output of the control circuit CCT.
この回路では出力XがHからLへ立下るとき、出力Yは
LからHへ立上るが、これを利用して制御回路OCTは
トランジスタT、のベース電位を上げ、電流源T b、
Rsの電流を大にする。従って出力Xの立下りは急速
に行なわれる。In this circuit, when the output X falls from H to L, the output Y rises from L to H. Using this, the control circuit OCT raises the base potential of the transistor T, and the current source T b,
Increase the current of Rs. Therefore, the output X falls quickly.
出力YがHからLへ立下るときも同様で、このとき出力
XはLからHへ立上るが、制御回路OCTはこれを利用
してトランジスタT、のベース電位を上げ、電流源T?
、R6の電流を大にする。従って出力Yの立下りは急速
に行なわれる。The same is true when the output Y falls from H to L. At this time, the output X rises from L to H. The control circuit OCT uses this to raise the base potential of the transistor T, and the current source T?
, increase the current in R6. Therefore, the output Y falls rapidly.
出力Xが立下って出力Yが立上るとき、電流源Th、R
sの電流が大になるが、このとき電流源T7R6の電流
は小になる。出力Yが立下って出力Xが立上るときはこ
の逆で、電流源T、、R6の電流が大になって電流源T
i、 、 Rsの電流が小になる。When output X falls and output Y rises, current sources Th and R
Although the current of s becomes large, the current of current source T7R6 becomes small at this time. When the output Y falls and the output
The currents of i, , and Rs become small.
つまり、H側出力の電流源の電流が小、L側出力の電流
源の電流が大である。従って両方の電流源の電流を大に
するのに比べて消費電力が少なくて済む。In other words, the current of the current source with the H side output is small, and the current of the current source with the L side output is large. Therefore, compared to increasing the current of both current sources, the power consumption can be reduced.
〔実施例]
第2図に本発明の実施例を示す。制御回路OCTは本例
ではCCT、とCCT2からなり、CCT1はダイオー
ドDI、D3と抵抗R7の直列回路で構成され、ダイオ
ードD1はエミッタホロアのトランジスタT4とI6の
間に挿入され、ダイオード’ D 3と抵抗R7は直列
になってり、とI6の接続点aと、低電位電源■、との
間に接続され、D3とR1の接続点が相手側エミッタホ
ロアの電流源トランジスタT、のベースに接続される。[Example] FIG. 2 shows an example of the present invention. In this example, the control circuit OCT is composed of CCT and CCT2, CCT1 is composed of a series circuit of diodes DI, D3 and resistor R7, diode D1 is inserted between emitter follower transistors T4 and I6, and diode 'D3 and The resistor R7 is connected in series between the connection point a of I6 and the low potential power supply ■, and the connection point of D3 and R1 is connected to the base of the current source transistor T of the emitter follower on the other side. Ru.
制御回路CCT、も同様構成である。The control circuit CCT also has a similar configuration.
動作を説明すると出力XがH−L、出力Yが1−−Hに
変わると、D z、 D a、 R、lの経路の電流が
大、D、、D3.R,の経路の電流が小になり、トラン
ジスタT、は導通度を上げてこの電流源の電流は大、ト
ランジスタT、は導通度を下げてこの電流源の電流は小
になる。従って出力Xは立下りは急速になり、出力Yの
立上りも促進される。To explain the operation, when the output X changes to HL and the output Y changes to 1--H, the current in the path Dz, Da, R, l becomes large, D,, D3. The current in the path R becomes small, transistor T increases its conductivity and the current of this current source becomes large, and transistor T decreases its conductivity and the current of this current source becomes small. Therefore, the fall of the output X becomes rapid, and the rise of the output Y is also promoted.
これとは逆に出力XがL−H1出力YがH−Lに変わる
と、D2.D、、RBの経路の電流が小、D1D3.R
7の経路の電流が大になり、トランジスタT、が導通度
を上げて出力Yの立下りが急速になり、またトランジス
タT6が導通度を下げて出力Xの立上りを促進する。Conversely, when the output X changes to L-H1 and the output Y changes to HL, D2. D,, the current in the RB path is small, D1D3. R
The current in path 7 becomes large, transistor T increases its conductivity and the fall of the output Y becomes rapid, and transistor T6 decreases its conductivity to promote the rise of the output X.
第3図はダイオードD3.D−を抵抗R9,RIOに代
えたもので、これでも第2図と同様に動作する。Figure 3 shows the diode D3. D- is replaced with resistors R9 and RIO, and the operation is the same as in FIG. 2.
第2図の回路の数値例を挙げると、出力X、 YのLレ
ベルは−1,6■、Hレベルは−1,0■である。つま
り本例では高電位側電源■。。はグランド、低電位側電
源■。は負電位(−5,2V)としている。電流源T6
とR5の電流を11、電流源T7とR7の電流をI2と
して、これらが大きくなったときのタイオードD+、D
zの電圧降rが0.85■、逆に小さくなったときのそ
れが0.8 Vとする。To give an example of the numerical values of the circuit shown in FIG. 2, the L level of the outputs X and Y is -1,6■, and the H level is -1,0■. In other words, in this example, the high potential side power supply ■. . is ground, low potential side power supply■. is set to a negative potential (-5.2V). Current source T6
Let the currents of T7 and R5 be 11, and the currents of current sources T7 and R7 be I2, and when these become large, the diodes D+ and D
Assume that the voltage drop r of z is 0.85V, and conversely, when it becomes smaller, it is 0.8V.
この状態では、出力XがH−Lに変ったとき、ノートa
の電位は−1,6V−0,85V=−2,45’V、/
−)” b (7)電位は−1,0−0,8= −1
,8V ニなる。In this state, when the output X changes to H-L, the note a
The potential of is -1,6V-0,85V=-2,45'V, /
-)" b (7) The potential is -1,0-0,8=-1
, 8V 2.
ダイオードD、、D、の電圧降下も電流が大きくなった
とき0.85 V、電流が小さくなったとき0.8■と
すると、トランジスタT、のベースは−1,8V−0,
85V=−2,65V、トランジスタT7のベースは−
2,45V−0,8V=−3,25Vになる。Assuming that the voltage drop across the diodes D, D, is 0.85 V when the current is large and 0.8 V when the current is small, the base of the transistor T is -1.8 V - 0,
85V=-2,65V, the base of transistor T7 is -
2,45V-0,8V=-3,25V.
こうしてトランジスタT6のベース電位がトランジスタ
T、のベース電位より充分高くなり、電流■1が電流I
2より(Hレベルのときより)大きくなり(例えばI、
=1.4mA、Iz −0,75mA)、配線容量C1
の電荷を急速に引抜く。In this way, the base potential of the transistor T6 becomes sufficiently higher than the base potential of the transistor T, and the current ■1 changes to the current I
2 (than at H level) (for example, I,
=1.4mA, Iz -0,75mA), wiring capacitance C1
The charge is rapidly extracted.
トランジスタT7はトランジスタT6より(Lレベル時
より)電流が少なくなり、出力Yの立上りの促進、消費
電力の節減が図れる。The current of the transistor T7 is smaller than that of the transistor T6 (when at L level), so that the rise of the output Y can be promoted and power consumption can be reduced.
ダイオードD、、D、に流す電流は、これらのダイオー
ドD、、D4をオンさせるだけでよいから微少でよく、
従って消費電流の増大を招くことはない。The current flowing through the diodes D, D, can be very small since it is only necessary to turn on these diodes D, D4.
Therefore, no increase in current consumption occurs.
タイオードD、−D、はレベルシフト用で、これらがあ
ると、トランジスタT、、T7へ所要ベース電位を供給
する抵抗が小さくて済む。またダイオードDI、Dzは
トランジスタTb、I7のベース、コレクタ間に正常な
電圧が加わるようにする。例えば上記のようにノードa
が前記のように−2,45■、ノードbが−1,8■の
ときI6のベースは2、65 Vでコレクタ電位より低
いが、例えばり。The diodes D and -D are for level shifting, and their presence requires only a small resistance to supply the required base potential to the transistors T and T7. Further, the diodes DI and Dz ensure that a normal voltage is applied between the bases and collectors of the transistors Tb and I7. For example, as shown above, node a
As mentioned above, when the voltage is -2,45 and the node b is -1,8, the base of I6 is 2,65 V, which is lower than the collector potential.
D2を除いてT、のベースを出力端Yへ抵抗を介して接
続すると、ノートaは−1,6■、I6のベースは最高
で−1,0■になり、ベースの方がコレクタより高電位
になる恐れがある。この点、ダイオードD I”’ D
4でトランジスタT b 、 T ’rのコレクタ電
位、ベース電位を決める第2図は確実なバイアス点の設
定ができる。If the bases of T, excluding D2, are connected to the output terminal Y via a resistor, note a will be -1,6■, and the base of I6 will be -1,0■ at the highest, and the base will be higher than the collector. There is a risk of potential. At this point, the diode DI"' D
In FIG. 2, where the collector potential and base potential of the transistors T b and T'r are determined in step 4, a bias point can be set reliably.
また第2図のり、とR?、D4とRs、第3図のR9と
R?、RI。とRIlはエミッタホロアの電流の一部に
なっており(従って制御のための、回路動作とは直接関
係ない余分な電流ではない)、出力の立下り時にはその
立下りに寄与する。Also, the glue in Figure 2 and R? , D4 and Rs, R9 and R in Figure 3? , R.I. and RIl are part of the emitter follower current (therefore, they are not extra currents for control that are not directly related to circuit operation), and contribute to the fall of the output when the output falls.
以上説明したよっに本発明は、エミッタホロア電流を実
質上増加させず、かつ出力の立下りを速くすることがで
き、LSIの性能向上に寄与する所が大きい。As described above, the present invention makes it possible to speed up the fall of the output without substantially increasing the emitter follower current, and greatly contributes to improving the performance of LSI.
第1図は本発明の原理図、
第2図及び第3図は本発明の実施例を示す回路図、
第4図は従来例を示す回路図である。
第1図でT、、T2はECL本体部のエミッタ結合され
たトランジスタ、T4とT、とR5,T。
とT、とR6はエミッタホロア、X、Yはその出力、C
CTは制御回路である。
第3図
従来例を示す回路図
第4図FIG. 1 is a principle diagram of the present invention, FIGS. 2 and 3 are circuit diagrams showing embodiments of the present invention, and FIG. 4 is a circuit diagram showing a conventional example. In FIG. 1, T, T2 are emitter-coupled transistors of the ECL body, T4, T, and R5, T. and T, and R6 are emitter followers, X and Y are their outputs, and C
CT is a control circuit. Figure 3: Circuit diagram showing a conventional example Figure 4
Claims (1)
ホロアとを備える半導体装置において、該一対のエミッ
タホロアの出力(X、Y)を受け、出力が立下る側のエ
ミッタホロアの電流源の電流を増加させ、出力が立上る
側のエミッタホロアの電流の電流を減少させる制御回路
(CCT)を有することを特徴とする半導体装置。 2、制御回路は、エミッタホロアのトランジスタとその
電流源との間に挿入されたダイオード(D_1、D_2
)と、 該ダイオードと電流源との接続点(a、b)と低電位側
電源との間に接続されたダイオード(D_3、D_4)
と抵抗(R_7、R_8)との直列回路とからなり、該
ダイオードと抵抗の直列接続点が、相手側エミッタホロ
アの電流源トランジスタ(T_6、T_7)のベースに
接続されたことを特徴とする請求項1記載の半導体装置
。 3、制御回路は、エミッタホロアのトランジスタとその
電流源との間に挿入されたダイオード(D_1、D_2
)と、 該ダイオードと電流源との接続点(a、b)と低電位側
電源との間に接続された第1の抵抗(R_9、R_1_
0)と第2の抵抗(R_7、R_8)との直列回路とか
らなり、 該第1、第2の抵抗の直列接続点が、相手側エミッタホ
ロアトランジスタ(T_6、T_7)のベースに接続さ
れたことを特徴とする請求項1記載の半導体装置。[Claims] 1. In a semiconductor device comprising an ECL circuit main body and a pair of emitter followers at its output stage, the output of the emitter follower on the side where the output falls (X, Y) is received. A semiconductor device comprising a control circuit (CCT) that increases the current of a current source and decreases the current of an emitter follower on the side where the output rises. 2. The control circuit uses diodes (D_1, D_2) inserted between the emitter follower transistor and its current source.
), and diodes (D_3, D_4) connected between the connection point (a, b) between the diode and the current source and the low potential side power supply.
and a resistor (R_7, R_8) in series, and the series connection point of the diode and the resistor is connected to the base of the current source transistor (T_6, T_7) of the emitter follower on the other side. 1. The semiconductor device according to 1. 3. The control circuit uses diodes (D_1, D_2) inserted between the emitter follower transistor and its current source.
), and a first resistor (R_9, R_1_
0) and second resistors (R_7, R_8), and the series connection point of the first and second resistors is connected to the base of the emitter follower transistor (T_6, T_7) on the other side. The semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23849390A JPH04119011A (en) | 1990-09-07 | 1990-09-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23849390A JPH04119011A (en) | 1990-09-07 | 1990-09-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04119011A true JPH04119011A (en) | 1992-04-20 |
Family
ID=17031071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23849390A Pending JPH04119011A (en) | 1990-09-07 | 1990-09-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04119011A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602498A (en) * | 1994-03-15 | 1997-02-11 | Mitsubishi Denki Kabushiki Kaisha | Current switching logic type circuit with small current consumption |
-
1990
- 1990-09-07 JP JP23849390A patent/JPH04119011A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602498A (en) * | 1994-03-15 | 1997-02-11 | Mitsubishi Denki Kabushiki Kaisha | Current switching logic type circuit with small current consumption |
| US5754062A (en) * | 1994-03-15 | 1998-05-19 | Mitsubishi Denki Kabushiki Kaisha | Current switching logic type circuit with small current consumption |
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