JPH04101568A - Signal processing circuit for image sensor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit for an image sensor used in a small facsimile or a handheld image reading device that reads a document without reducing it.

[Conventional technology]

Among image sensors, contact type image sensors can read a document without using a reduction optical system, so the optical path length is short and the device can be made smaller.

Therefore, in recent years, it has been widely used as an image reading device for small facsimile machines, barcode leagues, and the like.

There are various types of image sensors, but the image sensor described below has a large number of photodiodes that photoelectrically convert optical signals from a document, and a large number of blocking diodes that are provided as switching elements corresponding to each photodiode. They are connected in a matrix.

By sequentially and continuously supplying driving pulses to the blocking diodes, image signals converted into electrical signals can be extracted from each photodiode.

The output portion of this photodiode consists of a plurality of signal lines, such as 16 channels and 32 channels, from which image signals are taken out in parallel. However, when considering the case where a circuit that processes signals from a CCD or the like is used as it is in a circuit subsequent to the image sensor, it is more convenient to extract the image output of the image sensor as a serial signal. The same is true when an image sensor is used to read images in a facsimile machine that sends signals over a single telephone line.

Therefore, a circuit for converting a parallel signal into a serial signal using a multiplexer is required at a stage subsequent to the output portion of the photodiode.

FIG. 4 is a block diagram showing an example of the signal processing circuit of such an image sensor, FIG. 5(a) is a waveform diagram of the output signal of the preamplifier at point A of the signal processing circuit shown in FIG. 4, and FIG. (b) is a waveform diagram of the output signal of the sample-and-hold circuit at point B of the signal processing circuit, and FIG. FIG. 5(d) is a waveform diagram of the output signal of the integrating circuit. FIG. 5(d) is a waveform diagram of the serial signal output from the multiplexer at the zero point of the signal processing circuit shown in FIG. In addition, in Fig. 4, in reality, for example, 1
Only a block for one channel out of six channels is shown.

In FIG. 4, an image signal supplied to an input terminal 40 from a photodiode (not shown) is amplified by a preamplifier 42. In FIG. The state of this signal is shown in FIG. 5(a). The peak value of this signal is held by the sample hold circuit 44 for a certain period of time as shown in FIG. 5(b). Within this holding period, the multiplexer 46 switches each channel and sequentially outputs the values held in each sample and hold circuit from the output terminal 48, thereby obtaining a serial image signal as shown in FIG. 5(d). .

Furthermore, an integrating circuit can be used instead of the sample and hold circuit 44. The appearance of the signal at point B when an integrating circuit is used is as shown in FIG. 5(C).

[Problem to be solved by the invention]

It takes a certain amount of time to extract the charge accumulated in the photodiode as an electrical signal. TI in Figure 5(a)
corresponds to this period, and it takes approximately several microseconds. Correspondingly, when using a sample hold circuit, the period T2 until the signal reaches its peak is
Multiplexer 46 cannot be operated. In addition, when using an integrating circuit, the reset period T of the integrating circuit, the period T until the output of the photodiode ends,
cannot operate multiplexer 46.

As a result, the serial signal output from the multiplexer is
As shown in d), there is a period T during which the signal is output (T when an integrating circuit is used) and a period T2 during which the signal is lost.
(T x + T + when using an integrating circuit)
This is an intermittent signal that alternates between As long as the period during which this signal is lost is sufficiently smaller than T2 (T4/(number of channels)), there is no problem even if the multiplexer is operated continuously.

However, in reality, if the signal output frequency is IMHz, T4
÷ (number of channels) is 1 microsecond, whereas the missing period T2 is quite long at 3 to 4 microseconds, and this period depends on the physical characteristics of the image sensor.
It is difficult to make it any shorter.

If the output signal of the multiplexer is a continuous signal rather than intermittent, the subsequent bivalent processing can be easily performed using a well-known analog circuit using a low-pass filter. If the signal is intermittent, the subsequent signal processing becomes complicated. That is, for example, a procedure is required in which a signal is first converted into a digital signal, then taken into a memory, subjected to predetermined processing, and then further converted into an analog signal. Therefore, there are problems in that the configuration and operation of the circuit become complicated, the number of parts increases, and the cost increases.

The present invention has been made based on the above circumstances, and an object of the present invention is to provide a signal processing circuit for an image sensor that can convert the output signal of a multiplexer into a continuous signal.

[Means to solve the problem]

To achieve the above object, the present invention includes a first signal holding means for holding each image signal supplied in parallel from an image sensor for a certain period of time; In a signal processing circuit for an image sensor, the image sensor signal processing circuit includes a switching means for serially outputting signals in a predetermined order, and a second signal holding means for holding the output signal of the first signal holding means for a certain period of time is provided at a stage subsequent to the first signal holding means. The present invention is characterized in that a signal holding means is provided, and the parallel image signals held by the second signal holding means are serially outputted in a predetermined order by the switching means.

[Effect]

The second signal holding means performs the signal holding operation at a certain point in the period during which the output of the first signal holding means is held constant. Once the second signal holding means holds the signal, even if the output of the first signal holding means changes, it does not affect the output of the second signal holding means. The second signal holding means continues to hold the previous signal even during the period when the second signal holding means is holding the next signal. Thereafter, at a certain point in the period during which the output of the first signal holding means is held constant, the second signal holding means performs the holding operation again. Moreover, the signal sampling period of the second signal holding means is extremely short, for example 0, because there is no need to wait for the image sensor to output the signal as in the case of the first signal holding means. It is about .3 to 0.4 microseconds. Therefore, there is virtually no problem even if the switching means performs the switching operation within this period.

As a result, the switching means can perform the switching operation by time-sharing one period of the operation of the second signal holding means by the number of channels, so that no missing portion occurs in the output signal and a continuous serial signal is generated. Obtainable.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a signal processing circuit of an image sensor according to an embodiment of the present invention, FIG. Figure 2 (b) is a waveform diagram of the output signal of the sample and hold circuit in the previous stage at point B of the signal processing circuit, and Figure 2 (C) is the signal when an integrating circuit is used in place of the sample and hold circuit in the previous stage. A waveform diagram of the output signal of the integrating circuit at point B of the processing circuit, Fig. 2(d) is the first
FIG. 2(e) is a waveform diagram of the output signal of the subsequent sample and hold circuit at point 0 of the signal processing circuit shown in the figure, and FIG. 2(e) is a waveform diagram of the serial signal output from the multiplexer at point D of the signal processing circuit.

The image sensor signal processing circuit shown in FIG. 1 includes an input terminal 10, a preamplifier 12, and a sample hold circuit 1.
4.16, a multiplexer 18, and an output terminal 20. In addition, in Fig. 1, in reality, for example, 1
Only a block for one channel out of six channels is shown.

In FIG. 1, image signals from photodiodes connected in a matrix are input to an input terminal 10 as in FIG. 4, and are amplified by a preamplifier 12. This signal is shown in FIG. 2(a).

This amplified signal is sampled by the sample and hold circuit 14 over a period Tt as shown in FIG. 2(b), and thereafter this value is held for a certain period T4.

An integrating circuit may be used instead of the sample and hold circuit 14, and the signal in this case will be as shown in FIG. 2(C). Since the amount of charge extracted from the photodiode corresponds to the area of the signal shown in FIG. 2(a), an integrating circuit can be used if it is desired to obtain a signal corresponding to the amount of charge. The operation up to this point is similar to the circuit shown in FIG.

In the circuit of this embodiment, another sample and hold circuit 16 is provided at the subsequent stage of this sample and hold circuit 14. This sample-and-hold circuit 16 operates at a certain point 1.0 during a period in which the sample-and-hold circuit 14 holds a constant value. The signal holding operation is started at . At this time, the time T6 required for the subsequent sample and hold circuit 16 to output a constant value is extremely short, for example, 0.3
~0.4 microseconds. This is because the period T2 for waiting for the accumulated charge to be taken out from the photodiode unlike the sample and hold circuit 14 in the previous stage is unnecessary, and the output signal of the sample and hold circuit 14 in the previous stage is constant.

The subsequent sample and hold circuit 16 holds this value until the next sampling start time t3. Prior to this, the sample-and-hold circuit 14 at the previous stage is partially reset at time t2, and starts a sample-and-hold operation for the next image signal sent from the photodiode of the image sensor. However, this does not mean that the sample and hold circuit 16 at the subsequent stage
The sample and hold circuit 16 at the subsequent stage continues to hold the value without affecting the signal held by the sample hold circuit 16 at the subsequent stage.

The multiplexer IB electronically switches and outputs the values held by the sample and hold circuits 16 of each channel in a predetermined order. The cycle for performing the switching operation at this time is the period T7 from time t to time t3 in FIG. 2(d).
The period is set in advance so that the period is divided by the number of channels n. Therefore, this period becomes the signal interval for one pixel of the image signal output from the terminal 20 of the multiplexer 18. This time interval is specifically about 1 microsecond.

In reality, the sample-and-hold operation of the sample-and-hold circuit 16 at the subsequent stage also requires a period indicated by T6 in FIG. 2(d) as a sampling period. As mentioned above, this period is approximately 0.3 to 0.4 microseconds, and the signal X first output from the multiplexer 18 does not reach its peak value until after this period has elapsed. However, this period is sufficiently shorter than the 1 microsecond mentioned above (therefore, the waveform of the first output signal This waveform distortion is not a problem.

The signal output from the multiplexer 18 is shown in FIG.
), after the serial signals for n channels are output, the parallel signals for the next n channels are immediately output, and during this time there is no missing portion of the signal as shown in FIG. 5(d).

The serial signal output from the terminal 20 is binarized by a circuit as shown in FIG. 3, for example.

This circuit supplies a serial image signal input to a terminal 22 to a comparator 24, and also supplies a portion of the signal to a low-pass filter 26.

The low frequency signal that has passed through the low pass filter 26 is supplied to the other terminal of the comparator 24. That is, a comparison operation is performed by sequentially changing the threshold value using a low frequency signal passed through the low-pass filter 26, and the signal is divided into two.
Value.

If a serial signal with a missing part as shown in Fig. 5(d) is input to the circuit shown in Fig. 3, the signal after passing through the low-pass filter, that is, the threshold value for binarization, will be large. As a result, a correctly binarized image signal cannot be obtained. Therefore, when binarizing such an intermittent signal, -1 A/D
If the signal is like the one shown in Figure 2(e), which needs to be digitized by a converter, stored in memory, and then subjected to predetermined processing, it can be converted to a third signal without performing such procedures. A high quality binarized image signal can be obtained using a simple binarization circuit as shown in the figure.

Incidentally, in the above embodiment, a case was explained in which a normal sample and hold circuit was used as the signal holding circuit, but the present invention is not limited to this. A circuit may also be used. Furthermore, the signal holding circuits at the front and rear stages may be separate circuits as long as they operate in the same way.

〔Effect of the invention〕

As explained above, according to the present invention, an additional signal holding circuit is provided in the signal processing circuit of a conventional image sensor, thereby eliminating the missing portion of the signal from the serial image signal output from the switching means and continuously Since this signal can be converted into a standard serial signal, this signal can be binarized using a simple binarization circuit, and since the threshold value does not fluctuate, a high-quality image signal can be obtained. A signal processing circuit for an image sensor can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal processing circuit of an image sensor according to an embodiment of the present invention, FIG. 2'(a) is a waveform diagram of the output signal of the preamplifier at point A of the signal processing circuit shown in FIG. Figure 2 (b) is a waveform diagram of the output signal of the sample and hold circuit in the previous stage at point B of the signal processing circuit;
C) is a waveform diagram of the output signal of the integrating circuit at point B of the signal processing circuit when an integrating circuit is used instead of the sample and hold circuit in the previous stage, and FIG. 2(d) is the signal processing circuit shown in FIG. 1. Figure 2(e) is a waveform diagram of the output signal of the subsequent sample and hold circuit at point 0 of the signal processing circuit, and Figure 3 is a waveform diagram of the serial signal output from the multiplexer at point D of the signal processing circuit. 4 is a block diagram of an example of a signal processing circuit of a conventional image sensor. 5th circle (a) is a waveform diagram of the output signal of the preamplifier at point A of the signal processing circuit shown in FIG. Figure 5(b) is a waveform diagram of the output signal of the sample and hold circuit at point B of the signal processing circuit, and Figure 5(C) is the waveform diagram of the output signal of the signal processing circuit at point B of the signal processing circuit when an integrating circuit is used instead of the sample and hold circuit. FIG. 5(d) is a waveform diagram of the serial signal output from the multiplexer at point 0 of the signal processing circuit shown in FIG. 4. 10.22.40...Input terminal, 12.42...Preamplifier, 14.16.44...Sample hold circuit, 18.
46... Multiplexer, 20.48... Output terminal, 24... Comparator,
26...Low pass filter.

Claims (1)

[Scope of Claims] A first signal holding means that holds each image signal supplied in parallel from an image sensor for a certain period of time; and a first signal holding means that holds the parallel image signals held by the first signal holding means in a predetermined order. In a signal processing circuit for an image sensor having a switching means for serially outputting, a second signal holding means for holding the output signal of the first signal holding means for a certain period of time is provided after the first signal holding means. . A signal processing circuit for an image sensor, characterized in that the parallel image signals held by the second signal holding means are configured to be serially output in a predetermined order by the switching means.