JPH04106895A - Manufacture of semiconductor and manufacture of el luminous layer - Google Patents
Manufacture of semiconductor and manufacture of el luminous layerInfo
- Publication number
- JPH04106895A JPH04106895A JP2222519A JP22251990A JPH04106895A JP H04106895 A JPH04106895 A JP H04106895A JP 2222519 A JP2222519 A JP 2222519A JP 22251990 A JP22251990 A JP 22251990A JP H04106895 A JPH04106895 A JP H04106895A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- light emitting
- film layer
- layer
- lower thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000010409 thin film Substances 0.000 claims abstract description 42
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 28
- 238000000151 deposition Methods 0.000 claims description 17
- 239000010408 film Substances 0.000 abstract description 12
- 230000008021 deposition Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 63
- 229910052984 zinc sulfide Inorganic materials 0.000 description 17
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 239000011247 coating layer Substances 0.000 description 6
- 229910052772 Samarium Inorganic materials 0.000 description 5
- 238000005566 electron beam evaporation Methods 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052771 Terbium Inorganic materials 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 2
- 239000005083 Zinc sulfide Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 150000004763 sulfides Chemical class 0.000 description 2
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 2
- 239000005132 Calcium sulfide based phosphorescent agent Substances 0.000 description 1
- 229910052775 Thulium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体の製造方法に関し、特に−層中に２種以
上の異なる部材を配列して薄膜層とする場合、この薄膜
層の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor, and in particular to a method for forming a thin film layer when two or more different members are arranged in a layer to form a thin film layer. It is related to.
（従来の技術）
従来、例えば同一平面上に２種以上の発光部材がモザイ
ク状に形成されるＥＬ（エレクトロルミネッセンス）パ
ネルのように、下部薄膜層上に２種以上の異なる部材を
配列してなる上部薄膜層を形成する半導体が存在する。(Prior Art) Conventionally, two or more different types of members are arranged on a lower thin film layer, such as an EL (electroluminescence) panel in which two or more types of light emitting members are formed in a mosaic shape on the same plane. There is a semiconductor forming the upper thin film layer.
ＥＬパネルは、例えば３種類の硫化亜鉛系発光部材（Ｚ
ｎＳ：Ｔｂ。EL panels are made of, for example, three types of zinc sulfide-based light-emitting materials (Z
nS:Tb.
Ｆ（緑） ＺｎＳ：Ｓｍ、Ｆ（赤） ＺｎＳ：Ｔｍ
、Ｆ（青））をそれぞれドツト状に形成したものを一画
素とし、これを多数配列してカラーデイスプレィとして
使用するものである。上記ＥＬパネルにおいては、前記
３種類の発光部材は全てＺｎＳ系部材で形成されている
ので同一エッチャントでエツチング可能となり、第１の
発光部材（例えばＺｎＳ：Ｔｂ、Ｆ）を着膜及びパター
ニング後、第２の発光部材（例えばＺｎＳ：Ｓｍ、Ｆ）
を着膜してパターニングする際に既にパターニングされ
た第１の発光部材もエツチングされてしまう。従って、
それぞれの発光部材をフォトリソ法によるエツチングに
より順次形成することができなかった。F (green) ZnS:Sm, F (red) ZnS:Tm
, F (blue)) each formed in the shape of a dot is used as one pixel, and a large number of these are arranged and used as a color display. In the above EL panel, all the three types of light-emitting members are made of ZnS-based materials, so they can be etched with the same etchant, and after depositing and patterning the first light-emitting member (for example, ZnS:Tb, F), Second light emitting member (e.g. ZnS:Sm, F)
When depositing and patterning the first light-emitting member, the first light-emitting member that has already been patterned will also be etched. Therefore,
It was not possible to sequentially form each light emitting member by etching using photolithography.
そこてＥＬパネルを形成する場合、第２図に示すような
リフトオフ法により行われていた。Therefore, when forming an EL panel, a lift-off method as shown in FIG. 2 was used.
すなわち、ガラス基板１上に透明電極２を形成し、これ
を覆う絶縁層３及び第１発光部材を着膜し、第１発光部
材上にレジストパターン４を形成した後、エツチングし
て第１発光層５を形成する（第２図（ａ））。That is, a transparent electrode 2 is formed on a glass substrate 1, an insulating layer 3 covering it and a first light emitting member are deposited, a resist pattern 4 is formed on the first light emitting member, and then etched to form a first light emitting member. A layer 5 is formed (FIG. 2(a)).
次に、第２発光部材６′を着膜した後（第２図（ｂ））
、前記レジストパターン４及びレジストパターン４上
の第２発光部材６′を除去して第１発光層５と同一平面
上に第２発光層６を形成する（第２図（Ｃ））。Next, after depositing the second light emitting member 6' (FIG. 2(b))
Then, the resist pattern 4 and the second light emitting member 6' on the resist pattern 4 are removed to form a second light emitting layer 6 on the same plane as the first light emitting layer 5 (FIG. 2(C)).
そして、絶縁層７を着膜し、フォトリソ法により各発光
層５，６に対応するよう個別化された背面電極８を形成
してＥＬパネルが完成する（第２図（ｄ））。以上のよ
うに構成されたＥＬパネルは、透明電極２と背面電極８
間に電圧か印加されることにより、両者に挾まれた発光
層から光が放射される。Then, an insulating layer 7 is deposited, and individual back electrodes 8 are formed by photolithography to correspond to the respective light emitting layers 5 and 6, thereby completing the EL panel (FIG. 2(d)). The EL panel configured as described above includes the transparent electrode 2 and the back electrode 8.
By applying a voltage between them, light is emitted from the light emitting layer sandwiched between them.
（発明が解決しようとする課題）
しかしながら上記方法によると、レジストバタン４を構
成するフォトレジストの耐熱温度を考慮し、例えば発光
部材にＺｎＳ系の部材を用いた場合、レジストパターン
４を残した状態で第２発光部材６′を着膜する際、着膜
温度を最適着膜温度である２００〜２５０℃より低い温
度（１５０℃）で着膜しなければならない。そのため、
輝度の低下及び発光しきい値電圧の上昇等により発光層
の特性が劣化し、発光効率も悪化するという問題点があ
った。(Problem to be Solved by the Invention) However, according to the above method, in consideration of the heat resistance temperature of the photoresist constituting the resist pattern 4, for example, when a ZnS-based member is used as the light emitting member, the resist pattern 4 may be left in the state. When depositing the second light emitting member 6', the film must be deposited at a temperature (150°C) lower than the optimum film deposition temperature of 200 to 250°C. Therefore,
There have been problems in that the characteristics of the light emitting layer deteriorate due to a decrease in brightness and an increase in the light emission threshold voltage, and the light emission efficiency also deteriorates.
また、発光部材にアルカリ土類硫化物系の部材を用いた
場合、５００〜６００’Ｃの温度で着膜しなければなら
ず、レジストパターン４が焼けて剥離が困難となるので
上記リフトオフ法でＥＬパネルを形成することができな
がった。Furthermore, when an alkaline earth sulfide-based material is used as the light-emitting member, the film must be deposited at a temperature of 500 to 600'C, which burns the resist pattern 4 and makes peeling difficult. It became impossible to form an EL panel.
本発明は上記実情に鑑みてなされたもので、下部薄膜層
上に２種以上の異なる部材を配列してなる上部薄膜層を
形成する場合、上部薄膜層を構成する部材をそれぞれ最
適温度で着膜することができる半導体の製造方法及びＥ
Ｌ発光層の製造方法を提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and when an upper thin film layer is formed by arranging two or more different members on a lower thin film layer, the members constituting the upper thin film layer are each heated at an optimum temperature. Method for manufacturing a semiconductor that can be formed into a film and E
An object of the present invention is to provide a method for manufacturing an L-emitting layer.
（課題を解決するための手段）
上記従来例の問題点を解消するため請求項１の半導体の
製造方法は、下部薄膜層上に２種以上の異なる部材を配
列してなる上部薄膜層を形成する方法において、次の工
程を具備することを特徴としている。(Means for Solving the Problems) In order to solve the problems of the conventional example, the method of manufacturing a semiconductor according to claim 1 forms an upper thin film layer formed by arranging two or more different members on a lower thin film layer. The method is characterized by comprising the following steps.
第１工程として、下部薄膜層上に第１の部材を着膜する
。As a first step, a first member is deposited on the lower thin film layer.
第２工程として、着膜された第１の部材をパタニングし
て上部薄膜層の一部を形成する。As a second step, the deposited first member is patterned to form a part of the upper thin film layer.
第３工程として、パターニングされた第１の部材を覆う
ように前記下部薄膜層の全面に被覆部材を形成する。As a third step, a covering member is formed on the entire surface of the lower thin film layer so as to cover the patterned first member.
第４工程として、前記被覆部材をパターニングして前記
下部薄膜層の一部を露出させる。As a fourth step, the covering member is patterned to expose a portion of the lower thin film layer.
第５工程として、前工程で露出した下部薄膜層を覆うよ
うに第２の部材を着膜する。As a fifth step, a second member is deposited to cover the lower thin film layer exposed in the previous step.
第６エ程として、着膜された第２の部材をパタニングし
て上部薄膜層の一部を形成する。As a sixth step, the deposited second member is patterned to form a portion of the upper thin film layer.
第７エ程として、前記被覆部材を除去する。As a seventh step, the covering member is removed.
を具備する半導体の製造方法。A method for manufacturing a semiconductor, comprising:
請求項２のＥＬ発光層の製造方法は、下部薄膜層上に２
種以上の発光部材を配列してなる発光層を形成する方法
において、次の工程を具備することを特徴としている。The method for producing an EL light emitting layer according to claim 2 provides a method for producing an EL light emitting layer, in which two layers are formed on the lower thin film layer.
A method for forming a light-emitting layer formed by arranging more than one type of light-emitting members is characterized by comprising the following steps.
第１工程として、下部薄膜層上に第１の発光部材を着膜
する。As a first step, a first light emitting member is deposited on the lower thin film layer.
第２工程として、着膜された第１の発光部材をパターニ
ングして発光層の一部を形成する。As a second step, the deposited first light emitting member is patterned to form a part of the light emitting layer.
第３工程として、パターニングされた第１の発光部材を
覆うように前記下部薄膜層の全面に耐熱性部材を形成す
る。As a third step, a heat resistant member is formed on the entire surface of the lower thin film layer so as to cover the patterned first light emitting member.
第４工程として、前記耐熱性部材をパターニングして前
記下部薄膜層の一部を露出させる。As a fourth step, the heat-resistant member is patterned to expose a portion of the lower thin film layer.
第５工程として、前工程で露出した下部薄膜層を覆うよ
うに第２の発光部材を着膜する。As a fifth step, a second light emitting member is deposited to cover the lower thin film layer exposed in the previous step.
第６エ程として、着膜された第２の発光部材をパターニ
ングして発光層の一部を形成する。As a sixth step, the deposited second light emitting member is patterned to form a part of the light emitting layer.
第７エ程として、前記耐熱性部材を除去する。As a seventh step, the heat-resistant member is removed.
（作用）
請求項１の発明方法によれば、パターニングされた第１
の部材は被覆部材によって覆われているので、第２の部
材を着膜及びパターニングする際に、前記第１の部材に
影響を与えることを防止することができる。(Operation) According to the invention method of claim 1, the patterned first
Since the member is covered with the covering member, it is possible to prevent the first member from being affected when the second member is deposited and patterned.
請求項２の発明方法によれば、パターニングされた第１
の発光部材は耐熱性部材によって覆われているので、第
２の発光部材を最適温度で着膜することができる。また
、第２の発光部材をパタニングする際に、前記第１の発
光部材に影響を与えることを防止することができる。According to the invention method of claim 2, the patterned first
Since the light-emitting member is covered with a heat-resistant member, the second light-emitting member can be deposited at an optimal temperature. Further, when patterning the second light emitting member, it is possible to prevent the first light emitting member from being affected.
（実施例）
本発明の実施例に係るＥＬカラーパネルの製造方法につ
いて第１図（ａ）乃至（ｇ）を参照しながら説明する。(Example) A method for manufacturing an EL color panel according to an example of the present invention will be described with reference to FIGS. 1(a) to (g).
ガラス基板１１上にＩｎ、 Ｏ，、ＳｎＯ，等をスパッ
タ法、プラズマＣＶＤ法、電子ビーム蒸着法等で着膜し
、共通電極となる帯状の透明電極１２を形成する。続い
て、Ｓ １３ Ｎａ 、Ｙ２０３ 。A film of In, O, SnO, etc. is deposited on a glass substrate 11 by a sputtering method, a plasma CVD method, an electron beam evaporation method, or the like to form a band-shaped transparent electrode 12 that will become a common electrode. Next, S 13 Na and Y203.
Ｓ ｉｏ２．Ｔａ、Ｏ，等をスパッタ法、プラズマＣＶ
Ｄ法、電子ビーム蒸着法等で着膜して絶縁層１３を形成
する。次に、ＺｎＳ：Ｔｂ、Ｆをスパッタ法若しくは電
子ビーム蒸着法等で最適温度（２００〜２５０℃）で着
膜する。更にレジストの塗布、露光、現像を行ってレジ
ストパターン（図示せず）を形成し、前記ＺｎＳ：Ｔｂ
、Ｆを塩酸系のエッチャントでエツチングして所望のパ
ターンの第１発光層１４（緑色）を形成する（第１図（
ａ））。Sio2. Ta, O, etc. are sputtered, plasma CV
The insulating layer 13 is formed by depositing using the D method, electron beam evaporation method, or the like. Next, a film of ZnS:Tb, F is deposited at an optimum temperature (200 to 250° C.) by sputtering, electron beam evaporation, or the like. Further, a resist pattern (not shown) is formed by coating, exposing and developing a resist, and the ZnS:Tb
, F with a hydrochloric acid-based etchant to form the first light emitting layer 14 (green) in a desired pattern (see FIG. 1).
a)).
前記第１発光層１４を覆うようにガラス基板１の全面に
ネガ型感光性ポリイミドで構成された耐熱性有機物を塗
布して露光、現像を行ない、前記第１発光層１４を覆う
とともに以後の工程で第２発光層が形成されるべき位置
の絶縁層１３が露出するようパターニングされた被覆層
１５を形成する（第１図（ｂ））。前記耐熱性有機物（
感光性ポリイミド）は、耐熱温度２５０〜３００℃を有
している。また、本実施例では感光性ポリイミドを使用
することにより、感光性ポリイミド自体を露光、現像し
てパターニングしたが、通常のポリイミドを使用し、そ
の上にレジストを塗布し、該レジストを露光、現像して
パターニングし、前記ポリイミドをエツチングした後、
前記レジストを剥離液で除去してもよい。A heat-resistant organic material made of negative-type photosensitive polyimide is coated on the entire surface of the glass substrate 1 so as to cover the first light-emitting layer 14, and then exposed and developed to cover the first light-emitting layer 14 and perform subsequent steps. Then, a patterned covering layer 15 is formed so that the insulating layer 13 at the position where the second light emitting layer is to be formed is exposed (FIG. 1(b)). The heat-resistant organic substance (
Photosensitive polyimide) has a heat resistance temperature of 250 to 300°C. In addition, in this example, photosensitive polyimide was used, and the photosensitive polyimide itself was exposed and developed for patterning, but ordinary polyimide was used, a resist was applied on it, and the resist was exposed and developed. After patterning and etching the polyimide,
The resist may be removed using a stripping solution.
次に、ＺｎＳ：Ｓｍ、Ｆをスパッタ法若しくは電子ビー
ム蒸着法等で最適温度（２００〜２５０℃）で着膜して
発光層膜１６′を形成する（第１図（Ｃ））。レジスト
の塗布、露光、現像を行ってレジストパターン１７を形
成しく第１図（ｄ））、前記ＺｎＳ：Ｓｍ、Ｆを塩酸系
のエッチャントでエツチングして所望のパターンの第２
発光層１６（赤色）を形成する。この際、第１発光層１
４は被覆層１５で覆われているので、第２発光層１６の
形成時に第１発光層１４をエツチングするのに用いたエ
ッチャントを使用しても、第１発光層１４がエツチング
されるのを防止する。また、被覆層１５の存在により、
第２発光層１６の形成位置を規制することかできる。続
いて、前記レジストパターン１７を剥離液で除去する（
第１図（ｅ））。Next, a light emitting layer film 16' is formed by depositing ZnS:Sm, F at an optimum temperature (200 to 250 DEG C.) by sputtering or electron beam evaporation (FIG. 1C). A resist pattern 17 is formed by coating, exposing, and developing a resist (FIG. 1(d)). The ZnS:Sm, F is etched with a hydrochloric acid-based etchant to form a second pattern of a desired pattern.
A light emitting layer 16 (red) is formed. At this time, the first light emitting layer 1
4 is covered with the coating layer 15, even if the etchant used to etch the first light emitting layer 14 when forming the second light emitting layer 16 is used, the first light emitting layer 14 will not be etched. To prevent. Furthermore, due to the presence of the coating layer 15,
The formation position of the second light emitting layer 16 can be regulated. Subsequently, the resist pattern 17 is removed using a stripping solution (
Figure 1(e)).
次に、被覆層１５をヒドラジン若しくはレジスト剥離液
で除去する（第１図（ｆ））。Next, the coating layer 15 is removed using hydrazine or a resist stripper (FIG. 1(f)).
更に第１図（ｂ）〜第１図（ｆ）の上記プロセスを、発
光部材ＺｎＳ：Ｔｍ、Ｆについて行ない、第３発光層１
８（青色）を形成する。そして、Ｓｉ、Ｎ、、Ｙ、Ｏ，
、Ｓｉｎ、、Ｔａ２Ｏ，等をスパッタ法、プラズマＣＶ
Ｄ法、電子ビーム蒸着法等で着膜して絶縁層１つを形成
する。最後にアルミニウムを着膜及びパターニングし、
各発光層に対応するように分離された背面電極２０を形
成し、同一平面上に３種類の発光部材（ＺｎＳ：Ｔｂ、
Ｆ（緑） ＺｎＳ：Ｓｍ、Ｆ （赤） ＺｎＳ：Ｔ
ｍ、 Ｆ （青））をドツト状に配置したＥＬカラー
パネルか形成される（第１図（ｇ））。Furthermore, the above processes of FIG. 1(b) to FIG. 1(f) are performed on the light emitting member ZnS:Tm,F to form the third light emitting layer 1.
8 (blue) is formed. And Si, N, , Y, O,
, Sin, , Ta2O, etc. by sputtering method, plasma CV
One insulating layer is formed by depositing the film using the D method, electron beam evaporation method, or the like. Finally, aluminum is deposited and patterned,
Separated back electrodes 20 are formed to correspond to each light emitting layer, and three types of light emitting members (ZnS:Tb,
F (green) ZnS:Sm, F (red) ZnS:T
An EL color panel is formed in which dots (m, F (blue)) are arranged in a dot shape (FIG. 1(g)).
発光部材としては上記実施例で使用した他に、ＺｎＳ：
Ｍｎやアルカリ土類硫化物（ＣａＳ：Ｅｕ ＣａＳ：
Ｃｅ ＳｒＳ：Ｅｕ ＳｒＳ：Ｃｅ等）を使用して
もよい。アルカリ土類硫化物の最適着膜温度は５００〜
６００℃と高温度であるか、着膜時間か短時間（数時間
）であれば、実用上前記感光性ポリイミドを被覆層］５
として使用することができる。In addition to the light emitting members used in the above examples, ZnS:
Mn and alkaline earth sulfides (CaS:Eu CaS:
Ce SrS:Eu SrS:Ce, etc.) may be used. The optimum film deposition temperature for alkaline earth sulfides is 500~
If the temperature is as high as 600°C or the film deposition time is short (several hours), it is practical to use the photosensitive polyimide as a coating layer]5
It can be used as
また上記実施例においては、被覆層１５を感光性ポリイ
ミドで形成したか、耐熱性を有し、且つ第１図（ｅ）か
ら第１図（ｆ）の被覆層１５を除去する工程で、第１発
光層１４及び第２発光層１６を劣化させることなく薬液
で除去できる材料、例えばアルミニウム等で構成しても
よい。Further, in the above embodiment, the covering layer 15 is made of photosensitive polyimide or has heat resistance, and in the step of removing the covering layer 15 from FIG. 1(e) to FIG. 1(f), The first light emitting layer 14 and the second light emitting layer 16 may be made of a material that can be removed with a chemical solution without deteriorating, such as aluminum.
上記実施例によれば、ＥＬカラーパネルを作製する際に
、耐熱性部材で形成された被覆層１５を形成及び除去す
る工程を設けることにより、硫化亜鉛系やアルカリ土類
硫化物系薄膜を、各々最適温度で着膜することができる
。According to the above embodiment, when producing an EL color panel, by providing a step of forming and removing the coating layer 15 made of a heat-resistant material, a zinc sulfide-based or alkaline earth sulfide-based thin film can be formed. Films can be deposited at their respective optimum temperatures.
（発明の効果）
請求項１の発明方法によれば、パターニングされた第１
の部材は被覆部材によって覆われているので、第２の部
材を着膜及びパターニングする際に、前記第１の部材に
影響を与えず且つ第１の部材の劣化を防止し、良好な特
性を有する半導体を得ることができる。(Effect of the invention) According to the invention method of claim 1, the patterned first
Since the member is covered with the covering member, when the second member is deposited and patterned, it does not affect the first member, prevents deterioration of the first member, and maintains good characteristics. It is possible to obtain a semiconductor having the following properties.
請求項２の発明方法によれば、パターニングされた第１
の発光部材は耐熱性部材によって覆われているので、第
２の発光部材を最適温度で着膜することができるととも
に、第２の発光部材をパタニングする際に前記第１の発
光部材に影響を与えず且つ第１の部材の劣化を防止し、
良好な特性を有するＥＬ発光層を得ることができる。According to the invention method of claim 2, the patterned first
Since the light-emitting member is covered with a heat-resistant member, the second light-emitting member can be deposited at an optimal temperature, and the second light-emitting member can be patterned without affecting the first light-emitting member. and prevents deterioration of the first member,
An EL light-emitting layer having good characteristics can be obtained.
第１図（ａ）乃至（ｇ）は本発明実施例のＥＬカラーパ
ネルの製造方法を示す工程図、第２図（ａ）乃至（ｄ）
は従来のＥＬパネルの製造方法（リフトオフ法）を示す
工程図である。
５・・・・・・被覆層
６・・・・・・第２発光層
８・・・・・第３発光層
９・・・・・・絶縁層
Ｏ・・・・・背面電極
１１・・・・・・ガラス基板
１２・・・・・透明電極
１３・・・・・・絶縁層
１４・・・・・・第１発光層
第
図
第１
図FIGS. 1(a) to (g) are process diagrams showing a method for manufacturing an EL color panel according to an embodiment of the present invention, and FIGS. 2(a) to (d)
1 is a process diagram showing a conventional EL panel manufacturing method (lift-off method). 5...Coating layer 6...Second light emitting layer 8...Third light emitting layer 9...Insulating layer O...Back electrode 11... ...Glass substrate 12 ...Transparent electrode 13 ...Insulating layer 14 ...First light emitting layer Fig. 1
Claims (2)
なる上部薄膜層を形成する方法において、下部薄膜層上
に第１の部材を着膜する工程と、着膜された第１の部材
をパターニングして上部薄膜層の一部を形成する工程と
、 パターニングされた第１の部材を覆うように前記下部薄
膜層の全面に被覆部材を形成する工程と、該被覆部材を
パターニングして前記下部薄膜層の一部を露出させる工
程と、 前工程で露出した下部薄膜層を覆うように第２の部材を
着膜する工程と、 着膜された第２の部材をパターニングして上部薄膜層の
一部を形成する工程と、 前記被覆部材を除去する工程と、 を具備する半導体の製造方法。(1) A method for forming an upper thin film layer formed by arranging two or more different members on a lower thin film layer, which includes the step of depositing a first member on the lower thin film layer, and the step of depositing a first member on the lower thin film layer; forming a part of the upper thin film layer by patterning the member, forming a covering member on the entire surface of the lower thin film layer so as to cover the patterned first member, and patterning the covering member. exposing a part of the lower thin film layer; depositing a second member so as to cover the lower thin film layer exposed in the previous step; and patterning the deposited second member to form an upper part. A method for manufacturing a semiconductor, comprising: forming a part of a thin film layer; and removing the covering member.
る発光層を形成する方法において、 下部薄膜層上に第１の発光部材を着膜する工程と、 着膜された第１の発光部材をパターニングして発光層の
一部を形成する工程と、 パターニングされた第１の発光部材を覆うように前記下
部薄膜層の全面に耐熱性部材を形成する工程と、 該耐熱性部材をパターニングして前記下部薄膜層の一部
を露出させる工程と、 前工程で露出した下部薄膜層を覆うように第２の発光部
材を着膜する工程と、 着膜された第２の発光部材をパターニングして発光層の
一部を形成する工程と、 前記耐熱性部材を除去する工程と、 を具備するＥＬ発光層の製造方法。(2) A method for forming a light emitting layer formed by arranging two or more types of light emitting members on a lower thin film layer, comprising: depositing a first light emitting member on the lower thin film layer; and depositing a first light emitting member on the lower thin film layer; forming a part of the light emitting layer by patterning the light emitting member; forming a heat resistant member on the entire surface of the lower thin film layer so as to cover the patterned first light emitting member; and the heat resistant member patterning to expose a part of the lower thin film layer; depositing a second light emitting member to cover the lower thin film layer exposed in the previous step; and depositing the second light emitting member. A method for manufacturing an EL light emitting layer, comprising: forming a part of the light emitting layer by patterning the heat resistant member; and removing the heat resistant member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2222519A JPH04106895A (en) | 1990-08-27 | 1990-08-27 | Manufacture of semiconductor and manufacture of el luminous layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2222519A JPH04106895A (en) | 1990-08-27 | 1990-08-27 | Manufacture of semiconductor and manufacture of el luminous layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04106895A true JPH04106895A (en) | 1992-04-08 |
Family
ID=16783703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2222519A Pending JPH04106895A (en) | 1990-08-27 | 1990-08-27 | Manufacture of semiconductor and manufacture of el luminous layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04106895A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7343288B2 (en) | 2002-05-08 | 2008-03-11 | Sap Ag | Method and system for the processing and storing of voice information and corresponding timeline information |
| US7406413B2 (en) | 2002-05-08 | 2008-07-29 | Sap Aktiengesellschaft | Method and system for the processing of voice data and for the recognition of a language |
-
1990
- 1990-08-27 JP JP2222519A patent/JPH04106895A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7343288B2 (en) | 2002-05-08 | 2008-03-11 | Sap Ag | Method and system for the processing and storing of voice information and corresponding timeline information |
| US7406413B2 (en) | 2002-05-08 | 2008-07-29 | Sap Aktiengesellschaft | Method and system for the processing of voice data and for the recognition of a language |
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