JPH0410619Y2 - - Google Patents
Info
- Publication number
- JPH0410619Y2 JPH0410619Y2 JP15749285U JP15749285U JPH0410619Y2 JP H0410619 Y2 JPH0410619 Y2 JP H0410619Y2 JP 15749285 U JP15749285 U JP 15749285U JP 15749285 U JP15749285 U JP 15749285U JP H0410619 Y2 JPH0410619 Y2 JP H0410619Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- film
- anisotropic conductive
- liquid crystal
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920000642 polymer Polymers 0.000 claims description 15
- 239000004973 liquid crystal related substance Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 11
- 239000011521 glass Substances 0.000 description 10
- 238000002161 passivation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
この考案は、液晶表示板に表示用信号を供給す
る集積回路（以下ICと略す）を、液晶表示板上
に実装する構造に関する。[Detailed description of the invention] [Industrial application field] This invention relates to a structure in which an integrated circuit (hereinafter abbreviated as IC) for supplying display signals to a liquid crystal display board is mounted on a liquid crystal display board.
この考案は、液晶表示板のガラス基板上に設置
した金属配線パターン上に、異方性導電膜を介し
てICをフエースダウンで実装する構造において、
ICのバンプ部分を開孔した高分子絶縁フイルム
を、ICのフエース面と、異方性導電膜の間に挿
入することにより、異方性導電膜中の導電物質お
よび接着剤をICのフエース面に接することを防
止し、信頼性を向上させるようにしたものであ
る。
This idea is based on a structure in which an IC is mounted face-down on a metal wiring pattern installed on a glass substrate of a liquid crystal display board via an anisotropic conductive film.
By inserting a polymer insulating film with holes in the bump portion of the IC between the face surface of the IC and the anisotropic conductive film, the conductive substance and adhesive in the anisotropic conductive film are transferred to the face surface of the IC. This is designed to prevent contact with other objects and improve reliability.
従来、液晶表示板の表示用信号ICの実装は、
ガラスエポキシ基板上に設置し、フレキシブル基
板を用いて、液晶表示板へ電気的に接続する方式
が採用されていた。この方法では表示用画素のピ
ツチの微細化に対応しきれなくなりつつある。そ
こで、第２図のごとく、液晶表示板のガラス基板
８上にIC５を設置し、IC５のバンプ２とガラス
基板８上に設置したリード電極７の間に、接着剤
に導電体を分散させた異方性導電膜１を介して、
電気的に導通させ、IC５の外側に枠６を設置し、
モールド剤４をコーテイングする実装方式が進め
られている。
Conventionally, the mounting of display signal ICs on liquid crystal display boards was
A method was adopted in which the device was installed on a glass epoxy substrate and electrically connected to the liquid crystal display panel using a flexible substrate. This method is becoming unable to cope with the miniaturization of the pitch of display pixels. Therefore, as shown in Figure 2, the IC 5 was installed on the glass substrate 8 of the liquid crystal display panel, and a conductor was dispersed in the adhesive between the bump 2 of the IC 5 and the lead electrode 7 installed on the glass substrate 8. Through the anisotropic conductive film 1,
Make it electrically conductive, place a frame 6 outside the IC 5,
A mounting method in which a molding agent 4 is coated is being developed.
しかし従来の方法は、異方性導電膜１に使用さ
れる導電体の大きさが、IC５のバンプ２の凸高
さより小でなければ、IC５を背面より加熱、加
圧し、異方性導電膜１を硬化させる際、IC５の
フエース面とガラス基板８の間の導電体が、IC
５のパツシベーシヨン膜を破壊する現象が生ず
る。また、IC５のパツシベーシヨン膜に直接、
異方性導電膜１の接着剤が接触しているため信頼
性を低下させてしまう。
However, in the conventional method, unless the size of the conductor used for the anisotropic conductive film 1 is smaller than the convex height of the bump 2 of the IC 5, the IC 5 is heated and pressurized from the back side, and the anisotropic conductive film When curing the IC 1, the conductor between the face of the IC 5 and the glass substrate 8
A phenomenon that destroys the passivation film No. 5 occurs. In addition, directly to the passivation membrane of IC5,
Since the adhesive of the anisotropic conductive film 1 is in contact with the adhesive, reliability is reduced.
前記問題点を解決するためIC５のパツシベー
シヨン膜を厚くし、導電体により破壊されないよ
うにすることが考えられるが、ICコストが高く、
かつ使用する材料の制約を受ける。そこで本考案
は、IC５は一般の金バンプを使用し、高分子絶
縁フイルム３をあらかじめバンプ２部分を開孔
し、ガラス基板８上に異方性導電膜１を設置し、
前記高分子絶縁フイルム３を設置した後、IC５
をセツトし、高分子絶縁フイルム３の開孔部の異
方性導電膜１で、バンプ２と電気的に導通させ
た。
In order to solve the above problem, it is possible to thicken the passivation film of IC5 so that it will not be destroyed by the conductor, but the IC cost is high and
Also, there are restrictions on the materials used. Therefore, in the present invention, the IC 5 uses a general gold bump, the polymer insulating film 3 is pre-drilled at the bump 2 part, the anisotropic conductive film 1 is placed on the glass substrate 8,
After installing the polymer insulation film 3, IC5
was set and electrically connected to the bumps 2 through the anisotropic conductive film 1 in the openings of the polymer insulating film 3.
本考案は上記のように構成するため、異方性導
電膜１の導電体により、IC５のパツシベーシヨ
ン膜が破壊されることがなく、一般のバンプIC
が使用できる。また高分子絶縁フイルム３のため
直接IC５のパツシベーシヨン膜に接触しても信
頼性を低下させることがなく、使用する異方性導
電膜１の導電体の大きさのバラツキをあまり気に
することなくできるので異方性導電膜１の自由度
が高くなる。
Since the present invention is constructed as described above, the passivation film of the IC 5 is not destroyed by the conductor of the anisotropic conductive film 1, and is similar to that of a general bump IC.
can be used. In addition, since the polymer insulating film 3 is in direct contact with the passivation film of the IC 5, reliability will not deteriorate, and there is no need to worry too much about variations in the size of the conductor of the anisotropic conductive film 1 used. Therefore, the degree of freedom of the anisotropic conductive film 1 increases.
以下に本考案の実施例を図面にもとづいて説明
する。第１図は本考案の断面を示す略図である。
第１図において、ガラス基板８に異方性導電膜１
を貼り付け、保護フイルムをハクリする。あらか
じめバンプ２部のみ開孔した高分子絶縁フイルム
３を、異方性導電膜１上にセツトし、貼り付け
る。IC５をフエースダウンで、前記高分子絶縁
フイルム３の開孔部とIC５のバンプ２を合わせ
セツトし、IC５の背面より、温度130℃〜170℃、
圧力５Kg／cm2〜50Kg／cm2で、数秒〜十数秒保持
し、異方性導電膜１を硬化させ、リード電極７と
IC５のバンプ２を導電体で電気的に接続した。
動作テスト後、シリコン樹脂でIC５の外周部に
枠６を印刷で形成し、モールド剤４をコーテイン
グして表示用信号ICをガラス基板８上に実装し
た。なお高分子絶縁フイルム３のバンプ部の開孔
はドライフイルムのソルダーレジストやメツキマ
スクフイルムで、フオトレジスト法により容易に
作れる。また別方法として、炭酸ガスレーザー
や、YAGレーザーを用いて、能率良く開孔する
ことが可能で、後者の場合は高分子絶縁フイルム
３の材料の自由度が高い利点を持つ。
Embodiments of the present invention will be described below based on the drawings. FIG. 1 is a schematic cross-sectional view of the present invention.
In FIG. 1, an anisotropic conductive film 1 is placed on a glass substrate 8.
Paste it and peel off the protective film. A polymer insulating film 3, in which holes have been opened only in the bump 2 portions, is set on the anisotropic conductive film 1 and pasted. Place the IC 5 face down, aligning the opening of the polymer insulating film 3 with the bump 2 of the IC 5, and set the IC 5 at a temperature of 130°C to 170°C from the back side of the IC5.
A pressure of 5 Kg/cm 2 to 50 Kg/cm 2 is maintained for several seconds to more than ten seconds to harden the anisotropic conductive film 1 and bond it to the lead electrode 7.
Bump 2 of IC5 was electrically connected with a conductor.
After the operation test, a frame 6 was printed on the outer periphery of the IC 5 using silicone resin, a molding agent 4 was coated, and the display signal IC was mounted on the glass substrate 8. Note that the openings in the bump portions of the polymer insulating film 3 can be easily made using a dry film solder resist or a plating mask film by a photoresist method. As another method, it is possible to efficiently open the holes using a carbon dioxide laser or a YAG laser, and the latter has the advantage of having a high degree of freedom in the material of the polymer insulating film 3.
この考案は以上説明したように、IC５とガラ
ス基板８の間に高分子絶縁フイルム３を設置して
いるので、異方性導電膜１が直接IC５のフエー
ス面に触れないので信頼性もあり、また高分子絶
縁フイルム３によりIC５のパツシベーシヨン膜
が破壊されることがなくなり信頼性を向上させる
ことができる。
As explained above, this device is reliable because the polymer insulating film 3 is placed between the IC 5 and the glass substrate 8, so the anisotropic conductive film 1 does not directly touch the face of the IC 5. Furthermore, the polymer insulating film 3 prevents the passivation film of the IC 5 from being destroyed, thereby improving reliability.
第１図は本考案の断面を示す略図で、第２図は
従来の構造を示す断面を示す略図である。
１……異方性導電膜、２……バンプ、３……高
分子絶縁フイルム、４……モールド剤、５……
IC、６……枠、７……リード電極、８……ガラ
ス基板。
FIG. 1 is a schematic cross-sectional diagram of the present invention, and FIG. 2 is a schematic cross-sectional diagram of a conventional structure. 1... Anisotropic conductive film, 2... Bump, 3... Polymer insulating film, 4... Molding agent, 5...
IC, 6...frame, 7...lead electrode, 8...glass substrate.
Claims (1)
ースダウンで実装する構造において、 液晶表示板の集積回路を設置する部分に接着
剤に導電体物質を分散させた異方性導電膜を設
置し、 前記集積回路の電極部のみ開口した開口部を
有する高分子絶縁フイルムを、前記開口部の位
置に前記集積回路の電極パツトを合わせて、前
記異方性導電膜の上に設置し、 集積回路の電極パツトと液晶表示板を前記導
電体物質を介して電気的に接続する液晶表示板
の集積回路実装構造。 (2) 前記集積回路の電極パツトに、金のバンプを
設置し、バンプの高さが、前記高分子絶縁フイ
ルムの厚さと同等以上である実用新案登録請求
の範囲第(1)項記載の集積回路実装構造。 (3) 前記高分子絶縁フイルムの厚さが10μm以上
ある実用新案登録請求の範囲第(1)項記載の集積
回路実装構造。[Scope of Claim for Utility Model Registration] (1) In a structure in which an integrated circuit is mounted face-down on the lead electrode part of a liquid crystal display board, a conductive material is dispersed in an adhesive in the part of the liquid crystal display board where the integrated circuit is installed. A polymer insulating film having an opening that opens only the electrode part of the integrated circuit is placed, and the electrode part of the integrated circuit is aligned with the opening, and the anisotropic conductive film is placed in the anisotropic conductive film. An integrated circuit mounting structure of a liquid crystal display board, which is installed on a film and electrically connects the electrode parts of the integrated circuit and the liquid crystal display board via the conductive material. (2) The integrated circuit according to claim 1, wherein gold bumps are installed on the electrode pads of the integrated circuit, and the height of the bumps is equal to or greater than the thickness of the polymer insulating film. Circuit mounting structure. (3) The integrated circuit mounting structure according to claim (1), wherein the polymer insulating film has a thickness of 10 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15749285U JPH0410619Y2 (en) | 1985-10-15 | 1985-10-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15749285U JPH0410619Y2 (en) | 1985-10-15 | 1985-10-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6265679U JPS6265679U (en) | 1987-04-23 |
| JPH0410619Y2 true JPH0410619Y2 (en) | 1992-03-16 |
Family
ID=31080089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15749285U Expired JPH0410619Y2 (en) | 1985-10-15 | 1985-10-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410619Y2 (en) |
-
1985
- 1985-10-15 JP JP15749285U patent/JPH0410619Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6265679U (en) | 1987-04-23 |
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