JP7731660B2 - Semiconductor device and method for manufacturing the same - Google Patents

Description

This invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Traditionally, silicon (Si) has been used as a constituent material for power semiconductor devices that control high voltages and large currents. There are several types of power semiconductor devices, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to their intended application.

For example, bipolar transistors and IGBTs have higher current densities and can handle larger currents than MOSFETs, but they cannot switch at high speeds. Specifically, bipolar transistors are limited to switching frequencies of around a few kHz, while IGBTs are limited to switching frequencies of around several tens of kHz. On the other hand, power MOSFETs have lower current densities than bipolar transistors and IGBTs, making it difficult to handle larger currents, but they are capable of high-speed switching operations of up to a few MHz.

However, there is strong market demand for power semiconductor devices that combine high current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, with development currently approaching the material limits. From the perspective of power semiconductor devices, semiconductor materials to replace silicon are being considered, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to create (manufacture) next-generation power semiconductor devices with low on-state voltage, high-speed characteristics, and excellent high-temperature properties.

The reason behind this is that SiC is a very chemically stable material with a wide band gap of 3 eV, allowing it to be used extremely stably as a semiconductor even at high temperatures. Its maximum electric field strength is also more than an order of magnitude greater than that of silicon. Because SiC has the potential to exceed the material limits of silicon, it is expected to see great growth in future applications for power semiconductors, particularly MOSFETs. Its low on-resistance is particularly promising. It is anticipated that vertical SiC-MOSFETs will have even lower on-resistance while maintaining their high breakdown voltage characteristics.

The structure of a conventional silicon carbide semiconductor device will be described using a vertical MOSFET as an example. Fig. 26 is a cross-sectional view showing the structure of a conventional planar silicon carbide semiconductor device. As shown in Fig. 26, vertical MOSFET 150 has n ^- type silicon carbide epitaxial layer 103 deposited on the front surface of n ⁺ type silicon carbide substrate 101, and p ⁺ type base layer 104 selectively provided on the surface of n ^- type silicon carbide epitaxial layer 103. Furthermore, n ⁺ type source region 108 and p ⁺ type contact region 107 are selectively provided in the surface layer of p ⁺ type base layer 104.

An n ^- type JFET (Junction FET) region 114 is provided in a portion of the p ⁺ -type base layer 104 above the ⁿ -type silicon carbide epitaxial layer 103, penetrating the p ⁺ -type base layer 104 in the depth direction and reaching the n -type silicon carbide epitaxial layer 103. A gate electrode 106 is provided on the surfaces of the p ^{+ -type} base layer 104 and the n ⁺ -type source region 108 via a gate insulating film 105. A source electrode 110 is provided on the surfaces of the n -type silicon carbide epitaxial layer 103, the p ⁺ -type contact region 107, and the n ⁺ -type source region 108. A drain electrode (not shown) is provided on the back surface of the n ⁺ -type silicon carbide substrate 101.

In addition, to reduce the electric field strength and energy loss of vertical MOSFETs, planar silicon carbide semiconductor devices using a trench structure (TED (Trench-Etched Double-Diffused) MOSFET) are known (see Patent Documents 1 to 3 below).

Figure 27 is a perspective view showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. Figure 28 is a cross-sectional view taken along A-A' in Figure 27, showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. Figure 29 is a cross-sectional view taken along B-B' in Figure 27, showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. Figure 27 omits the structure from the gate insulating film 105 (described below) to the source electrode 110 (described below).

27 to 29 , in vertical MOSFET 151, n ⁻ type silicon carbide epitaxial layer 103 is deposited on the front surface of n ⁺ type silicon carbide substrate 101, and p ⁺ type base layer 104 is selectively provided on the surface of n ⁻ type silicon carbide epitaxial layer 103. Furthermore, n ⁺ type source region 108, p ⁺ type contact region 107, and n ⁺ type current diffusion layer 112 are selectively provided in the surface layer of p ⁺ type base layer 104.

Furthermore, an n ^- type JFET region 114 is provided in the portion of p ⁺ -type base layer 104 above n -type silicon carbide epitaxial layer 103, penetrating p ⁺ -type base layer 104 in the depth direction and reaching ⁿ -type silicon carbide epitaxial layer 103, and ^p -type electric field relaxation layer 113 is provided on JFET region 114. By covering the entire JFET region 114 with ^p -type electric field relaxation layer 113, it is possible to reduce the electric field of the gate insulating film applied when the device is off.

Further, trenches 111 are selectively provided, each shallower than the n ⁺ -type current diffusion layer 112, with its bottom surface in contact with the p ⁺ -type base layer 104. FIG. 28 is a cross-sectional view of a portion where the trench 111 is not provided, and FIG. 29 is a cross-sectional view of a portion where the trench 111 is provided. A gate electrode 106 is provided on the inner wall of the trench 111, the n ⁺ -type current diffusion layer 112, the p ⁺ -type base layer 104, and the surface of the n ⁺ -type source region 108, with a gate insulating film 105 interposed therebetween, and an interlayer insulating film 109 is provided so as to cover the gate electrode 106. A source electrode 110 is provided on the surfaces of the p ⁺ -type contact region 107 and the n ⁺ -type source region 108. A drain electrode (not shown) is provided on the back surface of the n ⁺ -type silicon carbide substrate 101.

In this structure, the side surfaces of the trench 111 form the channel region, achieving higher channel mobility than the channel region of a planar silicon carbide semiconductor device (see Figure 26). Furthermore, forming the trench 111 increases the channel width, enabling a higher current density to be achieved than in a planar silicon carbide semiconductor device.

Patent No. 6290457 Patent No. 6309656 Patent No. 6336055

However, in a planar silicon carbide semiconductor device using a conventional trench structure, the p ^- type electric field reduction layer 113 for reducing the electric field of the gate insulating film becomes a resistance component, which increases the JFET resistance (resistance of the JFET region 114) and the on-resistance, which is a problem.

Furthermore, the vertical MOSFETs 150 and 151 have a parasitic pn diode composed of an n ⁻ -type silicon carbide epitaxial layer 103 and a p ⁺ -type base layer 104. When a current flows through the parasitic pn diode, holes are injected from the p ⁺ -type base layer 104, and electrons and holes recombine in the n ⁻ -type silicon carbide epitaxial layer 103 or the n ⁺ -type silicon carbide substrate 101. The recombination energy (3 eV) generated at this time, equivalent to the band gap, moves basal plane dislocations, a type of crystal defect present in the silicon carbide substrate, and stacking faults sandwiched between two basal plane dislocations expand. When the stacking faults expand, the stacking faults make it difficult for current to flow, which raises the problem of increasing the on-resistance of the vertical MOSFETs 150 and 151 and the forward voltage of the parasitic pn diode. Furthermore, because the parasitic pn diode is a bipolar device, it also raises the problem of large switching losses (Qrr).

The purpose of this invention is to provide a planar semiconductor device using a trench structure that reduces the gate insulating film electric field, decreases current flow through the parasitic pn diode, and reduces on-resistance in order to resolve the problems associated with the prior art described above, as well as a method for manufacturing the semiconductor device.

In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: a first semiconductor layer of a first conductivity type, which has an impurity concentration lower than that of the semiconductor substrate, is provided on a semiconductor substrate of a first conductivity type; a second semiconductor layer of a second conductivity type is provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate; a first semiconductor region of the first conductivity type is provided from the surface of the second semiconductor layer, penetrating the second semiconductor layer and reaching the first semiconductor layer; a second semiconductor region of the first conductivity type, which has an impurity concentration higher than that of the semiconductor substrate, is selectively provided in the surface layer of the second semiconductor layer on the opposite side of the first semiconductor layer; a third semiconductor region of the first conductivity type, which is spaced apart from the second semiconductor region and in contact with the first semiconductor region, is selectively provided in the surface layer of the second semiconductor layer on the opposite side of the first semiconductor layer; and a trench is provided from the surface of the second semiconductor layer, which is sandwiched between the second semiconductor region and the third semiconductor region and does not reach the first semiconductor layer. A gate insulating film is provided from the first semiconductor region to the second semiconductor region and on the inner wall of the trench. A gate electrode is provided on the gate insulating film. A fourth semiconductor region of a second conductivity type is provided between the third semiconductor region and the gate electrode, contacting the inner wall of the trench. The fourth semiconductor region covers the first semiconductor region. An interlayer insulating film is provided on the gate electrode. The gate electrodes are separated by a region on the first semiconductor region.

Furthermore, in the semiconductor device according to the present invention, the width of the isolated region is wider than the thickness of the interlayer insulating film.

Furthermore, in the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region comprises a lower first semiconductor region that is deeper than the surface of the third semiconductor region facing the semiconductor substrate, and an upper first semiconductor region that is shallower than the surface of the third semiconductor region facing the semiconductor substrate, and the upper first semiconductor region has the same impurity concentration as the third semiconductor region but a higher impurity concentration than the lower first semiconductor region.

Furthermore, in the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region comprises a lower first semiconductor region provided on the first semiconductor layer and an upper first semiconductor region provided on the lower first semiconductor region, the interface between the lower first semiconductor region and the upper first semiconductor region is deeper than the surface of the third semiconductor region facing the semiconductor substrate, and the upper first semiconductor region has the same impurity concentration as the third semiconductor region but a higher impurity concentration than the lower first semiconductor region.

Furthermore, in the semiconductor device according to the present invention, the first semiconductor region has the same impurity concentration as the third semiconductor region.

In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features: First, a first step is performed in which a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on a semiconductor substrate of a first conductivity type. Next, a second step is performed in which a second semiconductor layer of a second conductivity type is formed on the side of the first semiconductor layer opposite the semiconductor substrate, and a first semiconductor region of the first conductivity type is formed from the surface of the second semiconductor layer, penetrating the second semiconductor layer and reaching the first semiconductor layer. Next, a third step is performed in which a second semiconductor region of the first conductivity type having an impurity concentration higher than that of the semiconductor substrate is selectively formed in a surface layer of the second semiconductor layer opposite the first semiconductor layer. Next, a fourth step is performed in which a third semiconductor region of the first conductivity type is selectively formed in a surface layer of the second semiconductor layer opposite the first semiconductor layer, spaced apart from the second semiconductor region and in contact with the first semiconductor region. Next, a fifth step is performed in which a fourth semiconductor region of the second conductivity type is formed in a surface layer of the third semiconductor region opposite the first semiconductor layer. Next, a sixth step is performed in which a trench is formed from the surface of the second semiconductor layer, the trench being sandwiched between the second semiconductor region and the third semiconductor region and not reaching the first semiconductor layer. Next, a seventh step is performed in which a gate insulating film is formed from the first semiconductor region to the second semiconductor region, and a gate insulating film is formed on the inner wall of the trench. Next, an eighth step is performed in which a gate electrode is formed on the gate insulating film. Next, a ninth step is performed in which an interlayer insulating film is formed on the gate electrode. In the fifth step, the fourth semiconductor region is formed between the third semiconductor region and the gate electrode, in contact with the inner wall of the trench, and the fourth semiconductor region covers the first semiconductor region . The eighth step includes a step of removing the gate electrode in a region above the first semiconductor region.

According to the above-mentioned invention, the gate electrode is removed in the region above the JFET region. In this way, by removing the gate electrode above the JFET region where the electric field tends to concentrate, the electric field applied to the gate insulating film can be alleviated. The reduced electric field allows the impurity concentration in the JFET region to be increased, thereby reducing the on-resistance.

The semiconductor device and semiconductor device manufacturing method of the present invention have the advantage of providing a planar semiconductor device using a trench structure that reduces the electric field in the gate insulating film, reduces current flow through the parasitic pn diode, and reduces on-resistance.

1 is a perspective view showing a structure of a silicon carbide semiconductor device according to a first embodiment; 2 is a cross-sectional view taken along line A-A' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to a first embodiment. 2 is a cross-sectional view taken along the line B-B' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. 1 is a top view showing a structure of a gate electrode of a silicon carbide semiconductor device according to a first embodiment; 1A to 1C are cross-sectional views showing a state during manufacture of a silicon carbide semiconductor device according to a first embodiment (part 1). FIG. 2 is a cross-sectional view showing a state during manufacturing of the silicon carbide semiconductor device according to the first embodiment (part 2). 10A to 10C are cross-sectional views showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 3); 4 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 4); FIG. FIG. 5 is a cross-sectional view showing a state during manufacturing of the silicon carbide semiconductor device according to the first embodiment (part 5). FIG. 10 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a second embodiment; FIG. 10 is a cross-sectional view (part 2) showing the structure of a silicon carbide semiconductor device according to the second embodiment; FIG. 11 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a third embodiment; FIG. 11 is a cross-sectional view (part 2) showing the structure of a silicon carbide semiconductor device according to the third embodiment; FIG. 11 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a fourth embodiment (part 1); FIG. 13 is a cross-sectional view (part 2) showing the structure of a silicon carbide semiconductor device according to the fourth embodiment; FIG. 1 is another cross-sectional view (part 1) showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is another cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment (part 2). FIG. 11 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a fifth embodiment (part 1); FIG. 20 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the fifth embodiment (part 2); FIG. 13 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a sixth embodiment (part 1); FIG. 22 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the sixth embodiment (part 2); FIG. 13 is a plan view showing a structure of a silicon carbide semiconductor device according to a sixth embodiment. FIG. 13 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a seventh embodiment (part 1); FIG. 22 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the seventh embodiment (part 2); FIG. 13 is a plan view showing a structure of a silicon carbide semiconductor device according to a seventh embodiment. FIG. 1 is a cross-sectional view showing the structure of a conventional planar silicon carbide semiconductor device. FIG. 1 is a perspective view showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. 27A-27C are cross-sectional views showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. 27A is a cross-sectional view taken along the line B-B' of FIG. 27A showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure.

Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference symbols, and redundant explanations will be omitted. In this specification, in Miller indices, a "-" symbol represents a bar attached to the index immediately following it, and a "-" symbol before an index indicates a negative index. It is recommended that terms such as "same" or "equivalent" be used to include variations within 5%, taking into account variations in manufacturing.

(Embodiment 1)
A semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In a first embodiment, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET 50 as an example. FIG. 1 is a perspective view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view taken along line B-B' in FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. In FIG. 1, the structure from a gate insulating film 5 to a source electrode 10, which will be described below, is omitted.

As shown in Figures 1 to 3, the silicon carbide semiconductor device according to the first embodiment has an n ^- type silicon carbide epitaxial layer (first semiconductor layer of first conductivity type) 3 deposited on a main surface (front surface) of an n ⁺ type silicon carbide substrate (semiconductor substrate of first conductivity type) 1.

The n ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen (N). The n ^- type silicon carbide epitaxial layer 3 is a low-concentration n-type drift layer doped with, for example, nitrogen at an impurity concentration lower than that of the n ⁺ type silicon carbide substrate 1. Hereinafter, the n ⁺ type silicon carbide substrate 1 alone, or the n ⁺ type silicon carbide substrate 1 and the n ^- type silicon carbide epitaxial layer 3 together, will be referred to as a silicon carbide semiconductor base.

In the silicon carbide semiconductor device according to the first embodiment, a drain electrode (not shown) is provided on the surface (back surface of the silicon carbide semiconductor base) opposite to the n ⁻ type silicon carbide epitaxial layer 3 side of the n ⁺ type silicon carbide substrate 1, which serves as the drain region, and a drain electrode pad (not shown) for connection to an external device is also provided.

A MOS (metal-oxide-semiconductor insulated gate) structure (device structure) is formed on the front surface side of the silicon carbide semiconductor substrate. Specifically, a p ⁺ type base layer (second semiconductor layer of a second conductivity type) 4 is selectively provided on the surface layer of the ^n- type silicon carbide epitaxial layer 3 on the side opposite to the n ⁺ type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate). The p ⁺ type base layer 4 is doped with, for example, aluminum (Al).

An n ⁺ -type source region (first conductivity type second semiconductor region) 8 is provided in the surface layer of the p ⁺ -type base layer 4. A p ⁺ -type contact region 7 may also be provided. The n ⁺ -type source region 8 and the p ⁺ -type contact region 7 are in contact with each other. The n ⁺ -type source region 8 is located closer to a JFET region 14 (described below) than the p ⁺ -type contact region 7.

Furthermore, an n ^- type JFET (Junction FET) region (first semiconductor region of first conductivity type) 14 is provided on the surface of a portion of the surface layer of the n-type silicon carbide epitaxial layer 3 opposite the n ⁺ type silicon carbide substrate 1 side where the p ⁺ type base layer 4 is not provided. The n ^- type JFET region 14 penetrates the p ⁺ type base layer 4 from the surface of the p ⁺ type base layer 4 in the depth direction (the direction from a source electrode (first electrode) 10 described later toward the n ⁺ type silicon carbide substrate 1) and reaches the n-type silicon carbide epitaxial layer 3. The JFET region 14 constitutes a drift region together with the n ^- type silicon carbide epitaxial layer 3. An n ⁺ type current diffusion layer (third semiconductor region of first conductivity type) 12 is provided in the surface layer of the p ⁺ type base layer 4, spaced apart from the n ⁺ type source region 8, and in contact with the JFET region 14. The n ⁺ -type current spreading layer 12 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers.

A trench structure is selectively provided on the first main surface side (p ⁺ -type base layer 4 side) of the silicon carbide semiconductor substrate. Specifically, trench 11 is provided from the surface of p ⁺ -type base layer 4 opposite to n ⁺ -type silicon carbide substrate 1 side (first main surface side of the silicon carbide semiconductor substrate) to a depth not reaching n ⁻ -type silicon carbide epitaxial layer 3. Furthermore, trench 11 is preferably provided to a position shallower than the interface between n ⁺ -type current diffusion layer 12 and p ⁺ -type base layer 4. This is because if trench 11 reaches a position deeper than the interface between n ⁺ -type current diffusion layer 12 and p ⁺ -type base layer 4, a channel will not be formed at the bottom of trench 11. FIG. 2 is a cross-sectional view of a portion without a trench structure, and FIG. 3 is a cross-sectional view of a portion with a trench structure.

A gate insulating film 5 is provided along the inner wall of the trench 11, on the bottom and side walls of the trench 11, and a gate electrode 6 is provided inside the gate insulating film 5 within the trench 11. The gate electrode 6 is also provided via the gate insulating film 5 on the surface of a portion of the p ⁺ type base layer 4 that is sandwiched between the n ⁺ type source region 8 and the JFET region 14. The gate electrode 6 may be provided on the surface of the n ⁺ type current diffusion layer 12 via the gate insulating film 5 and a p ^- type field relaxation layer 13, which will be described later. The gate electrode 6 is insulated from the JFET region 14 and the p ⁺ type base layer 4 by the gate insulating film 5.

As shown in FIGS. 2 and 3 , the gate electrode 6 is not provided in the region above the JFET region 14. Therefore, in the cross-sectional view, the gate electrode 6 is divided into two regions. The gate electrode 6 only needs to be provided in the region from the surface where the n ⁺ -type source region 8 and the p ⁺ -type base layer 4 contact to the surface where the n ⁺ -type current diffusion layer 12 contacts the JFET region 14, and may be removed from the entire region above the JFET region 14. In this way, by removing the gate electrode 6 above the JFET region 14 where an electric field is likely to concentrate, the electric field applied to the gate insulating film 5 can be alleviated. Here, the impurity concentration in the JFET region 14 can be increased by the amount of the alleviated electric field, thereby reducing the on-resistance.

Furthermore, the width of the removed isolation region, i.e., the distance w between the gate electrode 6 divided into two regions, is preferably wider than the height h of the interlayer insulating film 9 (w>h). This is because if it is narrower than the height h, the effect of alleviating the electric field will be reduced.

Figure 4 is a top view showing the structure of a gate electrode of a silicon carbide semiconductor device according to the first embodiment. While the gate electrode 6 is divided into two regions in the cross-sectional view, it is preferable that the distributed gate electrodes 6 are connected, for example, in the edge termination region 30, to be at the same potential. While Figure 4 shows gate electrodes 6 within the same cell connected, it is also acceptable for gate electrodes 6 from other cells to be connected. The edge termination region 30 surrounds the active region 40, through which current flows when the device is on, and has the function of alleviating electric field concentration at the edge of the active region 40 and maintaining a predetermined breakdown voltage (withstand voltage).

Furthermore, a p ^- type electric field relaxation layer (fourth semiconductor region of the second conductivity type) 13 is provided between the n ⁺ type current diffusion layer 12 and the gate electrode 6, in contact with the inner wall of the trench 11. The ^p- type electric field relaxation layer 13 may be provided between the JFET region 14 and the gate insulating film 5. The p ^- type electric field relaxation layer 13 prevents the JFET region 14 from contacting the gate electrode 6, and makes it possible to reduce the electrical capacitance between the gate electrode 6 and the n ^- type silicon carbide epitaxial layer 3.

Although Figure 1 shows only one MOS structure, multiple MOS structures may be arranged in parallel.

An interlayer insulating film 9 is provided on the entire front surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 6. The source electrode 10 is in contact with the n ⁺ -type source region 8 and the p ⁺ -type base layer 4 via contact holes opened in the interlayer insulating film 9. When the p ⁺ -type contact region 7 is provided, the source electrode 10 is in contact with the n ⁺ -type source region 8 and the p ⁺ -type contact region 7. The source electrode 10 is electrically insulated from the gate electrode 6 by the interlayer insulating film 9. An electrode pad (not shown) is provided on the source electrode 10.

(Method for manufacturing silicon carbide semiconductor device according to first embodiment)
Next, a method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described. FIGS. 5 to 9 are cross-sectional views showing states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment. First, an n ⁺ -type silicon carbide substrate 1 doped with nitrogen at an impurity concentration of about 2×10 ¹⁹ /cm ³ is prepared. The n ⁺ -type silicon carbide substrate 1 may have a (000-1) plane whose main surface has an off-angle of about 4 degrees in the <11-20> direction. Next, an n ⁻ -type silicon carbide epitaxial layer 3 doped with nitrogen at an impurity concentration of 1.0×10 ¹⁶ /cm ³ and having a thickness of about 10 μm is grown on the (000-1) plane of the n ⁺ -type silicon carbide substrate 1. This results in the structure shown in FIG. 5 .

Next, an oxide film mask for ion implantation is formed by photolithography and etching, and p ⁺ type base layer 4 is selectively formed by ion implantation on the surface layer of ^n- type silicon carbide epitaxial layer 3. The region of ^n- type silicon carbide epitaxial layer 3 sandwiched between p ⁺ type base layers 4 becomes JFET region 14. In this ion implantation, for example, aluminum may be used as the dopant, and the dose may be set so that the impurity concentration of p ⁺ type base layer 4 is ^2.0 × ¹⁰¹⁶ /cm3. At this point, the structure shown in FIG. 6 is obtained.

Next, n ⁺ type source regions 8 are selectively formed in the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation. Next, p ⁺ type contact regions 7 may be selectively formed in the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation. Next, n ⁺ type current diffusion layers 12 are selectively formed in the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation. Next, p- ^type field relaxation layers 13 are selectively formed in the surface layers of the n ⁺ type current diffusion layers 12 and the JFET region 14 by photolithography and ion implantation. This results in the structure shown in FIG. 7.

A heat treatment (annealing) is performed to activate the p ⁺ -type base layer 4, the n ⁺ -type source region 8, the p ⁺ -type contact region 7, the n ⁺ -type current diffusion layer 12, and the p ⁻ -type field relaxation layer 13. The heat treatment temperature and the heat treatment time may be 1620° C. and 10 minutes, respectively.

The order in which the p ⁺ type base layer 4, the n ⁺ type source region 8, the p ⁺ type contact region 7, the n ⁺ type current diffusion layer 12, and the ^p- type electric field buffer layer 13 are formed can be changed in various ways. The ^p- type electric field buffer layer 13 can also be formed by epitaxial growth.

Next, a trench forming mask having a predetermined opening is formed by photolithography on the surface of the p ⁺ type base layer 4. Next, trenches 11 are selectively formed by dry etching from the surface of the p ⁺ type base layer 4 to a position shallower than the interface between the n ⁺ type current diffusion layer 12 and the p ⁺ type base layer 4, but do not reach the n ^- type silicon carbide epitaxial layer 3.

Next, the front surface of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 5 with a thickness of 100 nm. This thermal oxidation may be performed by heat treatment at a temperature of about 1000°C in a mixed atmosphere of oxygen (O ₂ ) and hydrogen (H ₂ ). As a result, each region formed on the surface of the p ⁺ -type base layer 4, the surface of the p ^- -type field reduction layer 13, and the bottom and sidewalls of the trench 11 are covered with the gate insulating film 5. This results in the structure shown in FIG. 8 . FIG. 8 shows a cross-sectional view taken along line B-B' of FIG. 1 in which the trench 11 has been formed. The same applies to the following FIG. 9 .

Next, a polycrystalline silicon layer (polysilicon (poly-Si) layer) doped with, for example, phosphorus (P) or boron (B) is formed on the gate insulating film 5 as the gate electrode 6. Next, the polycrystalline silicon layer is patterned and selectively removed, leaving the polycrystalline silicon layer inside the gate insulating film 5 in the trench 11 and on the portion of the p ⁺ type base layer 4 sandwiched between the n ⁺ type source region 8 and the JFET region 14. At this time, the polycrystalline silicon layer is not left on the JFET region 14. At this point, the structure shown in FIG. 9 is obtained.

Next, for example, phosphosilicate glass (PSG) is deposited as an interlayer insulating film 9 so as to cover the gate insulating film 5. The thickness of the interlayer insulating film 9 may be 1.0 μm. Next, the interlayer insulating film 9 and the gate insulating film 5 are patterned and selectively removed to form contact holes, thereby exposing the n ⁺ -type source region 8 and the p ⁺ -type contact region 7. Next, a heat treatment (reflow) is performed to planarize the interlayer insulating film 9.

Next, the source electrode 10 is formed on the surface of the interlayer insulating film 9. At this time, the source electrode 10 is also embedded in the contact hole, and the n ⁺ -type source region 8 and the p ⁺ -type contact region 7 are brought into contact with the source electrode 10. The thickness of the portion of the source electrode 10 on the interlayer insulating film 9 may be, for example, 5 μm. The source electrode 10 may be formed of, for example, aluminum containing 1 wt % silicon (Al—Si).

Next, a nickel film, for example, is formed as a drain electrode (not shown) on the surface of the n ⁺ -type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate). Then, a heat treatment is performed at a temperature of, for example, 970°C to form an ohmic junction between the n ⁺ -type silicon carbide substrate 1 and the drain electrode. Next, an electrode pad is deposited by, for example, sputtering, over the entire front surface of the silicon carbide semiconductor substrate, covering the source electrode 10 and the interlayer insulating film 9. The thickness of the portion of the electrode pad on the interlayer insulating film may be, for example, 5 μm. The electrode pad may be formed of, for example, aluminum containing 1 wt % silicon (Al—Si). Next, the electrode pad is selectively removed.

Next, a drain electrode pad is formed on the surface of the drain electrode, using, for example, titanium (Ti), nickel (Ni), and gold (Au) in this order. A protective film may then be formed on the surface. This completes the MOSFET 50 shown in Figures 1 to 3.

As explained above, according to the first embodiment, the gate electrode is removed in the region above the JFET region. In this way, by removing the gate electrode above the JFET region where the electric field tends to concentrate, the electric field applied to the gate insulating film can be alleviated. By alleviating the electric field, the impurity concentration in the JFET region can be increased, thereby reducing the on-resistance.

(Embodiment 2)
10 and 11 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 2. Fig. 10 is a cross-sectional view of a portion corresponding to Fig. 2 of embodiment 1, and Fig. 11 is a cross-sectional view of a portion corresponding to Fig. 3 of embodiment 1.

10 and 11 , the lower JFET region 14 a is provided in a region deeper than the surface of the n + type current diffusion layer 12 facing the n ⁺ type silicon carbide substrate 1 (a region closer to the n ⁺ type silicon carbide substrate 1 than that surface), and the upper JFET region 14 b is provided in a region shallower than the surface of the n ⁺ type current diffusion layer 12 facing the ^{n + type} silicon carbide substrate 1 (a region closer to the source electrode 10 than that surface).

Furthermore, the lower JFET region 14a has an impurity concentration similar to that of the n ⁻ type silicon carbide epitaxial layer 3, while the upper JFET region 14b has an impurity concentration higher than that of the n ⁻ type silicon carbide epitaxial layer 3 and similar to that of the n ⁺ type current diffusion layer 12. By providing the upper JFET region 14b with a high impurity concentration in this manner, the JFET resistance can be made lower than that of the first embodiment, and the on-resistance can be further reduced. Furthermore, in the second embodiment, as in the first embodiment, the gate electrode 6 is removed in the region above the JFET region 14. Therefore, the same effects as those of the first embodiment are obtained.

(Method for manufacturing silicon carbide semiconductor device according to second embodiment)
The silicon carbide semiconductor device of embodiment 2 can be manufactured by forming an upper JFET region 14b in the surface layer of the JFET region 14 when selectively forming an n ⁺ type current diffusion layer 12 in the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation in the manufacturing method of the silicon carbide semiconductor device of embodiment 1.

As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, in the second embodiment, an upper JFET region having an impurity concentration similar to that of the n ⁺ type current diffusion layer is provided in a region shallower than the surface of the n ⁺ type current diffusion layer on the n ⁺ type silicon carbide substrate side. This makes it possible to reduce the JFET resistance more than in the first embodiment, and to further reduce the on-resistance.

(Embodiment 3)
12 and 13 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 3. Fig. 12 is a cross-sectional view of a portion corresponding to Fig. 2 of embodiment 1, and Fig. 13 is a cross-sectional view of a portion corresponding to Fig. 3 of embodiment 1.

The silicon carbide semiconductor device according to the third embodiment differs from the silicon carbide semiconductor device according to the second embodiment in that the interface between the lower JFET region 14 a and the upper JFET region 14 b is deeper than the surface of the n ⁺ -type current spreading layer 12 on the side of the n ⁺ -type silicon carbide substrate 1. In other words, the film thickness of the upper JFET region 14 b is thicker than that of the second embodiment.

The impurity concentrations of the lower JFET region 14a and the upper JFET region 14b are the same as in embodiment 2. In this way, by providing an upper JFET region 14b that is thicker than in embodiment 2, the JFET resistance can be lowered compared to embodiment 2, making it possible to further reduce the on-resistance. Also, in embodiment 3, as in embodiment 1, the gate electrode 6 is removed in the region above the JFET region 14. Therefore, the same effects as in embodiment 1 are achieved.

(Method for manufacturing silicon carbide semiconductor device according to third embodiment)
The silicon carbide semiconductor device of embodiment 3 can be manufactured by selectively forming an n ⁺ type current diffusion layer 12 in the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation in the manufacturing method of the silicon carbide semiconductor device of embodiment 1, and then forming an upper JFET region 14b in the surface layer of the JFET region 14 by photolithography and ion implantation.

As explained above, according to the third embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, in the third embodiment, the film thickness of the upper JFET region is thicker than in the second embodiment. This allows the JFET resistance to be lower than in the second embodiment, making it possible to further reduce the on-resistance.

(Fourth embodiment)
14 and 15 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 4. Fig. 14 is a cross-sectional view of a portion corresponding to Fig. 2 of embodiment 1, and Fig. 15 is a cross-sectional view of a portion corresponding to Fig. 3 of embodiment 1.

The silicon carbide semiconductor device according to the fourth embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the JFET region 14 has the same impurity concentration as the n ⁺ -type current diffusion layer 12. The JFET region 14 is replaced with the upper JFET region 14b of the second and third embodiments. Hereinafter, the same impurity concentration means, for example, an impurity concentration including manufacturing variations when formed simultaneously, that is, substantially the same.

By providing a JFET region 14 that is thicker than the upper JFET region 14b in the second and third embodiments and has the same impurity concentration as the n ⁺ type current diffusion layer 12, the JFET resistance can be made lower than in the second and third embodiments, and the on-resistance can be further reduced. Also, in the fourth embodiment, as in the first embodiment, the gate electrode 6 is removed in the region above the JFET region 14. Therefore, the same effect as in the first embodiment is obtained.

(Method for manufacturing silicon carbide semiconductor device according to fourth embodiment)
The silicon carbide semiconductor device of embodiment 4 can be manufactured by selectively forming an n ⁺ type current diffusion layer 12 in the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation in the manufacturing method of the silicon carbide semiconductor device of embodiment 1, and then making the impurity concentration of the JFET region 14 the same as the impurity concentration of the n ⁺ type current diffusion layer 12 by photolithography and ion implantation.

As described above, according to the fourth embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, in the fourth embodiment, the JFET region has the same impurity concentration as the n ⁺ -type current diffusion layer 12, and the JFET region has a thickness greater than that of the upper JFET region in the second and third embodiments. This makes it possible to reduce the JFET resistance more than in the second embodiment, and to further reduce the on-resistance.

In the first to fourth embodiments, the n ⁺ -type current spreading layer 12 and the p ⁻ -type field relaxation layer 13 may have other shapes. Figures 16 and 17 are other cross-sectional views showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figures 16 and 17 show the structure of the n ⁺ -type current spreading layer 12 and the p ⁻ -type field relaxation layer 13 in the JFET region 14 of the first embodiment, but the n ⁺ -type current spreading layer 12 and the p ⁻ -type field relaxation layer 13 may have the same shapes in the JFET region 14 of the second to fourth embodiments.

16, the n ⁺ type current diffusion layer 12 may have a shape in which the width on the ^p- type field relaxation layer 13 side is wide and the width on the n ⁺ type silicon carbide substrate 1 side is narrow. This shape also alleviates electric field concentration, and the region of the n ⁺ type current diffusion layer 12 with a high impurity concentration can be narrowed compared to when the width on the p- type field relaxation layer 13 side and the width on the n ^{+ type} silicon carbide substrate 1 side are approximately the same. This makes it possible to improve the trade-off between on-resistance and the electric field of the gate insulating film, and to reduce the electric field of the gate insulating film with a low on-resistance.

17, the p ^- type electric field buffer layer 13 may be removed in the region where the gate electrode 6 is not provided. Therefore, the distance w' between the p ^- type electric field buffer layers 13 is equal to or narrower than the distance w between the gate electrodes 6 (w'≦w). The p ^- type electric field buffer layer 13 is provided to reduce the electric field of the gate insulating film applied during the off state, and therefore may not be required in the region where the gate electrode 6 is not provided.

Furthermore, by combining Figures 16 and 17, the n ⁺ type current diffusion layer 12 may have a shape that is wider on the ^p- type electric field relaxation layer 13 side and narrower on the n ⁺ type silicon carbide substrate 1 side, and the ^p- type electric field relaxation layer 13 may be removed in the area where the gate electrode 6 is not provided.

Fifth Embodiment
18 and 19 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 5. Fig. 18 is a cross-sectional view of a portion corresponding to Fig. 2 of embodiment 1, and Fig. 19 is a cross-sectional view of a portion corresponding to Fig. 3 of embodiment 1.

The silicon carbide semiconductor device according to the fifth embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the interlayer insulating film 9 has an opening above the JFET region 14, a Schottky metal 15 is disposed in the opening, and an SBD (Schottky Barrier Diode) is built in.

In the region where the gate electrode 6 is isolated, the interlayer insulating film 9 is opened down to the surface of the JFET region 14, and a metal that forms a Schottky contact with SiC, such as Ti (titanium) or Mo (molybdenum), is embedded in the opening, forming a Schottky contact between the source electrode 10 and the JFET region 14.

The SBD has a lower forward voltage Vf than the parasitic pn diode, so it turns on at a lower voltage than the parasitic pn diode. As a result, during commutation, current flows through the SBD, reducing the current flow through the parasitic pn diode. This prevents the on-resistance of the vertical MOSFET from increasing. Furthermore, because the SBD operates in unipolar mode, Qrr is smaller than that of a parasitic pn diode in bipolar operation, reducing switching loss.

Furthermore, it is preferable that the width of the Schottky metal 15 is narrower than the width of the opening in the interlayer insulating film 9, and that the p ^- type electric field relaxation layer 13 protrudes beyond the opening. Since the edge of the JFET region 14 is a location where leakage is likely to occur, the provision of the p ^- type electric field relaxation layer 13 can relax the electric field at the Schottky interface and reduce the leakage current.

(Method for manufacturing silicon carbide semiconductor device according to fifth embodiment)
The silicon carbide semiconductor device according to the fifth embodiment can be manufactured by adding the following process to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. First, the interlayer insulating film 9 is opened up to the surface of the JFET region 14 in the region where the gate electrode 6 is isolated. Note that when forming the p ^- type field reduction layer 13, it is not formed on the opening of the JFET region 14. Next, a metal film made of, for example, Ti or Mo is formed along the surface of the JFET region 14 in the opening. Next, a heat treatment (annealing) is performed in a nitrogen (N ₂ ) atmosphere at a temperature of, for example, 500° C. or less to form a Schottky junction between the metal film and the semiconductor region on the surface of the JFET region 14. Except for this, the silicon carbide semiconductor device can be manufactured in the same manner as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

As explained above, according to the fifth embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, in the fifth embodiment, an opening is made in the interlayer insulating film above the JFET region, and a Schottky metal is placed in the opening to embed the SBD. As a result, during commutation, current flows through the SBD, reducing the current flow through the parasitic pn diode. This prevents the on-resistance of the vertical MOSFET from increasing. Furthermore, because the SBD operates in unipolar mode, Qrr is reduced compared to a parasitic pn diode operating in bipolar mode, allowing for reduced switching loss.

(Embodiment 6)
20 and 21 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 6. Fig. 20 is a cross-sectional view of a portion corresponding to Fig. 2 of embodiment 1, and Fig. 21 is a cross-sectional view of a portion corresponding to Fig. 3 of embodiment 1.

The silicon carbide semiconductor device according to the sixth embodiment differs from the silicon carbide semiconductor device according to the fifth embodiment in that the interlayer insulating film 9 is opened above the JFET region 14, a Schottky trench (second trench) 16 is formed above the JFET region 14, and a Schottky metal 15 is disposed on the bottom and sidewalls of the Schottky trench 16, thereby incorporating an SBD.

A Schottky connection between the source electrode 10 and the JFET region 14 is formed by embedding a metal that forms a Schottky connection with SiC, such as Ti (titanium) or Mo (molybdenum), in the bottom and sidewalls of the Schottky trench 16. In the sixth embodiment, a Schottky connection is formed at the bottom and sidewalls of the Schottky trench 16, so the area of the Schottky connection can be increased compared to the fifth embodiment.

Here, it is preferable that the Schottky trench 16 has a tapered shape in which the width of the opening is wider than the width of the bottom. This is because if the Schottky trench 16 has an inverse tapered shape in which the angle θ between the sidewall and bottom is 90° or more, the electric field will concentrate at the corner between the sidewall and bottom of the Schottky trench 16.

Furthermore, the larger the angle θ, the larger the area of the sidewall, allowing for an increased area for the Schottky junction. On the other hand, the larger the angle θ, the more difficult it becomes to narrow the width of the Schottky trench 16. For this reason, the angle θ between the sidewall and bottom of the Schottky trench 16 is preferably 82° or greater and less than 90°, and more preferably 85° or greater and 88° or less.

Furthermore, the Schottky trench 16 can be formed simultaneously in a self-aligned manner when the trench 11 is formed. Therefore, the Schottky trench 16 has the same depth as the trench 11. Furthermore, it is preferable that both the trench 11 and the Schottky trench 16 are deep, but as they become deeper, an electric field concentrates at the bottom of the trench 11 and the Schottky trench 16. The trench 11 has a p ⁺ -type base layer 4 at its bottom, and the bottom is protected by the p ⁺ -type base layer 4, so that the electric field is less likely to concentrate at the bottom than in the Schottky trench 16. Therefore, the trench 11 may be deeper than the Schottky trench 16.

Figure 22 is a plan view showing the structure of a silicon carbide semiconductor device according to the sixth embodiment. The A-A' cross section in Figure 22 corresponds to the cross section in Figure 20, and the B-B' cross section in Figure 22 corresponds to the cross section in Figure 21. Figure 22 is also a plan view of the CC' cross section in Figures 20 and 21. As shown in Figure 22, trench 11 has a rectangular shape in plan view (when vertical MOSFET 50 is viewed from the source electrode 10 side toward the n ⁺ type silicon carbide substrate 1 side), and Schottky trench 16 has a stripe shape in plan view.

In this case, it is preferable that the width w1 of trench 11 is wider than the width w2 of Schottky trench 16. The wider the width, the deeper the trench tends to be. For this reason, Schottky trench 16 is made narrower and shallower than trench 11.

(Method for manufacturing silicon carbide semiconductor device according to sixth embodiment)
The silicon carbide semiconductor device according to the sixth embodiment can be manufactured by adding the following process to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. First, the interlayer insulating film 9 is opened down to the surface of the p ⁻ type field buffer layer 13 in the region where the gate electrode 6 is isolated. Next, a trench forming mask having a predetermined opening is formed by photolithography on the surfaces of the p ⁺ type base layer 4 and the JFET region 14, using, for example, an oxide film. Next, by dry etching, a trench 11 is selectively formed from the surface of the p ⁺ type base layer 4 to a position shallower than the interface between the n ⁺ type current diffusion layer 12 and the p ⁺ type base layer 4, the trench 11 not reaching the n ⁻ type silicon carbide epitaxial layer 3, and a Schottky trench 16 from the surface of the p ⁻ type field buffer layer 13 to the JFET region 14. Next, a metal film is formed along the sidewalls and bottom of the Schottky trench 16, using, for example, Ti or Mo. Next, a heat treatment (annealing) is performed in a nitrogen (N ₂ ) atmosphere at a temperature of, for example, about 500° C. or less, thereby forming a Schottky junction between the metal film and the semiconductor region on the sidewalls and bottom of Schottky trench 16. Except for this, the manufacturing method can be the same as that for the silicon carbide semiconductor device according to embodiment 1. In this way, Schottky trench 16 can be formed simultaneously with trench 11, and no additional process is required.

As described above, according to the sixth embodiment, the same effects as those of the fifth embodiment can be obtained. Furthermore, in the sixth embodiment, a Schottky trench is provided, and a Schottky metal is disposed on the bottom and sidewalls of the Schottky trench to incorporate an SBD. Therefore, the sixth embodiment can increase the area of the Schottky connection more than the fifth embodiment.

Seventh Embodiment
23 and 24 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to the seventh embodiment. FIG. 23 is a cross-sectional view of a portion corresponding to FIG. 2 of the first embodiment, and FIG. 24 is a cross-sectional view of a portion corresponding to FIG. 3 of the first embodiment. FIG. 25 is a plan view showing the structure of a silicon carbide semiconductor device according to the seventh embodiment. The A-A' cross section of FIG. 25 is the cross section of FIG. 23, and the B-B' cross section of FIG. 25 is the cross section of FIG. 24. FIG. 25 is a plan view of the C-C' cross section of FIGS. 23 and 24.

The silicon carbide semiconductor device according to the seventh embodiment differs from the silicon carbide semiconductor device according to the sixth embodiment in that the Schottky trench 16 is rectangular. Therefore, in the seventh embodiment, by making the Schottky trench 16 finer, the sidewall portion of the Schottky trench 16 can be increased, and the area of the Schottky junction can be increased more than in the sixth embodiment. Making the Schottky trench 16 finer means shortening the length l of the rectangle (see FIG. 25). By shortening it, the sidewall portion in the direction in which the rectangles are arranged (the direction perpendicular to A-A' in FIG. 25) can be increased.

The shape of the Schottky trench 16 can be rectangular with rounded corners or circular. In this case, the concentration of the electric field at the corners of the rectangle can be reduced. Also, circular shapes are easier to create than rectangular shapes.

25, the trenches 11 and the Schottky trenches 16 are preferably staggered. In other words, the trenches 11 and the Schottky trenches 16 are not provided on the same cross section in the direction in which the p ⁺ -type base layer 4 and the JFET region 14 are aligned (the direction parallel to A-A' in FIG. 25). This allows the trenches 11 and the Schottky trenches 16 to be spaced apart, suppressing localized heat generation and facilitating miniaturization.

(Method for manufacturing silicon carbide semiconductor device according to seventh embodiment)
The silicon carbide semiconductor device according to the seventh embodiment can be manufactured by using the method for manufacturing the silicon carbide semiconductor device according to the sixth embodiment, but by forming Schottky trench 16 in a rectangular shape.

As explained above, according to the seventh embodiment, the same effects as those of the sixth embodiment can be obtained. Furthermore, in the seventh embodiment, by making the Schottky trenches finer, the area of the Schottky junction can be increased more than in the sixth embodiment. Furthermore, by staggering the trenches and Schottky trenches, the trenches and Schottky trenches can be separated, which can suppress localized heat generation and further facilitates miniaturization.

While the fifth to seventh embodiments have been described above with reference to the first embodiment shown in FIGS. 1 to 3 , an SBD can also be added to the second to fourth embodiments. That is, the Schottky metal 15 can also be disposed on the surface of the JFET region 14 in the second embodiment, in which the JFET region 14 is composed of the lower JFET region 14 a and the upper JFET region 14 b. The Schottky metal 15 can also be disposed on the surface of the JFET region 14 in the third embodiment, in which the interface between the lower JFET region 14 a and the upper JFET region 14 b is deeper than the surface of the ^{n +} -type current diffusion layer 12 on the ^{n +} -type silicon carbide substrate 1 side. The Schottky metal 15 can also be disposed on the surface of the JFET region 14 in the fourth embodiment, in which the JFET region 14 has the same impurity concentration as the n + -type current diffusion layer 12.

Furthermore, in the fifth to seventh embodiments, the shape of n ⁺ -type current diffusion layer 12 may be the shape shown in Fig. 16. That is, n ⁺ -type current diffusion layer 12 may have a wide width on the p ^-type electric field buffer layer 13 side and a narrow width on the n ⁺ -type silicon carbide substrate 1 side.

The above embodiments have been described using MOSFETs as an example, but they can also be applied to IGBTs in which a p-type region is provided on the back side of the silicon carbide semiconductor substrate. In this case, the resistance of the surface of the silicon carbide semiconductor substrate is reduced by the IE effect (Injection Enhancement Effect), making it possible to create an IGBT with high breakdown voltage.

The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-described embodiments, the dimensions of each component and the impurity concentration, for example, are set in various ways according to the required specifications. Furthermore, while each of the above-described embodiments uses silicon carbide as the wide bandgap semiconductor, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). It can also be applied to semiconductors other than wide bandgap semiconductors, such as silicon (Si) and germanium (Ge). Furthermore, while each of the embodiments describes the first conductivity type as n-type and the second conductivity type as p-type, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

As described above, the silicon carbide semiconductor device and method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and automotive igniters.

1, 101 n ⁺ type silicon carbide substrate 3, 103 n ^- type silicon carbide epitaxial layer 4, 104 p ⁺ type base layer 5, 105 gate insulating film 6, 106 gate electrode 7, 107 p ⁺ type contact region 8, 108 n ⁺ type source region 9, 109 interlayer insulating film 10, 110 source electrode 11, 111 trench 12, 112 n ⁺ type current diffusion layer 13, 113 p ^- type field relaxation layer 14, 114 JFET region 14a lower JFET region 14b upper JFET region 15 Schottky metal 16 Schottky trench 30 edge termination region 40 active region 50, 150, 151 vertical MOSFET

Claims (6)

a semiconductor substrate of a first conductivity type;
a first semiconductor layer of a first conductivity type provided on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate;
a first semiconductor region of a first conductivity type extending from a surface of the second semiconductor layer through the second semiconductor layer to reach the first semiconductor layer;
a second semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the first semiconductor layer and having a higher impurity concentration than the semiconductor substrate;
a third semiconductor region of the first conductivity type selectively provided on a surface layer of the second semiconductor layer opposite to the first semiconductor layer, the third semiconductor region being spaced apart from the second semiconductor region and in contact with the first semiconductor region;
a trench provided from the surface of the second semiconductor layer, sandwiched between the second semiconductor region and the third semiconductor region, and not reaching the first semiconductor layer;
a gate insulating film provided from the first semiconductor region to the second semiconductor region and on an inner wall of the trench;
a gate electrode provided on the gate insulating film;
a fourth semiconductor region of the second conductivity type provided between the third semiconductor region and the gate electrode and in contact with an inner wall of the trench;
an interlayer insulating film provided on the gate electrode;
Equipped with
a fourth semiconductor region covering the first semiconductor region, and a gate electrode separated by a region above the first semiconductor region; 2. The semiconductor device according to claim 1, wherein the width of the isolated region is greater than the thickness of the interlayer insulating film. the first semiconductor region comprises a lower first semiconductor region that is deeper than a surface of the third semiconductor region that faces the semiconductor substrate, and an upper first semiconductor region that is shallower than a surface of the third semiconductor region that faces the semiconductor substrate,
3. The semiconductor device according to claim 1, wherein the upper first semiconductor region has the same impurity concentration as the third semiconductor region and a higher impurity concentration than the lower first semiconductor region. the first semiconductor region includes a lower first semiconductor region provided on the first semiconductor layer and an upper first semiconductor region provided on the lower first semiconductor region,
an interface between the lower first semiconductor region and the upper first semiconductor region is deeper than a surface of the third semiconductor region on the semiconductor substrate side;
3. The semiconductor device according to claim 1, wherein the upper first semiconductor region has the same impurity concentration as the third semiconductor region and a higher impurity concentration than the lower first semiconductor region. The semiconductor device described in claim 1 or 2, characterized in that the first semiconductor region has the same impurity concentration as the third semiconductor region. a first step of forming a first semiconductor layer of a first conductivity type on a semiconductor substrate of a first conductivity type, the first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate;
a second step of forming a second semiconductor layer of a second conductivity type on the opposite side of the first semiconductor layer with respect to the semiconductor substrate, and forming a first semiconductor region of the first conductivity type that penetrates the second semiconductor layer from a surface of the second semiconductor layer and reaches the first semiconductor layer;
a third step of selectively forming a second semiconductor region of the first conductivity type having a higher impurity concentration than the semiconductor substrate in a surface layer of the second semiconductor layer opposite to the first semiconductor layer;
a fourth step of selectively forming a third semiconductor region of the first conductivity type in a surface layer of the second semiconductor layer opposite to the first semiconductor layer, the third semiconductor region being spaced apart from the second semiconductor region and in contact with the first semiconductor region;
a fifth step of forming a fourth semiconductor region of the second conductivity type in a surface layer of the third semiconductor region;
a sixth step of forming a trench from the surface of the second semiconductor layer, the trench being sandwiched between the second semiconductor region and the third semiconductor region and not reaching the first semiconductor layer;
a seventh step of forming a gate insulating film from the first semiconductor region to the second semiconductor region and forming the gate insulating film on an inner wall of the trench;
an eighth step of forming a gate electrode on the gate insulating film;
a ninth step of forming an interlayer insulating film on the gate electrode;
Including,
In the fifth step, the fourth semiconductor region is formed between the third semiconductor region and the gate electrode, in contact with an inner wall of the trench, and the fourth semiconductor region covers the first semiconductor region;
a step of removing the gate electrode from a region above the first semiconductor region;