JP7731485B2 - Power Conversion Device - Google Patents

Description

This disclosure relates to a power conversion device.

In recent years, modular multilevel converters (MMCs) have become known as high-voltage, large-capacity power conversion devices for use in high-voltage systems such as power grids. MMCs are composed of arms in which converter cells are cascaded. Each converter cell includes multiple semiconductor switches and capacitors, and turning the semiconductor switches on and off outputs either the voltage across the capacitor or zero voltage. Power conversion devices are also known that, if an abnormality occurs in a converter cell, short-circuit the converter cell using a bypass element, allowing continued operation.

For example, the power conversion device disclosed in Japanese Patent No. 5889498 (Patent Document 1) is configured such that, when an abnormality in a converter cell is detected, a semiconductor element selected from among multiple semiconductor elements is turned on so as to continuously form a current path that does not include a bypass element for the period until a closed circuit of the bypass element is established.

Patent No. 5889498

Patent Document 1 considers preventing damage to the bypass element by suppressing the overcurrent that flows through the bypass element when the bypass element closes when an abnormality occurs in the converter cell. The converter cell described in Patent Document 1 is configured as a half-bridge circuit or a full-bridge circuit.

On the other hand, in a converter cell having a configuration in which two half-bridge circuits are connected in series, the voltage applied to the entire converter cell can be divided by the two half-bridge circuits, thereby reducing the voltage applied to each half-bridge circuit. Even in a converter cell having this configuration, it is necessary to protect the bypass elements from damage by suppressing overcurrent flowing through them. However, Patent Document 1 does not teach or suggest a solution for achieving this protection.

An object of one aspect of the present disclosure is to provide a power conversion device that can protect a bypass element by suppressing overcurrent flowing through the bypass element when an abnormality occurs in a converter cell composed of two half-bridge circuits connected in series.

According to one embodiment, a power conversion device is provided that includes a plurality of converter cells connected in series. Each of the plurality of converter cells includes a cell control unit, a first switching circuit and a second switching circuit connected in series, a first input/output terminal and a second input/output terminal, and a bypass element connected between the first input/output terminal and the second input/output terminal. The first switching circuit includes a first semiconductor element, a second semiconductor element, and a first energy storage element connected in parallel to a series circuit including the first semiconductor element and the second semiconductor element. The first input/output terminal is connected to a connection point between the negative terminal of the first semiconductor element and the positive terminal of the second semiconductor element. The second switching circuit includes a third semiconductor element, a fourth semiconductor element, and a second energy storage element connected in parallel to the series circuit including the third semiconductor element and the fourth semiconductor element. The second input/output terminal is connected to a connection point between the negative terminal of the third semiconductor element and the positive terminal of the fourth semiconductor element. If an abnormality is detected in either the first switching circuit or the second switching circuit, the cell control unit executes control to close the bypass element, and in response to the control, executes control to turn each of the first semiconductor element and the fourth semiconductor element into an off state, and executes control to turn each of the second semiconductor element and the third semiconductor element into an on state, during the period before the bypass element is closed.

According to another embodiment, a power conversion device is provided that includes a plurality of converter cells connected in series. Each of the plurality of converter cells includes a cell control unit, a first switching circuit and a second switching circuit connected in series, a first input/output terminal and a second input/output terminal, and a bypass element connected between the first input/output terminal and the second input/output terminal. The first switching circuit includes a first semiconductor element, a second semiconductor element, and a first energy storage element connected in parallel to a series circuit including the first semiconductor element and the second semiconductor element. The first input/output terminal is connected to a connection point between the negative terminal of the first semiconductor element and the positive terminal of the second semiconductor element. The second switching circuit includes a third semiconductor element, a fourth semiconductor element, and a second energy storage element connected in parallel to the series circuit including the third semiconductor element and the fourth semiconductor element. The second input/output terminal is connected to a connection point between the negative terminal of the third semiconductor element and the positive terminal of the fourth semiconductor element. If a short-circuit current flowing through the first semiconductor element or the fourth semiconductor element is detected, the cell control unit controls the first semiconductor element and the fourth semiconductor element to the off state.

According to the present disclosure, when an abnormality occurs in a converter cell composed of two half-bridge circuits connected in series, it is possible to protect the bypass element by suppressing the overcurrent flowing through the bypass element.

FIG. 1 is a schematic configuration diagram of a power conversion device. FIG. 2 is a diagram illustrating a configuration example of a converter cell. FIG. 10 is a diagram showing an example of a path of a short-circuit current that can occur when a bypass element is closed. FIG. 10 is a diagram showing another example of a path of a short-circuit current that can occur when the bypass element is closed. 10 is a diagram illustrating an example of a path of a short-circuit current when on/off control is executed. FIG. 10 shows a current path for bypassing a converter cell. FIG. 10 is a diagram illustrating another example of a path of a short-circuit current when on/off control is executed. 10 is a flowchart showing an example of a processing procedure of a cell control unit according to the first embodiment. FIG. 10 is a diagram for explaining an example of a method for detecting a short-circuit current. FIG. 10 is a diagram for explaining another example of a method for detecting a short-circuit current. FIG. 10 is a diagram for explaining yet another example of a method for detecting a short-circuit current. 10 is a flowchart showing an example of a processing procedure of a cell control unit according to the second embodiment. 1A and 1B are diagrams for explaining an example in which a semiconductor element is destroyed on a large scale; FIG. 11 is a diagram for explaining a control method of a semiconductor element according to a third embodiment. FIG. 10 is a diagram for explaining a semiconductor element group according to a fourth embodiment. FIG. 13 is a diagram for explaining a control method for a semiconductor element group according to a fourth embodiment. FIG. 10 is a diagram showing a modified example of a converter cell. FIG. 2 is a diagram illustrating an example of the configuration of a cell control unit. FIG. 10 is a diagram for explaining another example configuration of the cell control unit.

The present embodiment will now be described with reference to the drawings. In the following description, identical components are designated by the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions of them will not be repeated.

Embodiment 1.
<Configuration of power conversion device>
Fig. 1 is a schematic diagram of a power conversion device. Referring to Fig. 1, the power conversion device 100 includes a power converter 110 including a plurality of converter cells 10 connected in series with each other, and a control device 120 for controlling the power converter 110. A "converter cell" is also called a "sub-module" or "unit converter." The power converter 110 is configured by a modular multilevel converter. Typically, the power converter 110 performs power conversion between a DC circuit 130 and an AC circuit 150.

The power converter 110 includes multiple leg circuits 40u, 40v, and 40w (hereinafter collectively referred to as "leg circuits 40") connected in parallel between a positive DC terminal (i.e., a high-potential side DC terminal) Np and a negative DC terminal (i.e., a low-potential side DC terminal) Nn.

A leg circuit 40 is provided for each of the multiple phases that make up the AC. The leg circuit 40 is connected between the DC circuit 130 and the AC circuit 150, and performs power conversion between the two circuits. Figure 1 shows a case where the AC circuit 150 is a three-phase AC system, with three leg circuits 40u, 40v, and 40w provided corresponding to the U phase, V phase, and W phase, respectively. AC terminals Nu, Nv, and Nw provided in the leg circuits 40u, 40v, and 40w, respectively, are connected to the AC circuit 150 via a transformer 140. The AC circuit 150 is, for example, an AC power system including an AC power source, etc.

The positive DC terminal Np and negative DC terminal Nn, which are commonly connected to each leg circuit 40, are connected to the DC circuit 130. The DC circuit 130 is, for example, the DC terminals of a DC power system including a DC transmission network or other power conversion device.

Leg circuit 40u includes a positive arm from the positive DC terminal Np to the AC terminal Nu, and a negative arm from the negative DC terminal Nn to the AC terminal Nu. The AC terminal Nu, which is the connection point between the positive arm and the negative arm, is connected to the transformer 140. Leg circuits 40v and 40w have a similar configuration.

The positive arm includes a plurality of cascaded converter cells 10 and a reactor 14P. The plurality of converter cells 10 and the reactor 14P are connected in series with each other. The negative arm includes a plurality of cascaded converter cells 10 and a reactor 14N. The plurality of converter cells 10 and the reactor 14N are connected in series with each other.

Reactor 14P may be inserted at any position on the positive arm, and reactor 14N may be inserted at any position on the negative arm. There may be multiple reactors 14P and 14N. Reactor 14P and reactor 14N may be magnetically coupled to form a single reactor. Only reactor 14P or only reactor 14N may be provided. Note that instead of providing a reactor, a configuration may be used in which parasitic inductance such as wiring inductance serves as a substitute for the reactor.

The control device 120 controls the power converter 110 based on detection signals detected by various electrical quantity detectors (not shown) (e.g., an AC voltage detector, an AC current detector, a DC voltage detector, an arm current detector, etc.). The control device 120 may be configured as a dedicated circuit, or part or all of it may be configured as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), a microprocessor, etc.

<Configuration of converter cell>
2 is a diagram showing an example of the configuration of a converter cell 10. Referring to Fig. 2, the converter cell 10 includes a cell control unit 15, a switching circuit 21 and a switching circuit 22 connected in series, a bypass element 25, a high-potential side input/output terminal Po, and a low-potential side input/output terminal No.

Switching circuits 21 and 22 are configured as half-bridge circuits. Specifically, switching circuit 21 includes semiconductor elements 31 and 32, and a capacitor EP as an energy storage element.

The semiconductor element 31 includes a switching element 31s and a diode 31d. The diode 31d is connected in anti-parallel (i.e., parallel and reverse biased) with the switching element 31s. The semiconductor element 32 includes a switching element 32s and a diode 32d. The diode 32d is connected in anti-parallel with the switching element 32s. Note that the switching element 31s may be configured to include the diode 31d.

The switching circuit 22 includes a semiconductor element 33, a semiconductor element 34, and a capacitor EN as an energy storage element. The semiconductor element 33 includes a switching element 33s and a diode 33d. The diode 33d is connected in anti-parallel to the switching element 33s. The semiconductor element 34 includes a switching element 34s and a diode 34d. The diode 34d is connected in anti-parallel to the switching element 34s.

Switching elements 31s, 32s, 33s, and 34s are composed of switching elements such as IGBTs (Insulated Gate Bipolar Transistors), GCTs (Gate Commutated Turn-off Thyristors), and MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors).

Capacitor EP is connected in parallel to a series circuit including semiconductor element 31 and semiconductor element 32, and holds a DC voltage. An input/output terminal Po is connected to the connection point between the negative terminal of semiconductor element 31 and the positive terminal of semiconductor element 32. The positive terminal of capacitor EP is connected to the positive terminal of semiconductor element 31, and the negative terminal of capacitor EP is connected to the negative terminal of semiconductor element 32.

Capacitor EN is connected in parallel to a series circuit including semiconductor element 33 and semiconductor element 34. Input/output terminal No is connected to the connection point between the negative terminal of semiconductor element 33 and the positive terminal of semiconductor element 34. The positive terminal of capacitor EN is connected to the positive terminal of semiconductor element 33, and the negative terminal of capacitor EN is connected to the negative terminal of semiconductor element 34.

The bypass element 25 is connected between the input/output terminal Po and the input/output terminal No. When the bypass element 25 is closed (i.e., turned on), the converter cell 10 is bypassed. For example, the bypass element 25 is used to bypass the converter cell 10 when an element of the converter cell 10 (e.g., semiconductor elements 31-34, etc.) fails. As a result, even if any one of the multiple converter cells 10 fails, the power converter 110 can continue to operate by using the other converter cells 10.

The cell control unit 15 controls the operation of the switching circuits 21 and 22. During steady-state operation (e.g., power conversion operation when no abnormalities occur in the switching circuits 21 and 22), the cell control unit 15 controls the switching elements 31s to 34s to the on or off state, outputting zero voltage or a positive voltage between the input/output terminals Po and No. The operation of the cell control unit 15 when an abnormality occurs in the switching circuits 21 and 22 will be described later. The cell control unit 15 is configured, for example, by an ASIC, an FPGA, or a combination of these.

In the converter cell 10 shown in Figure 2, the two switching circuits 21, 22 are connected in series, which reduces the voltage applied to each of the switching circuits 21, 22. Therefore, this type of converter cell 10 configuration is particularly useful when the voltage applied to the converter cell 10 becomes high due to the miniaturization and high density of MMCs.

<Operation when switching circuit is abnormal>
If an abnormality (e.g., a failure of a semiconductor element, an abnormality in the control power supply used in the gate drive unit of the semiconductor element, etc.) is detected in any of the converter cells 10, the bypass element 25 of the converter cell 10 in which the abnormality is detected is closed, and the converter cell 10 is bypassed.

If the number of converter cells 10 is designed to be redundant so that operation equivalent to steady-state operation is performed, even if one of the converter cells 10 becomes abnormal, the power converter 110 can continue to perform power conversion operation by bypassing the abnormal converter cell 10. However, the following problems can occur.

Figure 3 shows an example of a short-circuit current path that can occur when the bypass element is closed. Referring to Figure 3, let's consider a case where semiconductor element 31, which constitutes the upper arm of switching circuit 21, is short-circuited. In this case, an abnormality (i.e., a short-circuit fault) in semiconductor element 31 is detected, and bypass element 25 is closed. However, this causes the energy charge stored in capacitor EP to be discharged, and a short-circuit current (i.e., an overcurrent) flows along path R1, which runs from capacitor EP through semiconductor element 31, bypass element 25, and semiconductor element 33.

Figure 4 shows another example of a short-circuit current path that can occur when the bypass element is closed. Referring to Figure 4, consider a case where semiconductor element 34, which constitutes the lower arm of switching circuit 22, is short-circuited. In this case, an abnormality (i.e., a short-circuit fault) in semiconductor element 34 is detected, and bypass element 25 is closed. However, this causes the energy charge stored in capacitor EN to be discharged, and a short-circuit current flows through path R2, which runs from capacitor EN through semiconductor element 32, bypass element 25, and semiconductor element 34.

The bypass element 25 is designed based on the current value that flows through the converter cell 10 during normal power conversion operation, and this current value is usually no more than a few kA. However, the short-circuit current shown in Figures 3 and 4 is several tens to several hundred kA, and this short-circuit current could damage the bypass element 25. If the bypass element 25 is damaged, the power conversion device 100 will be unable to continue power conversion operation.

Therefore, when the cell control unit 15 according to this embodiment detects an abnormality in either the switching circuit 21 or the switching circuit 22, it executes control to close the bypass element 25 (hereinafter also referred to as "closing control"), executes control to turn off each of the semiconductor element 31 (specifically, switching element 31s) and the semiconductor element 34 (specifically, switching element 34s), and executes control to turn on each of the semiconductor element 32 (specifically, switching element 32s) and the semiconductor element 33 (specifically, switching element 33s). The reasons for executing the above-mentioned on/off control are explained below.

(When an abnormality occurs in the semiconductor element 31)
Assume that the cell control unit 15 detects an abnormality related to a short-circuit fault in the semiconductor element 31 (hereinafter also referred to as a "short-circuit-related abnormality"). An example of a short-circuit-related abnormality is an abnormality in the control power supply. The control power supply is a power supply supplied to a gate driver for turning the semiconductor element on and off, a power supply supplied to a control board that determines the on/off logic, etc. Typically, the gate driver and the control board are included in the cell control unit 15. The cell control unit 15 detects the voltage of the control power supply and determines whether the voltage is within the normal operating range. If the voltage is outside the normal operating range, the cell control unit 15 detects a short-circuit-related abnormality in the semiconductor element 31. The same method of detecting abnormalities in the other semiconductor elements 32 to 34 applies.

In this case, the cell control unit 15 executes closing control of the bypass element 25, and executes the above-described on/off control in the period before the bypass element 25 is closed in response to the closing control (i.e., before the bypass element 25 is completely closed). Specifically, the cell control unit 15 outputs a control signal (hereinafter also referred to as an "off signal") to semiconductor elements 31 and 34 to turn them off, and outputs a control signal (hereinafter also referred to as an "on signal") to semiconductor elements 32 and 33 to turn them on. As a result, semiconductor elements 32 and 33 are turned on, and semiconductor element 34 is turned off. However, since semiconductor element 31 is in a short-circuited state, it does not turn off. As a result, a short-circuit current path such as that shown in Figure 5 is formed.

Figure 5 shows an example of a short-circuit current path when on/off control is being executed. Referring to Figure 5, before bypass element 25 is closed, semiconductor element 32 is turned on, placing semiconductor elements 31 and 32 in a conductive state, causing a short-circuit current to flow through path R3 between capacitor EP, semiconductor element 31, and semiconductor element 32. This consumes the energy stored in capacitor EP (i.e., the charge is discharged), so that by the time bypass element 25 is actually closed, the energy stored in capacitor EP has been fully consumed. Therefore, the short-circuit current flowing through path R1 in Figure 3 after bypass element 25 is closed is suppressed, preventing damage to bypass element 25.

Here, we will explain the output timing of the close signal to the bypass element 25 and the on/off signals to the semiconductor elements 31-34. Because the bypass element 25 is typically composed of a mechanical switch, the time from when the close signal is given to the bypass element 25 until the bypass element 25 actually closes is about a few ms. On the other hand, the time from when the on/off signal is given to the semiconductor element until the semiconductor element actually turns on or off is about a few μs.

Therefore, even if the cell control unit 15 simultaneously outputs a close signal to the bypass element 25 and an on/off signal to the semiconductor elements 31-34, the on/off states of the semiconductor elements 31-34 are established before the bypass element 25 is closed, forming the current path R3 shown in Figure 5. Note that when using a bypass element 25 other than the mechanical switch described above, it is also possible to use one that closes several tens of microseconds or more after the close signal is applied. Note that the output timing of the on/off signal to the semiconductor elements 31-34 may precede the output timing of the close signal to the bypass element 25.

Here, we will explain why semiconductor element 34 is turned off when a short-circuit-related abnormality occurs in semiconductor element 31. As described above, when semiconductor elements 31 and 32 are conductive, the charge in capacitor EP is discharged via path R3, and when bypass element 25 is closed, current flows via path R1. If semiconductor element 34 were to be turned on in this state, current would flow via path R2 in Figure 4. In this case, charge would be discharged from capacitor EN, which has sufficient stored energy, so the current flowing via path R2 would become an overcurrent, potentially damaging bypass element 25. Therefore, semiconductor element 34 is turned off to prevent discharge from capacitor EN.

In addition, a current path must be formed to bypass the converter cell 10 between the time when the semiconductor element 31 short-circuits and the time when the bypass element 25 is actually closed.

Figure 6 shows the current path for bypassing the converter cell 10. Referring to Figure 6, by controlling the semiconductor elements 32 and 33 to the on state, current can be passed through path R4. This bypasses the converter cell 10. Therefore, the semiconductor element 33 must be turned on.

As described above, in the event of a short-circuit related abnormality in semiconductor element 31, semiconductor element 32 is turned on to allow current to flow through path R3 (see Figure 5) and consume the energy of capacitor EP, semiconductor element 34 is turned off to prevent overcurrent from capacitor EN from flowing to bypass element 25 through path R2 (see Figure 4), and semiconductor element 33 is turned on to allow current to flow through path R4 (see Figure 6) and bypass converter cell 10.

(When an abnormality occurs in the semiconductor element 34)
Assume that the cell control unit 15 detects a short-circuit-related abnormality in the semiconductor element 34. In this case, the cell control unit 15 also outputs a close signal to the bypass element 25, outputs an OFF signal to the semiconductor elements 31 and 34, and outputs an ON signal to the semiconductor elements 32 and 33. However, since the semiconductor element 34 is in a short-circuit state, it does not enter an OFF state. As a result, a short-circuit current path is formed as shown in FIG. 7.

Figure 7 shows another example of the path of short-circuit current when on/off control is being executed. Referring to Figure 7, before bypass element 25 is closed, semiconductor element 33 is turned on, placing semiconductor elements 33 and 34 in a conductive state, causing short-circuit current to flow through path R5 of capacitor EN, semiconductor element 33, and semiconductor element 34. This consumes the energy stored in capacitor EN, and by the time bypass element 25 is actually closed, the energy stored in capacitor EN has been fully consumed. Therefore, the short-circuit current flowing through path R2 in Figure 4 after bypass element 25 is closed is suppressed, preventing damage to bypass element 25.

The reason why semiconductor element 31 is turned off when an abnormality related to a short circuit in semiconductor element 34 occurs will be explained. Specifically, when semiconductor elements 33 and 34 are conductive, the charge in capacitor EN is discharged via path R5 in Figure 7, and when bypass element 25 is closed, current flows via path R2 in Figure 4. If semiconductor element 31 were to be turned on in this state, an overcurrent would flow via path R1 in Figure 3, potentially damaging bypass element 25. Therefore, semiconductor element 31 is turned off to prevent discharge from capacitor EP.

In addition, between the time when semiconductor element 34 short-circuits and the time when bypass element 25 is actually closed, semiconductor element 32 is controlled to the on state to form a current path (i.e., path R4 in Figure 6) for bypassing converter cell 10.

As described above, in the event of a short-circuit related abnormality in semiconductor element 34, semiconductor element 33 is turned on to allow current to flow through path R5 (see Figure 7) to consume the energy of capacitor EN, semiconductor element 31 is turned off to prevent overcurrent from capacitor EP from flowing to bypass element 25 through path R1 (see Figure 3), and semiconductor element 32 is turned on to allow current to flow through path R4 (see Figure 6) to bypass converter cell 10.

(When an abnormality occurs in the semiconductor elements 32 and 33)
Assume that the cell control unit 15 detects a short-circuit-related abnormality in the semiconductor element 32 or the semiconductor element 33. In this case, the cell control unit 15 also outputs a close signal to the bypass element 25, outputs an OFF signal to the semiconductor elements 31 and 34, and outputs an ON signal to the semiconductor elements 32 and 33.

If a short-circuit related abnormality is detected in semiconductor element 32 or semiconductor element 33, and if semiconductor element 31 is turned on while bypass element 25 is closed, an overcurrent will flow along path R1 in Figure 3. Therefore, semiconductor element 31 is controlled to the off state, thereby preventing discharge from capacitor EP. If semiconductor element 34 is turned on while bypass element 25 is closed, an overcurrent will flow along path R2 in Figure 4. Therefore, semiconductor element 34 is controlled to the off state, thereby preventing discharge from capacitor EN.

When a short-circuit related abnormality occurs in semiconductor element 32, semiconductor element 33 is controlled to the ON state, and when a short-circuit related abnormality occurs in semiconductor element 33, semiconductor element 32 is controlled to the ON state. This bypasses converter cell 10.

(summary)
As described above, if an abnormality occurs in either switching circuit 21 or switching circuit 22 (i.e., any of semiconductor elements 31 to 34), semiconductor elements 31 and 34 are controlled to the OFF state, and semiconductor elements 32 and 33 are controlled to the ON state, during the period before bypass element 25 is closed. This suppresses overcurrent to bypass element 25, preventing damage to bypass element 25.

<Flowchart>
8 is a flowchart showing an example of a processing procedure of cell control unit 15 according to the first embodiment. Referring to FIG. 8, cell control unit 15 determines (step S10) whether or not an abnormality has been detected in either switching circuit 21 or 22. If no abnormality has been detected (NO in step S10), cell control unit 15 repeats step S10.

If such an abnormality is detected (YES in step S10), the cell control unit 15 outputs a closed signal to the bypass element 25 (step S12), an OFF signal to the semiconductor elements 31 and 34 (step S14), and an ON signal to the semiconductor elements 32 and 33 (step S16). Note that the processing of steps S12, S14, and S16 may be performed in any order or simultaneously. However, it is assumed that the closed circuit of the bypass element 25 is established after the ON/OFF states of the semiconductor elements 31 to 34 are established.

<Advantages>
According to the first embodiment, even if a short-circuit-related abnormality occurs in each of the semiconductor elements 31 to 34, the bypass element 25 can be appropriately protected by suppressing the overcurrent flowing through the bypass element 25. Therefore, even if an abnormality occurs in any of the converter cells 10, the operation of the power conversion device 100 can be continued. Furthermore, a small, lightweight, and inexpensive bypass element can be adopted.

Embodiment 2.
In the above-described first embodiment, a configuration has been described that prevents damage to the bypass element 25 when a short-circuit-related abnormality occurs in the semiconductor elements 31 to 34. In the second embodiment, a configuration will be described that prevents damage to the bypass element 25 when the semiconductor elements 31 to 34 are in a normal state but the bypass element 25 is erroneously closed.

Referring to Figure 3, if the bypass element 25 malfunctions (i.e., closes) due to noise or other factors while the semiconductor element 31 is controlled to the on state, capacitor EP is shorted and a short-circuit current flows through path R1. If the semiconductor element 31 has not yet failed, this short-circuit current is limited to a saturation current value (e.g., several kA). However, the semiconductor element will fail within several μs to several tens of μs and enter a completely short-circuited state. In this case, the current flowing through the bypass element 25 will instantly rise to several tens to several hundred kA.

To prevent this, the cell control unit 15 has an arm short-circuit protection function to protect the semiconductor element 31. The arm short-circuit protection function protects the semiconductor element 31 from short-circuit current that flows when the capacitor EP shorts out through the semiconductor element 31.

The cell control unit 15 directly or indirectly detects that a short-circuit current has flowed through the semiconductor element 31 and shuts off the semiconductor element 31 (for example, by switching it to the off state). The cell control unit 15 achieves this shutoff within a few microseconds to a few tens of microseconds before the semiconductor element 31 fails, thereby eliminating the short-circuit current.

Semiconductor elements generally have tolerance characteristics (i.e., the ability to withstand short-circuit currents within 2 μs to 10 μs). Therefore, semiconductor element 31 can be protected by shutting it off within 2 μs to 10 μs after a short-circuit current occurs. This prevents semiconductor element 31 from breaking down, preventing currents of tens to hundreds of kA from flowing through bypass element 25. This prevents damage to bypass element 25.

The cell control unit 15 may shut off the semiconductor element 31 using a "soft shutdown" operation, which shuts off the semiconductor element 31 using a switching operation that is slower than the switching operation used in normal control. This is done to suppress the surge voltage that occurs across the semiconductor element when it is shut off, since the saturation current of the semiconductor element is larger than the current that is normally controlled.

Next, we will explain the configuration that prevents damage to the bypass element 25 when the bypass element 25 malfunctions (i.e., closes) while the semiconductor element 34 is in the on state. Referring to Figure 4, if the bypass element 25 malfunctions while the semiconductor element 34 is controlled to the on state, capacitor EN is short-circuited and a short-circuit current flows through path R2. As mentioned above, the semiconductor element 34 becomes completely short-circuited within a few microseconds to a few tens of microseconds.

The cell control unit 15 therefore has an arm short-circuit protection function that protects the semiconductor element 34 from short-circuit current that flows when the capacitor EN is shorted via the semiconductor element 34. The cell control unit 15 detects that a short-circuit current has flowed through the semiconductor element 34, and cuts off the semiconductor element 34 to remove the short-circuit current before the semiconductor element 34 fails. The cell control unit 15 may also output an ON signal to the semiconductor elements 32 and 33.

Figure 9 is a diagram illustrating an example of a short-circuit current detection method. Referring to Figure 9, current sensors 51 to 55 are provided in converter cell 10. Current sensor 51 is provided between capacitor EP and semiconductor element 31, current sensor 52 is provided between the connection point of semiconductor elements 31, 32 and bypass element 25, and current sensor 53 is provided between the connection point of semiconductor elements 33, 34 and bypass element 25. Current sensor 54 is provided between capacitor EN and semiconductor element 34, and current sensor 55 is provided between the connection point of capacitor EP and capacitor EN and the connection point of semiconductor elements 32, 33.

When the cell control unit 15 detects a short-circuit current based on the detection signal from at least one of the current sensors 51-55 (i.e., when it detects a short-circuit current flowing through the semiconductor element 31 or the semiconductor element 34), it shuts off the semiconductor element 31 and the semiconductor element 34 (i.e., controls them to the off state). It is sufficient that at least one of the current sensors 51-55 is provided.

Figure 10 is a diagram illustrating another example of a short-circuit current detection method. Referring to Figure 10, the cell control unit 15 has, for a target semiconductor element 61 (e.g., semiconductor element 31), a gate drive circuit 60, a detection unit 62 that detects short-circuit current, and a cutoff unit 63 that performs a cutoff operation when a short-circuit current is detected.

When an ON signal is input to the semiconductor element 31, the detection unit 62 determines whether the collector potential is equal to or greater than a specified potential. When a short-circuit current is flowing, the voltage of capacitor EP is applied to both ends of the semiconductor element 31, causing the ON-state voltage to rise. On the other hand, when no short-circuit current is flowing, the voltage drop across the semiconductor element 31 is several volts. The detection unit 62 determines whether a short-circuit current is flowing by comparing the detected collector potential using a comparator.

The cutoff unit 63 receives a signal from the detection unit 62 and performs a cutoff operation on the semiconductor element 31. The cutoff unit 63 may employ a "soft cutoff" that cuts off via a resistance greater than that used during normal operation.

Figure 11 is a diagram illustrating yet another example of a short-circuit current detection method. Referring to Figure 11, the cell control unit 15 detects short-circuit current using parasitic inductances 71 and 72 in the wiring of the converter cell 10.

Let's assume that a short-circuit current is occurring along path R1 (see Figure 3) in semiconductor element 31. In this case, a self-induced electromotive force is generated along path R1 based on the change in the short-circuit current over time, causing a voltage to be generated in parasitic inductance 71 on the emitter side of semiconductor element 31. Therefore, the cell control unit 15 detects the short-circuit current flowing through semiconductor element 31 based on the voltage of parasitic inductance 71. For example, the cell control unit 15 determines that a short-circuit current has occurred when the voltage of parasitic inductance 71 is equal to or greater than a threshold value.

When detecting short-circuit current flowing through the bypass element 25, if the detection method using the collector potential described in Figure 10 is used, the rise in collector potential is slow, making it difficult to detect the short-circuit current itself, or it may take a long time to detect it. In this respect, the detection method of Figure 11 is more useful than the detection method of Figure 10.

The cell control unit 15 also detects the short-circuit current of path R2 (see Figure 4) by monitoring the voltage of parasitic inductance 72 on the emitter side of semiconductor element 34. Note that the short-circuit path passing through semiconductor element 33 (i.e., path R1) includes semiconductor element 31, and the short-circuit path passing through semiconductor element 32 (i.e., path R2) includes semiconductor element 34. Therefore, the cell control unit 15 only needs to monitor the voltages of parasitic inductances 71 and 72 on the emitter sides of semiconductor elements 31 and 34.

Figure 12 is a flowchart showing an example of the processing procedure of the cell control unit 15 according to the second embodiment. Referring to Figure 12, the cell control unit 15 determines whether or not a short-circuit current flowing through the semiconductor element 31 or the semiconductor element 34 has been detected (step S50). If a short-circuit current has not been detected (NO in step S50), the cell control unit 15 repeats step S50.

If a short-circuit current is detected (YES in step S50), an OFF signal is output to semiconductor element 31 (step S52), and an OFF signal is output to semiconductor element 34 (step S54). This removes the short-circuit current. Note that steps S52 and S54 may be performed in any order or simultaneously. Furthermore, cell control unit 15 may output ON signals to semiconductor elements 32 and 33.

According to embodiment 2, the bypass element 25 can be appropriately protected even if the bypass element 25 is accidentally closed.

Embodiment 3.
In the above-described first embodiment, a configuration has been described in which the semiconductor element 32 is turned on to consume the energy stored in the capacitor EP when a short-circuit related abnormality occurs in the semiconductor element 31. However, in this case, an overcurrent flows in the semiconductor elements 31 and 32 when a high voltage is applied thereto, and therefore, if energy exceeding the short-circuit withstand capacity of the semiconductor elements 31 and 32 is applied, the semiconductor elements 31 and 32 may be destroyed to a large extent (for example, destroyed with an explosion).

To prevent deformation of converter cells due to the above-mentioned events, semiconductor elements or converter cells are designed with explosion-proofing in mind. However, there is variation in the short-circuit tolerance of semiconductor elements, and it is difficult to accurately grasp the state of an explosion. Therefore, even with an explosion-proof design, there is a possibility of unexpected converter cell failure. Furthermore, if this damages the bypass element or the bypass element's control board, it becomes difficult for the bypass element to bypass the converter cell, which could force the entire power converter to shut down.

Therefore, in embodiment 3, we describe a configuration in which, in the event of a short-circuit-related abnormality in semiconductor element 31, capacitor EP is discharged and bypass element 25 is closed while avoiding large-scale destruction of semiconductor elements 31 and 32.

Figure 13 is a diagram illustrating an example in which a semiconductor element suffers large-scale destruction. Referring to Figure 13, when a short-circuit-related abnormality occurs in semiconductor element 31, the resistance value between the collector and emitter of semiconductor element 31 decreases. Subsequently, when cell control unit 15 detects a short-circuit-related abnormality in semiconductor element 31, it outputs an ON signal to semiconductor element 32. When semiconductor element 32 enters the ON state, the resistance value between the collector and emitter of semiconductor element 32 decreases. As a result, energy in capacitor EP begins to be consumed, and the energy applied to semiconductor elements 31 and 32 increases.

Then, several microseconds to several tens of microseconds after semiconductor element 32 is turned on, the energy applied to semiconductor elements 31 and 32 exceeds their short-circuit resistance, causing them to be destroyed. This occurs because the applied energy causes the temperature of semiconductor elements 31 and 32 to rise rapidly. The example in Figure 13 shows how all of the energy from capacitor EP is consumed by semiconductor elements 31 and 32. Because all of the energy from capacitor EP is applied to semiconductor elements 31 and 32 within a period of several microseconds to several tens of microseconds, the scale of damage to semiconductor elements 31 and 32 is large. Below, we will explain a control method for semiconductor element 32 that avoids such large-scale damage to semiconductor elements 31 and 32.

Figure 14 is a diagram illustrating a semiconductor element control method according to embodiment 3. Referring to Figure 14, when a short-circuit-related abnormality occurs in semiconductor element 31, the resistance value between the collector and emitter of semiconductor element 31 decreases. When cell control unit 15 detects a short-circuit-related abnormality in semiconductor element 31, it begins control to intermittently turn semiconductor element 32 on and off. That is, when a short-circuit-related abnormality in semiconductor element 31 is detected, cell control unit 15 alternately switches semiconductor element 32 between the on state and the off state during the period before bypass element 25 is closed. Semiconductor elements 33 and 34 are controlled in the same way as in embodiment 1. Specifically, cell control unit 15 maintains semiconductor element 33 in the on state and semiconductor element 34 in the off state.

By the above control, the energy applied to semiconductor elements 31 and 32 is high when semiconductor element 32 is in the on state, but is low when semiconductor element 32 is in the off state. As a result, the energy of capacitor EP is gradually consumed, suppressing a sudden rise in temperature of semiconductor elements 31 and 32. As a result, damage to semiconductor elements 31 and 32 can be prevented. Alternatively, since semiconductor elements 31 and 32 reach damage when the energy of capacitor EP has been sufficiently reduced, the scale of damage to semiconductor elements 31 and 32 can be reduced.

For example, even if the semiconductor element 32 is turned on for a few microseconds before the bypass element 25 is closed (e.g., a few milliseconds after the on signal is output), and then an off period of tens to hundreds of microseconds is provided to allow the temperature to drop, the semiconductor element 32 can be turned on and off several times.

The above describes a configuration in which semiconductor element 32 alternates between the on and off states when a short-circuit-related abnormality occurs in semiconductor element 31, but a similar phenomenon can occur when a short-circuit-related abnormality occurs in semiconductor element 34. In other words, if semiconductor element 33 is turned on when a short-circuit-related abnormality occurs in semiconductor element 34, the energy of capacitor EN may increase the scale of damage to semiconductor elements 33 and 34.

For this reason, when the cell control unit 15 detects a short-circuit-related abnormality in semiconductor element 34, it controls semiconductor element 33 to turn on and off intermittently. That is, when a short-circuit-related abnormality in semiconductor element 34 is detected, the cell control unit 15 alternately switches semiconductor element 33 between the on and off states during the period before bypass element 25 is closed. Note that the same control as in embodiment 1 is performed on semiconductor elements 31 and 32. Specifically, the cell control unit 15 maintains semiconductor element 31 in the off state and semiconductor element 32 in the on state. This prevents damage to semiconductor elements 33 and 34 due to the energy of capacitor EN, or reduces the scale of such damage.

Other methods may be employed to gradually consume the energy of capacitors EP and EN. Specifically, when the cell control unit 15 controls semiconductor element 32 to turn on during a short-circuit-related abnormality in semiconductor element 31, it reduces the gate voltage of semiconductor element 32 when it is on below the gate voltage during normal switching. This limits the current flowing from capacitor EP to semiconductor element 32, thereby suppressing a sudden increase in temperature in semiconductor elements 31 and 32. As a result, it is possible to prevent damage to each semiconductor element 31 and 32, or to reduce the scale of damage to each semiconductor element 31 and 32. Similarly, when the cell control unit 15 controls semiconductor element 33 to turn on during a short-circuit-related abnormality in semiconductor element 34, it may reduce the gate voltage of semiconductor element 33 when it is on below the gate voltage during normal switching.

According to embodiment 3, it is possible to prevent damage to semiconductor elements due to the energy of capacitors EP and EN, or to reduce the scale of such damage.

Embodiment 4.
The third embodiment described above describes a configuration that prevents damage to semiconductor elements 31 and 32 (or reduces the scale of damage) by alternately switching the on state and off state of one semiconductor element 32. The fourth embodiment describes a configuration that prevents damage to semiconductor elements 31 and 32 by connecting one or more semiconductor elements in parallel to semiconductor element 32 and controlling these semiconductor elements to be sequentially turned on.

Figure 15 is a diagram illustrating a semiconductor element group according to embodiment 4. Referring to Figure 15, semiconductor element group 320 includes semiconductor elements 32, 32A, 32B, and 32C, a high-potential side terminal Xp, and a low-potential side terminal Xn. Terminal Xp is connected to the negative terminal of semiconductor element 31. Terminal Xn is connected to the positive terminal of semiconductor element 33. Semiconductor elements 32, 32A, 32B, and 32C are connected in parallel with each other.

Figure 16 is a diagram illustrating a control method for a semiconductor element group according to embodiment 4. Referring to Figure 16, when a short-circuit-related abnormality occurs in semiconductor element 31, the resistance value between the collector and emitter of semiconductor element 31 decreases. When cell control unit 15 detects a short-circuit-related abnormality in semiconductor element 31, it begins control to alternately turn on semiconductor elements 32 to 32C included in semiconductor element group 320.

Specifically, the cell control unit 15 turns semiconductor element 32 on a fixed time later and then turns it off. Next, the cell control unit 15 turns semiconductor element 32A on a fixed time later and then turns it off. Thereafter, the cell control unit 15 performs similar control on semiconductor elements 32B and 32C. In other words, if a short-circuit-related abnormality is detected in semiconductor element 31, the cell control unit 15 controls the on and off states of each of the multiple semiconductor elements 32-32C during the period before the bypass element 25 is closed, so that the on time of each of the multiple semiconductor elements 32-32C does not overlap with the on time of other semiconductor elements.

This control disperses the energy applied to semiconductor elements 31, 32-32C, preventing damage to each semiconductor element 31, 32-32C due to the energy of capacitor EP, or reducing the scale of such damage.

The cell control unit 15 may control the on/off of semiconductor elements 32-32C using a gate driver that drives multiple semiconductor elements collectively, or may control the on/off of semiconductor elements 32-32C using individual gate drivers.

Furthermore, destruction of semiconductor elements 33 and 34 may be prevented by connecting another semiconductor element (also referred to as "semiconductor element G" for convenience) in parallel to semiconductor element 33 and sequentially controlling these semiconductor elements to the ON state. Specifically, when the cell control unit 15 detects a short-circuit-related abnormality in semiconductor element 34, it begins control to alternately turn on semiconductor element 33 and semiconductor element G. In other words, when a short-circuit-related abnormality in semiconductor element 34 is detected, the cell control unit 15 controls the ON and OFF states of semiconductor element 33 and semiconductor element G during the period before the bypass element 25 is closed, so that the ON time of semiconductor element 33 does not overlap with the ON time of semiconductor element G. Note that, as in the example of Figure 15, a configuration in which multiple semiconductor elements G are provided may also be used.

According to embodiment 4, it is possible to prevent damage to semiconductor elements due to the energy of capacitors EP and EN, or to reduce the scale of such damage.

Other embodiments.
(1) In the above-described first embodiment, if the semiconductor elements 31 and 32 both experience an open circuit failure due to the energy of the capacitor EP being consumed in the semiconductor elements 31 and 32 before the bypass element 25 is closed, the converter cell 10 is in an open state and has a high impedance until the bypass element 25 is closed. The same applies to the case where the semiconductor elements 33 and 34 both experience an open circuit failure due to the energy of the capacitor EN being consumed in the semiconductor elements 33 and 34 before the bypass element 25 is closed.

In this case, if a voltage higher than expected is applied to the input/output terminals Po and No of the converter cell 10, an arc discharge or the like may occur, possibly causing damage to peripheral devices of the converter cell 10. Therefore, a resistor such as that shown in Figure 17 may be provided in the converter cell 10.

Figure 17 is a diagram showing a modified example of the converter cell 10. Referring to Figure 17, the converter cell 10 according to this modified example has a configuration in which a resistor 27 is added to the converter cell 10 of Figure 2. The resistor 27 is connected in parallel to the bypass element 25. The resistor 27 has a high resistance such that the converter cell 10 does not enter an open state.

(2) Figure 18 is a diagram illustrating an example configuration of the cell control unit 15. Referring to Figure 18, the cell control unit 15 includes a control circuit 81 for controlling the switching circuit 21 and a control circuit 82 for controlling the switching circuit 22.

Specifically, control circuit 81 performs on/off control of semiconductor elements 31 and 32. Control circuit 82 performs on/off control of semiconductor elements 33 and 34. In addition, control circuit 81 detects short-circuit-related abnormalities in semiconductor elements 31 and 32, and control circuit 82 detects short-circuit-related abnormalities in semiconductor elements 33 and 34.

For example, when control circuit 81 detects a short-circuit-related abnormality in semiconductor element 31, it outputs an OFF signal to semiconductor element 31 and an ON signal to semiconductor element 32. Control circuit 81 also sends an abnormality signal indicating the short-circuit-related abnormality to control circuit 82. When control circuit 82 receives the abnormality signal, it outputs an ON signal to semiconductor element 33 and an OFF signal to semiconductor element 34.

For example, when control circuit 82 detects a short-circuit-related abnormality in semiconductor element 34, it outputs an OFF signal to semiconductor element 34 and an ON signal to semiconductor element 33. Control circuit 82 also sends an abnormality signal indicating the short-circuit-related abnormality to control circuit 81. When control circuit 81 receives the abnormality signal, it outputs an OFF signal to semiconductor element 31 and an ON signal to semiconductor element 32.

Control circuit 81 includes a drive circuit for driving semiconductor element 31 and a drive circuit for driving semiconductor element 32. Control circuit 82 includes a drive circuit for driving semiconductor element 33 and a drive circuit for driving semiconductor element 34. These drive circuits must be electrically insulated from each other to prevent dielectric breakdown. For example, even if each drive circuit is mounted on the same universal board, the patterns connected to each semiconductor element 31 to 34 must be insulated. To prevent electrical breakdown, each drive circuit may be mounted on an independent circuit board.

(3) Figure 19 is a diagram illustrating another example configuration of the cell control unit 15. Referring to Figure 19, the cell control unit 15 includes control circuits 91 to 94 for controlling the semiconductor elements 31 to 34, respectively. The control circuits 91 to 94 each include a drive circuit for driving the semiconductor elements 31 to 34. Note that the cell control unit 15 may also be configured to control the semiconductor elements 31 to 34 using a single control circuit. In this case, the control circuit includes four drive circuits for driving the four semiconductor elements 31 to 34.

(4) The configurations exemplified as the above-described embodiments are examples of the configurations of the present disclosure, and may be combined with other known technologies. They may also be modified, such as by omitting some parts, without departing from the spirit of the present disclosure. Furthermore, the above-described embodiments may also be implemented by appropriately adopting the processes and configurations described in other embodiments.

The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications that are equivalent in meaning to and within the scope of the claims.

10 Converter cell, 14N, 14P Reactor, 15 Cell control unit, 21, 22 Switching circuit, 25 Bypass element, 27 Resistor, 31-34 Semiconductor elements, 31d-34d Diodes, 31s-34s Switching elements, 40u-40w Leg circuit, 51-55 Current sensor, 60 Gate drive circuit, 62 Detection unit, 63 Cutoff unit, 71, 72 Parasitic inductance, 81, 82, 91, 94 Control circuit, 100 Power conversion device, 110 Power converter, 120 Control device, 130 DC circuit, 140 Transformer, 150 AC circuit, 320 Semiconductor element group.

Claims (2)

A power conversion device comprising a plurality of converter cells connected in series,
Each of the plurality of converter cells comprises:
A cell control unit;
a first switching circuit and a second switching circuit connected in series;
a first input/output terminal and a second input/output terminal;
a bypass element connected between the first input/output terminal and the second input/output terminal;
the first switching circuit includes a first semiconductor device, a second semiconductor device, and a first energy storage element connected in parallel to a series circuit including the first semiconductor device and the second semiconductor device;
the first input/output terminal is connected to a connection point between a negative terminal of the first semiconductor element and a positive terminal of the second semiconductor element;
the second switching circuit includes a third semiconductor device, a fourth semiconductor device, and a second energy storage element connected in parallel to a series circuit including the third semiconductor device and the fourth semiconductor device;
the second input/output terminal is connected to a connection point between a negative terminal of the third semiconductor element and a positive terminal of the fourth semiconductor element;
When a short-circuit current flowing through the first semiconductor element or a short-circuit current flowing through the fourth semiconductor element is detected, the cell control unit controls the first semiconductor element and the fourth semiconductor element to an off state. The power conversion device according to claim 1 , wherein the cell control unit detects the short-circuit current flowing through the first semiconductor element based on a voltage of a parasitic inductance on an emitter side of the first semiconductor element.