JP7719761B2 - Method for manufacturing a multilayer chip card and multilayer chip card - Google Patents

Description

The present invention relates to a method for manufacturing a multi-layer chip card, also known as an IC card or smart card, and to a multi-layer chip card, particularly a dual-interface chip card. A dual-interface chip card is a chip card that combines an integrated circuit chip (IC chip), metallic contact pads for conductive communication with the IC chip, and an antenna for contactless communication with the IC chip within a single card structure.

Typically, the IC chip and contact pads are mounted as a chip module. In this chip module, the IC chip and contact pads are mounted on opposite sides of a support substrate. Contact between the IC chip and the contact pads is made through the support substrate on which they are mounted. The chip module is mounted within a cavity in the card body, such that the contact pads of the chip module are flush with the outer surface of the card body and the IC chip is concealed within the cavity. The antenna in a dual interface chip card typically takes the form of an antenna coil embedded inside the card body. Two antenna contact areas are exposed within the cavity in the card body, such that when the chip module is mounted within the cavity, both antenna contact areas contact corresponding contact areas on the underside of the chip module, thereby providing a conductive connection to the IC chip in the chip module.

Patent Document 1 discloses a dual interface smart card in which an IC chip, contact pads, and antenna are all mounted on the same flexible support substrate made of polyethylene terephthalate (PET), with this support substrate forming the core layer of the card body. The front layer has through holes and is positioned on the front side of the core layer so that the contact pads are housed in the through holes. The back layer has a cavity and is assembled to the back side of the core layer so that the IC chip is housed in the cavity. The IC chip and contact pads are electrically connected to conductor patterns provided on the core layer and do not overlap when viewed from the front side to the back side.

According to Patent Document 1, the core layer and backside layer are first laminated as a stack in a high-temperature cycle at a temperature of at least 80°C and a pressure of 2 MPa for approximately 30 minutes, followed by a low-temperature cycle at a temperature of 30°C or less and again at 2 MPa for approximately 20 minutes. During lamination, the backside layer softens, and an IC chip mounted as a flip chip on the core layer is pressed and embedded into the softened backside layer. After cooling, the laminate structure is then laminated to the frontside layer under the same conditions. In this case, the contact pads on the core layer are inserted into the through-holes in the frontside layer, thereby forming a continuous, flat surface with the front side of the final laminate structure. Alternatively, the contact pads and IC chip can be located on the same side of the core layer, in which case the cavity for accommodating the IC chip is located on the backside of the frontside layer.

European Patent No. 3384434B1

The object of the present invention is to improve the external appearance of a chip card having the above-mentioned core layer structure, i.e., a core layer structure comprising at least contact pads and an IC chip arranged without overlapping the contact pads, laminated to a further layer, thereby forming the chip card.

This object is achieved by a method and a multi-layer chip card as claimed in the accompanying independent claims. Specific features of preferred embodiments and refinements of the invention are set out in the dependent claims.

A first aspect of the present invention is a method for manufacturing a multi-layer chip card, comprising the steps of:
a core layer structure having a front side and a back side, with contact pads provided on the front side, and further comprising an IC chip and a conductor pattern, the IC chip and the contact pads being conductively connected to the conductor pattern and not overlapping when viewed from the front side towards the back side;
a surface layer structure arranged on the surface side of the core layer structure, the surface layer structure having through holes with a cross-sectional shape that corresponds substantially in size and position to the outer contours of contact pads provided on the surface side of the core layer structure;
a backside layer structure provided on the backside of the core layer structure;
a label is provided between the back layer structure and the core layer structure, in which, when viewed from the front side towards the back side, the label and the contact pads overlap completely or at least to a large extent.

The stacked front, core, and back layer structures, including the label positioned between the core and back layer structures, are then laminated by applying heat and pressure to the stack. The cross-sectional shape of the through-holes substantially corresponds in size and position to the outer contours of the contact pads so that the contact pads pass through the through-holes during lamination and are preferably flush with the outer surface of the laminated stack.

A second aspect of the invention relates to a multi-layer chip card having a corresponding structure. If the chip card to be manufactured is a dual-interface chip card, the core layer structure may further comprise an antenna, e.g., an antenna coil, conductively connected to the IC chip. Preferably, the IC chip and the contact pads are provided on a common substrate, more preferably on opposite sides of the common substrate. In particular, the IC chip and the contact pads may be arranged at a lateral distance from each other.

The label, located between the back layer structure and the core layer structure, serves to compensate for any unevenness that may occur on the front and/or back side of the laminated stack. During stack lamination, the label generates localized pressure on the back side of the core layer structure, forcing the core layer structure, along with the contact pads on its front side, into the through-holes of the front layer structure. That is, the contact pads are relatively thin compared to the thickness of the front layer structure, which is pressed flush with the outer surface of the laminated stack. Thus, the label material compensates to some extent for any lack of material in the through-holes.

Preferably, the label has an outer contour that substantially corresponds in size and position to the outer contour of the contact pads provided on the front side of the core layer structure. This ensures that pressure generated by the label during lamination is evenly distributed over the entire area of the contact pads.

The thickness of the label is preferably selected to be the same as or even thicker than the thickness of the surface layer structure. For example, the thickness of the label may be selected to be 5% to 15% thicker than the thickness of the surface layer structure. As mentioned above, the volume of the label will compensate for the lack of material in the through-holes of the surface layer structure. Overcompensation is preferable to undercompensation, as the excess material will flow and be evenly distributed between the layer structures. In a preferred embodiment, the thickness of the surface layer structure is selected to be 0.3 mm or slightly less, and the thickness of the label is selected to be 0.3 mm or slightly more than 0.3 mm.

Preferably, the labels are formed from glycol-modified polyethylene terephthalate (PETG) due to its relatively low viscosity.

In a preferred embodiment, the core layer structure is formed from a first layer on which an IC chip is mounted and a second layer having an opening, whereby the IC chip mounted on the first layer is housed within the opening in the second layer. This reduces the force applied to the IC chip during the lamination process. More specifically, the opening is preferably larger in size than the IC chip, whereby the IC chip is housed inside the opening without being exposed to any force when these two layers are laminated together with the remaining layers of the multilayer structure.

In one embodiment, the openings in the second layer of the core layer structure have the form of through-holes, and adhesive may be provided in the area of the through-holes, so that when the second layer of the core layer structure is brought into contact with the backside layer structure, a bonding connection is achieved between the IC chip housed in the through-hole and the backside layer structure.

It is further preferred that at least one of the front and back layer structures be formed from a plurality of layers, at least two, preferably three. For example, the inner layer of at least one of the front and back layer structures may have properties that favor contact with the aforementioned first layer supporting the contact pads or the aforementioned second layer housing the IC chip. One or both of the inner layers may support an adhesive to improve bonding to the core layer structure. The outer layer of the front and/or back layer structure may provide good protective and/or scratch-resistant properties. One layer of the front and/or back layer structure, for example, the intermediate layer, may have good print quality and may have one or more prints. For example, at least one layer of the front and/or back layer structure may be white and/or have print visible from outside the laminated stack.

To further improve the external appearance of the laminated stack, an isolating film may be provided on one or both of the front and back sides of the stack, preferably at least the front side of the stack, prior to the laminating step, and removed after the laminating step. For this purpose, the isolating film may comprise or is preferably made of polyethylene terephthalate (PET). The isolating film serves to protect the laminating plate from receiving marks that may be caused, for example, by perforations provided in particular in the front layer structure. Overall, the external appearance of the front and back sides of the laminated stack, and thus the external appearance of the final chip card, is improved.

With respect to the lamination process, preferably, the front layer structure, the core layer structure, and the back layer structure are stacked and laminated together in a single lamination process. More preferably, if one or more of these layer structures has more than one layer, all layers of all layer structures are stacked and laminated together in a single lamination process.

The lamination process includes a first heating step at a first heating temperature, a second heating step at a second heating temperature higher than the first heating temperature, and then a cooling step. This avoids the generation of bubbles and, if present, exposure of the antenna. The first heating temperature may be set within a range of 120°C to 130°C, for example, 125°C, and the second heating temperature may be set within a range of 140°C to 150°C, for example, 145°C. Preferably, the first heating step is performed in a first laminator, and the second heating step is performed in a separate, second laminator. Cooling may be performed at a lower temperature, for example, around 20°C. Cooling may be performed in the second laminator.

According to a preferred embodiment, the pressure is increased during the first heating step, further increased during the second heating step, and preferably still further increased during the cooling step. For example, the pressure may be increased continuously or stepwise from 3 bar (0.3 MPa) to 15 bar (1.5 MPa) during the first heating step, e.g., in three substeps of 3 bar (0.3 MPa), 10 bar (1.0 MPa), and 15 bar (1.5 MPa). The pressure may also be increased continuously or stepwise from 25 bar (2.5 MPa) to 35 bar (3.5 MPa) during the second heating step, e.g., in two substeps of 25 bar (2.5 MPa) and 35 bar (3.5 MPa). The pressure may then be further increased during the cooling step from 50 bar (5.0 MPa) to 60 bar (6.0 MPa) continuously or stepwise, for example in two sub-steps of 50 bar (5.0 MPa) and 60 bar (6.0 MPa).

Suitable durations for the heating and cooling steps and sub-steps may be selected according to the individual circumstances, in particular depending on the layer materials and layer thicknesses. The lamination temperatures and pressures described above have proven effective when the layer materials consist predominantly of PVC with additional layers formed from PET, but may also prove effective in other circumstances.

An exploded view showing multiple layers laminated together to form a multi-layer chip card.

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Figure 1 is the only view showing an exploded view of a multi-layer chip card, and more specifically, a number of layers 1.1-3.3 that are laminated together to form a dual interface chip card.

In one embodiment, a first layer structure 1, also referred to as the top layer structure, is provided. This first layer structure 1 has through holes 5 and consists of three layers 1.1, 1.2, and 1.3 in total. The top layer structure 1 may have more or fewer layers, but it comprises at least one layer.

The second layer structure 2, also referred to as the core layer structure, comprises at least a layer 2.1. This layer 2.1 supports contact pads 20 on its front side and an IC chip 10 on its back side. Furthermore, the front and back sides are provided with an antenna coil of an antenna 30. Conductive patterns on layer 2.1, which electrically connect the IC chip 10 to the contact pads 20 and the antenna 30, respectively, are not shown. Layer 2.1 may be made of PET. The IC chip 10 is mounted and connected to layer 2.1 using wire bonding techniques, and may be embedded in a polymer matrix, or flip-chip techniques may be used. The aluminum coating covering layer 2.1 of the conductor patterns (not shown), the antenna 30, and the contact pads 20 may be etched away.

In the illustrated embodiment, the core layer structure further comprises a second layer 2.2 having an opening 40 in which the IC chip 10 is housed. This second layer 2.2 may be attached to the first layer 2.1 by means of adhesive G, which may advantageously be provided in the second layer 2.2. The opening 40 may have the form of a recess in the layer 2.2 or, as in this case, may form a through-hole. When the layers are stacked one on top of the other, the opening 40 is filled with adhesive, thereby bonding the IC chip 10 to the adjacent layer. The second layer 2.2 of the core layer structure 2 serves to protect the IC chip 10.

The third layer structure 3, also referred to as the back layer structure, comprises three layers 3.1, 3.2, and 3.3. The back layer structure may include more or fewer layers than these three, but includes at least one layer. The thickness and material of layers 3.1, 3.2, and 3.3 may correspond to the thickness of layers 1.1, 1.2, and 1.3, respectively, of the front layer structure 1. The inner surfaces of the front layer structure 1 and the back layer structure 3 are coated with adhesive G, which provides a strong bond with the core layer structure 2.

Furthermore, one or both of the front layer structure 1 and the back layer structure 3 may be provided with printing P1 and/or printing P2, respectively. For example, the intermediate layers 1.2 and 3.2 of the front layer structure 1 and the back layer structure 3 may each be formed from PET. This PET may be clear, i.e., transparent, and may have printing P1 and P2 on one of its surfaces, or preferably white, i.e., opaque, and may have printing P1 and P2 on their respective outer surfaces, as shown. Additionally or alternatively, one or both of the inner layers 1.3 and 3.3 may have printing. Preferably, the inner layers 1.3 and 3.3 are formed from PVC, more preferably white PVC, i.e., opaque PVC. Finally, the outer layers 1.1 and 3.1 of the front layer structure 1 and the back layer structure 3, respectively, may be transparent and preferably also comprise PVC. The outer layers serve to protect the inner layers and printing of the multilayer structure. The printing mentioned above is printing that is visible from the outside, i.e. printing that will be visible to the user of the final chip card.

In embodiments in which the core layer structure 2 comprises only a first layer 2.1 on which electronic components are mounted, the opening 40 may be provided in the adjacent backside layer structure 3, more specifically in layer 3.3 of the backside layer structure 3. If the IC chip 10 is mounted on the front side of layer 2.1 together with the contact pads 20, the opening 40 may be provided in the frontside layer structure 1, more specifically in layer 1.3 of the frontside layer structure 1.

Additionally, a label 50 is provided. Viewed from the front to the back, this label 50 is positioned directly behind the contact pad 20. That is, this contact pad 20 has an outer contour that substantially or exactly corresponds to the cross-sectional shape of the through-hole 5, and the label 50 also has an outer contour that substantially or exactly corresponds to the outer contour of the contact pad. When layers 1.1 to 3.3 are laminated together, the contact pad 20 is pressed through the through-hole 5 so that it is flush with the outer surface of the entire stack. The label 50 behind the contact pad 20 supports this process.

The label 50 is made from PETG, which melts at a relatively low temperature and has a low viscosity so that it flows easily when melted.

The individual layers 1.1-3.3 may be stacked in groups and spot-welded to one another, and then the groups may be stacked on top of one another and laminated, thereby increasing positioning accuracy. For example, layers 1.1-1.3 of the front layer structure 1 may be stacked in a first group and spot-welded to one another, for example, using a soldering iron. Then, through-holes 5 are punched out of the spot-welded group of stacked layers 1.1-1.3. After punching out openings 40 in layer 2.2 of the core layer structure 2, layers 2.1 and 2.2 of the core layer structure 2 may be stacked on top of layer 3.3 of the back layer structure 3. A label 50 is placed between layers 2.2 and 3.3 in the correct position to cover the contact pads 20. Then, layers 3.2 and 3.1 of the back layer structure are stacked and spot-welded to one another, thereby forming a third group of spot-welded layers. The first and second groups of spot-welded layers are then stacked and transferred to a laminating machine, where all of the layers are laminated together, thereby forming a unitary multi-layer structure.

Naturally, the dimensions shown in the drawings are not to scale and should be understood only as an approximate representation. However, the thickness ratios of the individual layers are to scale. That is, PVC layers 1.3, 2.2, and 3.3 may have a thickness of 150 μm, PVC layers 1.1 and 3.1 may have a thickness of 80 μm, PET layers 1.2 and 3.2 may have a thickness of 100 μm, and PET layer 2.1, also known as the "inlay" that supports the electronic elements, may have a thickness of 40 μm, resulting in a total thickness of the final laminated layer stack of approximately 850 μm. PETG label 50 may have a thickness of 300 μm, which is slightly thicker than the combined thickness of layers 1.1-1.3 of front layer structure 1.

The exposed surface of the back layer structure 3 may carry further elements, such as security elements 60, for example a hologram, a signature area 70, a magnetic stripe 80, and the like. While the signature area and magnetic stripe are applied to the exposed surface of layer 3.1 of the back layer structure 3 prior to the lamination step, the hologram 60 may be applied after lamination, for example in a hot stamping process.

The lamination process is carried out in two sequential laminator machines to minimize production time on a continuous production line. In the first machine, the stack is subjected to a temperature of 125°C at successively increasing pressures of 3 bar (0.3 MPa), 10 bar (1.0 MPa), and 15 bar (1.5 MPa) for 480, 120, and 420 seconds, respectively. In the second laminator, the stack is subjected to a higher temperature of 145°C at successively increasing pressures of 25 bar (2.5 MPa) and 35 bar (3.5 MPa) for 300 and 720 seconds, respectively. Finally, the layer stack is subjected to a 20°C cooling step at successively increasing pressures of 50 bar (5.0 MPa) and 60 bar (6.0 MPa) for 300 and 720 seconds, respectively. This avoids bubble formation and exposure of the antenna 30. The cooling step may be performed in a second laminator or in a separate third laminator.

During the lamination step, an isolation film (not shown) is provided on at least the front side of the stack, i.e., the outer surface of the front layer structure 1, preferably on both the front side and the back side of the stack prior to the lamination step, and is removed after the lamination step. The isolation film includes or is preferably made of polyethylene terephthalate (PET). The isolation film may have a thickness of 0.05 mm.

Of course, the layers are usually provided as larger sheets in which each electronic element, hole and aperture is provided multiple times in a matrix, e.g. a 3x8 matrix, and the individual chip cards are finally die-cut from the laminated stack of sheets to the appropriate size, e.g. ID-1 size according to ISO 7810.

In addition to the visible printings described above, such as printings P1 and P2, processing markings may be provided on certain layers. These markings may also be in the form of printing. For example, printing P2.2 may be provided on the second layer 2.2 of the core layer structure 2 and serve to facilitate identification of the location where the opening 40 is to be produced, for example by punching. More specifically, printing P2.2 may completely cover the second layer 2.2 except for the area where the opening 40 is to be produced, as shown, or it may be provided only partially, i.e., exactly surrounding the opening 40. Alternatively, printing P2.2 may be provided exactly in the area of the opening 40.

Like the printing P2.2 on the second layer 2.2 of the core layer structure 2, printing P3.3 may be provided on the inner surface of the inner layer 3.3 of the third layer structure 3 and serve to facilitate identification of the location where the label 50 will be placed prior to lamination. More specifically, printing P3.3 may completely cover the inner layer 3.3 except for the area where the label 50 will be placed, as shown, or it may be only partially provided, i.e., exactly surrounding the area where the label 50 will be placed. Alternatively, printing P3.3 may be provided on the inner layer 3.3 only exactly in the area of the label 50.

Finally, the printing P1 may even serve to facilitate the identification of the locations where the through holes 5 are to be produced in the first layer structure 1, for example by punching. More specifically, the printing P1 may completely or partially cover the intermediate layer 1.2, as shown, leaving open exactly the areas where the through holes 5 are to be produced.

Preferred examples of the present invention are outlined in paragraphs 1-26 below.

1. A method for manufacturing a multi-layer chip card, comprising:
- providing a core layer structure (2) having a front side and a back side, the core layer structure (2) comprising contact pads (20) provided on the front side, and further comprising an IC chip (10) and a conductor pattern, the IC chip (10) and the contact pads (20) being conductively connected to the conductor pattern and not overlapping when viewed from the front side towards the back side;
- providing a front layer structure (1) on the front side of the core layer structure (2), the front layer structure (1) having through holes (5) with a cross-sectional shape that corresponds substantially in size and position to the outer contour of the contact pads (20) provided on the front side of the core layer structure (2);
- providing a backside layer structure (3) on the back side of said core layer structure (2);
- providing a label (50) between said back layer structure (3) and said core layer structure (2), said label (50) and said contact pads (20) overlapping completely or at least to a large extent when viewed from the front side towards the back side;
- laminating the stacked front layer structure (1), the core layer structure (2) and the back layer structure (3), including the label (50) positioned between the core layer structure (2) and the back layer structure (3), by applying heat and pressure to the stack.

2. The method of paragraph 1, wherein the label (50) has an outer contour that substantially corresponds in size and position to the outer contour of the contact pad (20) provided on the front side of the core layer structure (2).

3. The method described in paragraph 1 or 2, wherein the thickness of the label (50) is selected to be equal to or greater than the thickness of the outer layer structure (1).

4. The method described in paragraph 3, wherein the thickness of the label (50) is selected to be 5% to 15% thicker than the thickness of the outer layer structure (1).

5. The method described in paragraph 3 or 4, wherein the thickness of the surface layer structure (1) is selected to be 0.3 mm or less, and the thickness of the label (50) is selected to be 0.3 mm or more.

6. The method of any one of paragraphs 1 to 5, wherein the label (50) is formed from glycol-modified polyethylene terephthalate (PETG).

7. The method of any one of paragraphs 1 to 6, further comprising forming the core layer structure (2) from a first layer (2.1) on which the IC chip (10) is mounted and a second layer (2.2) having an opening (40), thereby accommodating the IC chip (10) provided on the first layer (2.1) within the opening (40) of the second layer (2.2).

8. The method of paragraph 7, wherein the opening (40) in the second layer (2.2) of the core layer structure (2) is a through-hole, and the method further comprises the step of providing adhesive in the area of the through-hole, thereby forming a bonding connection between the IC chip (10) accommodated in the through-hole and the back layer structure (3) when the second layer (2.2) of the core layer structure (2) is brought into contact with the back layer structure (3).

9. The method of any one of paragraphs 1 to 8, comprising forming at least one of the front layer structure (1) and the back layer structure (3) from a plurality of layers (1.1, 1.2, 1.3, 3.1, 3.2, 3.3).

10. The method of paragraph 9, wherein preferably at least one of the layers (1.3, 3.3) of the front layer structure or the back layer structure is white, and one of the layers (1.2, 3.2) of the front layer structure or the back layer structure is provided with a printing (P) that is visible from outside the stack.

11. The method of any one of paragraphs 1 to 10, including providing an isolating film on both the front side of the stack and the back side of the stack prior to the laminating step, and removing the isolating film after the laminating step.

12. The method of paragraph 11, wherein the isolating film comprises or is formed from polyethylene terephthalate (PET).

13. The method of any one of paragraphs 1 to 12, wherein the surface layer structure (1), the core layer structure (2), and the back layer structure (3) are laminated to each other in a single lamination process.

14. The method of paragraph 13, wherein one or more of the front layer structure (1), the core layer structure (2), and the back layer structure (3) comprises more than one layer, and all layers (1.1, 1.2, 1.3, 2.1, 2.2, 3.1, 3.2, 3.3) of all layer structures (1, 2, 3) are laminated to each other in the single lamination process.

15. The method of any one of paragraphs 1 to 14, wherein the laminating step includes a first heating step at a first heating temperature, a second heating step at a second heating temperature higher than the first heating temperature, and then a cooling step.

16. The method described in paragraph 15, wherein the first heating temperature is set within the range of 120°C to 130°C, and the second heating temperature is set within the range of 140°C to 150°C.

17. The method of paragraphs 15 or 16, wherein the first heating step is performed in a first laminator and the second heating step is performed in a separate second laminator.

18. The method of any one of paragraphs 15 to 17, wherein the pressure is increased during the first heating step, further increased during the second heating step, and yet further increased during the cooling step.

19. A multi-layer chip card, comprising:
a core layer structure (2) having a front side and a back side, the core layer structure (2) comprising contact pads (20) provided on the front side, and further comprising an IC chip (10) and a conductor pattern, the IC chip (10) and the contact pads (20) being conductively connected to the conductor pattern and not overlapping when viewed from the front side towards the back side;
a surface layer structure (1) provided on the surface side of the core layer structure (2), the surface layer structure (1) having through holes (5) with a cross-sectional shape that corresponds substantially in size and position to the outer contours of the contact pads (20) provided on the surface side of the core layer structure (2);
a back layer structure (3) provided on the back side of the core layer structure (2);
- a label (50) provided between the back layer structure (3) and the core layer structure (2), in which, when viewed from the front side towards the back side, the label (50) and the contact pads (20) overlap completely or at least to a large extent.

20. A multilayer chip card as described in paragraph 19, wherein the label (50) has an outer contour that substantially corresponds in size and position to the outer contour of the contact pads (20) provided on the obverse side of the core layer structure (2).

21. A multilayer chip card according to paragraph 19 or 20, wherein the label (50) is formed from glycol-modified polyethylene terephthalate (PETG).

22. A multilayer chip card according to any one of paragraphs 19 to 21, wherein the core layer structure (2) comprises a first layer (2.1) on which the IC chip (10) is mounted, and a second layer (2.2) having an opening (40) in which the IC chip (10) provided in the first layer (2.1) is accommodated.

23. The multilayer chip card of any one of paragraphs 19 to 22, wherein the core layer structure (2) comprises an antenna (30) conductively connected to the IC chip (10).

24. A multilayer chip card according to paragraph 23, wherein the IC chip (10) and the contact pads (20) are mounted on a common substrate (2.1).

25. A multilayer chip card according to paragraph 24, wherein the IC chip (10) and the contact pads (20) are provided on opposite sides of the common substrate (2.1).

26. A multilayer chip card according to any one of paragraphs 19 to 25, wherein the IC chip (10) and the contact pads (20) are laterally spaced apart from one another.

Claims (15)

1. A method for manufacturing a multi-layer chip card, comprising:
- providing a core layer structure (2) having a front side and a back side, the core layer structure (2) comprising contact pads (20) provided on the front side, and further comprising an IC chip (10) and a conductor pattern, the IC chip (10) and the contact pads (20) being conductively connected to the conductor pattern and not overlapping when viewed from the front side towards the back side;
- providing a front layer structure (1) on the front side of the core layer structure (2), the front layer structure (1) having through holes (5) with a cross-sectional shape that corresponds substantially in size and position to the outer contour of the contact pads (20) provided on the front side of the core layer structure (2);
- providing a backside layer structure (3) on the back side of said core layer structure (2);
- providing a label (50) between said back layer structure (3) and said core layer structure (2), said label (50) and said contact pads (20) overlapping completely or at least to a large extent when viewed from the front side towards the back side;
- laminating the stacked front layer structure (1), the core layer structure (2) and the back layer structure (3), including the label (50) positioned between the core layer structure (2) and the back layer structure (3), by applying heat and pressure to the stack. The method of claim 1, wherein the label (50) has an outer contour that substantially corresponds in size and position to the outer contour of the contact pad (20) provided on the front side of the core layer structure (2). 3. The method according to claim 1 or 2, wherein the thickness of the label (50) is selected to be equal to or greater than the thickness of the outer layer structure (1), and the thickness of the label (50) is selected to be 5% to 15% thicker than the thickness of the outer layer structure (1), and/or the thickness of the outer layer structure (1) is selected to be equal to or less than 0.3 mm, and the thickness of the label (50) is selected to be equal to or greater than 0.3 mm. The method of claim 1, wherein the label (50) is formed from glycol-modified polyethylene terephthalate (PETG). 2. The method according to claim 1, further comprising forming the core layer structure (2) from a first layer (2.1) on which the IC chip (10) is mounted and a second layer (2.2) having an opening (40), thereby accommodating the IC chip (10) provided on the first layer (2.1) in the opening (40) of the second layer (2.2) , the opening (40) provided in the second layer (2.2) of the core layer structure (2) being a through hole, the method further comprising providing an adhesive in the area of the through hole, thereby forming a bonding connection between the IC chip (10) accommodated in the through hole and the back layer structure (3) when the second layer (2.2) of the core layer structure (2) is brought into contact with the back layer structure (3). 2. The method of claim 1, comprising forming at least one of the front layer structure (1) and the back layer structure (3) from a plurality of layers (1.1, 1.2, 1.3, 3.1, 3.2, 3.3), wherein at least one of the layers (1.3, 3.3) of the front layer structure or the back layer structure is white, and wherein one of the layers (1.2, 3.2) of the front layer structure or the back layer structure is provided with a printing (P) that is visible from outside the stack. 2. The method of claim 1, further comprising the steps of: providing an isolating film on both the front side of the stack and the back side of the stack prior to the laminating step; and removing the isolating film after the laminating step, wherein the isolating film comprises or is formed from polyethylene terephthalate (PET). 2. The method according to claim 1, wherein the front layer structure (1), the core layer structure (2) and the back layer structure (3) are laminated together in a single lamination process , and one or more of these layer structures comprises more than one layer, and all layers (1.1, 1.2, 1.3, 2.1, 2.2, 3.1, 3.2, 3.3) of all layer structures (1, 2, 3) are laminated together in the single lamination process. 2. The method of claim 1, wherein the laminating step includes a first heating step at a first heating temperature, a second heating step at a second heating temperature higher than the first heating temperature, and then a cooling step , wherein the first heating temperature is set within a range of 120°C to 130°C and the second heating temperature is set within a range of 140°C to 150°C, and/or the first heating step is performed in a first laminator and the second heating step is performed in a separate second laminator. The method of claim 9, wherein the pressure is increased during the first heating step, further increased during the second heating step, and still further increased during the cooling step. A multi-layer chip card, comprising:
a core layer structure (2) having a front side and a back side, the core layer structure (2) comprising contact pads (20) provided on the front side, and further comprising an IC chip (10) and a conductor pattern, the IC chip (10) and the contact pads (20) being conductively connected to the conductor pattern and not overlapping when viewed from the front side towards the back side;
a surface layer structure (1) provided on the surface side of the core layer structure (2), the surface layer structure (1) having through holes (5) with a cross-sectional shape that corresponds substantially in size and position to the outer contours of the contact pads (20) provided on the surface side of the core layer structure (2);
a back layer structure (3) provided on the back side of the core layer structure (2);
- a label (50) provided between the back layer structure (3) and the core layer structure (2), in which, when viewed from the front side towards the back side, the label (50) and the contact pads (20) overlap completely or at least to a large extent. The multilayer chip card of claim 11, wherein the label (50) has an outer contour that substantially corresponds in size and position to the outer contour of the contact pads (20) provided on the obverse side of the core layer structure (2), and/or the label (50) is made of glycol-modified polyethylene terephthalate (PETG). A multilayer chip card according to claim 11 or 12, wherein the core layer structure (2) comprises a first layer (2.1) on which the IC chip (10) is mounted, and a second layer (2.2) having an opening (40) in which the IC chip (10) provided on the first layer (2.1) is accommodated. 12. The multilayer chip card according to claim 11, wherein the core layer structure (2) comprises an antenna (30) electrically connected to the IC chip (10) , the IC chip (10) and the contact pads (20) being arranged on a common substrate (2.1) , the IC chip (10) and the contact pads (20) being arranged on opposite sides of the common substrate (2.1). The multi-layer chip card of claim 11, wherein the IC chip (10) and the contact pads (20) are laterally spaced apart from each other.