JP7714163B2 - Hardware-aided software modem - Google Patents

Description

This invention relates to a hardware-aided software modem that implements modems used in mobile phones and other devices using software.

Historically, modems have evolved from the early 300 bps era for data communications in the late 1960s to 4,800 bps digital modems for fax machines in the 1970s, and into today's mobile phone era, where speeds have increased to hundreds of Mbps. 5G communications aim to further increase speeds to gigabits per second. Since the digital modem era, modem construction technology has often been based on dedicated LSIs as speeds have increased, but there are also software modems that are constructed using software. Software modems are inferior to dedicated LSIs in terms of processing speed, or communication speed as a modem's performance, but they have advantages such as lower price and the ability to incorporate application software that uses the modem into the modem software.

As in Reference 1, software modems are designed to consist of only a CPU and memory as hardware, with software processing methods such as interrupt processing devised. However, to increase speed, CPUs with multiple CPU cores are used, or special CPUs with a structure that allows parallel processing using many cores, such as GPUs (Graphics Processing Units), are used.

On the other hand, unrelated to modems, pipeline processing, which allows multiple instructions to be executed in parallel, has long been used to speed up computer processing, but this invention makes it possible to perform pipeline processing efficiently.

JP 2001-197128

Even software modems can achieve high speeds, achieving communication speeds of several hundred Mbps, comparable to 4G.

It can achieve communication speeds comparable to 4G, and can also be equipped with application software that uses the modem. It can be customized to suit a wide variety of customer needs, making it possible to build a system that is particularly suitable for local 5G applications.

Figure 1 shows the general configuration of a software modem. FIG. 2 shows the signal processing flow of a modem according to the present invention. FIG. 3 shows the hardware configuration of a software modem according to the present invention. FIG. 4 shows how the software processing of the macro circuit according to the present invention is pipelined. FIG. 5 shows an example where the processing times of the pipeline processes are not uniform.

Figure 1 shows a simplified view of the general configuration of a software modem, which has a CPU and memory like a personal computer, and along with an OS (operating system) that serves as the basic software that runs the computer, the modem software is installed in the memory as the computer's application software. The DAC/ADC in Figure 1 has the function of converting digital data resulting from computer processing into analog data and transmitting it, i.e., generating it as a modem output signal, and conversely, performing analog-to-digital conversion, converting modem input signals received as analog data into digital data for processing by the computer.

Today, CPU performance has improved by incorporating multiple cores, such as six, but modem speeds are limited to a few Mbps, which is the performance of 3G mobile phones. On the other hand, as seen in recent 4G (LTE) communications, we are now in an era where modem speeds of several hundred Mbps are required for video viewing.

Figure 2 shows the flow of signal processing (modem signal processing) in a mobile phone modem, with the transmitting side on the left and the receiving side on the right. On the transmitting side, user data is divided into frames at a specified length, and a redundant code for error detection called a CRC is added to each frame in the CRC adding unit 1 to detect errors that occur during communication, and the frame signal is formatted. The encoding unit 2 performs FEC (Forward Error Correction) to prevent transmission errors, and encodes the data using LDPC (Low Density Parity Check) code or turbo code.

The scrambling unit 3 randomizes the data to ensure uniform radio energy and improves the coding efficiency of the LDPC code (by preventing the creation of unusual patterns such as consecutive zeros). The modulation unit 4 then combines multiple bits from the scrambling unit output to form a symbol, and determines a two-dimensional coordinate point for QAM (quadrature amplitude modulation) for each symbol. In this invention, there are 64 coordinate points, and each symbol is 64QAM, consisting of 6 bits of data. The precoding unit 5 forms spatial channels that are orthogonal to each other for the multiple antennas used for MIMO (Multiple Input and Multiple Output) control, and performs weighting to appropriately control the transmission power allocated to each channel.

The resource element mapping unit 6 converts the precoding unit output data into multi-carrier data and performs frequency division multiplexing. The IFFT (Inverse Fast Fourier Transform) unit 7 converts the data sequence from frequency space to time space, and the DAC unit 8 converts the digital data to analog and transmits it as radio waves.

On the receiving side, the analog radio waves are first converted to digital by the ADC unit 17, the FFT (Fast Fourier Transform) unit 16 converts the data sequence from time space to frequency space, and the resource element demapping unit 15 extracts data of frequency components at specified positions from the frequency-division multiplexed signal.

The equalization processing unit 14 corrects for the time difference in the arrival of radio waves (the time difference between radio waves received directly between antennas and those reflected by obstacles such as mountains, multipath fading), and FFT and IFFT processing are also used here. The demodulation unit 13, descrambling unit 12, decoding unit 11, and CRC check unit 10 then perform signal processing in the reverse order to that performed on the transmitting side.

Table 1 shows an estimate of the amount of calculation required for each software processing element. To improve the speed (communication speed) of a software modem, it is important to incorporate elements that require a large amount of calculation into circuits (LSI). For this reason, it is effective to combine such operations - arithmetic operations such as addition, multiplication, and division, logical operations such as AND and OR, shift operations, and bit operations - and form a macro processing circuit, incorporating these into an LSI, along with basic circuits and sequence circuits that implement specific algorithms. The basic circuits mentioned above include logical operations such as AND and OR, shift operations, and bit operations, as well as temporary registers that temporarily store data during operations. A sequence circuit is a sequencer that executes algorithms to perform operations efficiently, and has the ability to issue instructions for operations (operation programs).

From Table 1, it is preferable to first select at least one of encoding and FFT/IFFT processing, which require a relatively large amount of calculations, as candidates for macro processing circuitization (LSI implementation). Processing with a medium amount of calculations, such as bit processing, scrambling, and modulation/demodulation, may be combined with processing with a small amount of calculations and implemented in an LSI (for example, combining bit processing and CRC processing). Processing with a small amount of calculations may be processed in software without being implemented in an LSI.

Figure 3 shows an example of the configuration of hardware (e.g., a hardware-aided software modem (described below) or a system-on-chip) according to the present invention. This configuration includes a processor 29, four macro processing circuits 21, 22, 23, and 24, each of which performs a portion of modem signal processing, and a memory 20 storing a program (modem software program) that causes the processor 29 to perform at least the remaining modem signal processing, excluding the processing performed by the four macro processing circuits 21, 22, 23, and 24. The encoding processing circuit 21 performs the processing of the encoding unit 2 and decoding unit 11 shown in Figure 2. Furthermore, the processing of the scrambling unit 3 and descrambling unit 12 shown in Figure 2, performed by the bit processing circuit 22, involves writing data horizontally and reading data vertically from memory. Because software processing by the processor 29 requires complex and time-consuming memory access, the horizontal-vertical conversion is implemented in hardware to reduce the time required.

The addition and check of the CRC shown in Figure 2 is also performed in this bit processing circuit. The modulation/demodulation processing circuit 23 performs the processing of the modulation and demodulation sections shown in Figure 2. The FFT/IFFT processing circuit (in this invention, the term "fast Fourier transform" is used to collectively refer to FFT and IFFT) 24 performs fast Fourier transform processing, which requires a high level of computing power. Control calculation cores 25, 26, 27, and 28 corresponding to each of the four macro processing circuits mentioned above are built into the processor 29. The processor 29 is equivalent to the CPU shown in Figure 1, and is commonly referred to by those skilled in the art as a microprocessor or CPU.

2, and also transmits (modulates, etc.) and receives (demodulates, etc.) radio waves. This analog front end 30 corresponds to the DAC/ADC in FIG. 1.
3, the processor 29, memory 20, and four macro processing circuits 21, 22, 23, and 24 are mounted on a single chip as an LSI. The analog front end 30 can also be accommodated on a single chip.

The four macro processing circuits 25, 26, 27, and 28 described above may work in cooperation with the control calculation cores 25, 26, 27, and 28 to perform pipeline processing as software. For example, if some of the calculations performed by each macro processing circuit are performed by the corresponding control calculation core, the calculation time can be shortened compared to when the macro processing circuit performs the calculation alone, and the pipeline processing time can be made uniform. The pipeline processing shown in Figure 4 is uniform, and there is no idle time (or waiting time), so processing is executed efficiently.

In addition, data can be stored and transferred for each processing unit in each macro processing circuit, and because the basic circuit of the macro processing circuit has a temporary register, it is no longer necessary to store and transfer data for each calculation, reducing the memory capacity required for storing and transferring intermediate data.

Note that Figure 5 shows an example where the times for each of the pipeline processing steps A, B, C, and D are not equal and are not uniform, making it difficult to utilize the characteristic of pipeline processing, which is the ability to process multiple instructions in parallel, and resulting in reduced processing efficiency. Memory 20 in Figure 3 contains programs such as modem software, protocol software for 5G communications, and customized software to meet customer requests.

In addition to the three pieces of software mentioned above, memory 20 also includes, although not shown, a program memory containing an operating system as basic software, a working memory for temporarily storing calculation data, and a flash memory for storing data that requires permanent storage.

The above-mentioned software implemented, in terms of the OSI seven-layer protocol defined by the ISO (International Organization for Standardization), comprises modem software as Layer 1 (physical layer), protocol software including MAC (Medium access Control), RLC (Radio Link Control), and PDCP (Packet Data Convergence Protocol) as Layer 2, RPC (Radio Resource Control) as Layer 3, and Layer 4 which executes Internet protocols. Furthermore, customized software is used in Layers 6 and 7 to transmit image data, sensor data, and perform various functions required by customer systems.

In an in-house wireless network system such as local 5G, a large number of sensor terminals, surveillance cameras, etc. are connected to the network, and a management center is typically connected that collects data received from the terminals and performs analysis and management of the data requested by the customer. Customized software performs the data transfer and analysis management functions required for this purpose.

The analysis management function not only centrally manages all sensor terminal information managed by the management sensor, but also determines the normality or abnormality of sensor information for each sensor terminal, manages sensor information chronologically, and queries other sensor terminals about their sensor sensitivity settings. This customization software allows for flexible response to customer systems.

A major feature of 5G mobile phones is their ability to transmit ultra-high-definition video in a short time at communication speeds of several gigabits per second. However, for local 5G, customers require communication speeds of several hundred Mbps, which is sufficient, and many prioritize customization features over speed, making this invention highly practical.

The modem of the present invention realizes many of its functions through software processing, but some functions are realized through a macro processing circuit, i.e., hardware, so it can be called a Hardware-Aided Software Modem.

In the example of Figure 3, four macro processing circuits (e.g., LSIs) are provided to perform some of the modem signal processing shown in Figure 2, but the number of macro processing circuits may be one or more. Also, in Figure 3, in order to equalize the processing time of pipeline processing, a configuration is adopted in which the control arithmetic core corresponding to each macro processing circuit assists the processing performed by that macro processing circuit, but each macro processing circuit may perform processing independently without assistance from the control arithmetic core. Also, in Figure 3, memory 20 is implemented with protocol software and customization software in addition to modem software, but software other than protocol software and customization software may also be implemented, and the implementation of protocol software and customization software may be omitted.

Because the software can execute modem functions capable of achieving communication speeds of several hundred megabps, it can be used not only as a modem for 4G mobile phones, but also in 5G mobile phone systems (especially local 5G), making it highly applicable to industrial applications.

1. CRC Addition Unit 2. Encoding Unit 3. Scrambling Unit 4. Modulation Unit 5. Precoding Unit 6. Resource Element Mapping Unit 7. IFFT Unit 8. DAC Unit 10. CRC Check Unit 11. Decoding Unit 12. Descrambling Unit 13. Demodulation Unit 14. Equalization Processing Unit 15. Resource Element Demapping Unit 16. FFT Unit 17. ADC Unit 20. Memory 21. Encoding Processing Circuit 22. Bit Processing Circuit 23. Modulation/Demodulation Processing Circuit 24. FFT/IFFT Processing Circuit 25. Control Calculation Core 1
26. Control calculation core 2
27. Control calculation core 3
28. Control calculation core 4
29. Processor 30. Analog Front End

Claims (2)

A hardware-aided software modem comprising a processor, a macro processing circuit that executes a part of modem signal processing , and a memory that stores a modem software program that causes the processor to execute at least the remaining part of the modem signal processing, excluding the part, wherein the processor is equipped with a control calculation core corresponding to the macro processing circuit . 2. The hardware-aided software modem according to claim 1, wherein the memory is installed with customized software for managing sensor data as a program to be executed by the processor.