JP7572685B2 - Etching Method - Google Patents

Description

The present disclosure relates to an etching method for a structure to be etched having multiple mixed crystal layers.

As one type of field effect transistor, for example, a high electron mobility transistor (HEMT) using a compound semiconductor material has been known. A HEMT uses a high-mobility two-dimensional electron gas (2DEG) resulting from a heterojunction as a channel. Patent Document 1 discloses an example of a HEMT. The HEMT disclosed in Patent Document 1 includes an AlGaN layer (electron supply layer) provided on an electron transit layer, an AlN layer (insulating layer) provided on the AlGaN layer, and a gate electrode provided on the AlN layer via a nitride semiconductor layer.

In addition to the high electron mobility transistor (HEMT) mentioned above, selective etching to form circuit patterns is extremely important for all devices, including CMOS transistors, PN diodes, JFETs (Junction Field Effect Transistors), and TFTs (Thin Film Transistors).

In the area of power devices, there have been many attempts to develop devices using wide band gap semiconductor materials that can be used to build high-efficiency devices with high voltage resistance that is not possible with silicon (Si). In recent years, research and development of power devices using such materials, silicon carbide (SiC) and gallium nitride (GaN), has been particularly active.

JP 2009-71061 A

In addition to the above silicon carbide (SiC) and gallium nitride (GaN), for example, in switching (power conversion) devices, gallium oxide-based power devices using Ga ₂ O ₃ material that can withstand a wider range of voltages than conventional materials including SiC and GaN are attracting attention. Gallium oxide-based power devices are expected to be compatible with a wide range of temperatures and voltages, including high temperatures and high voltages, and to be low-cost, highly efficient, and highly reliable. For this reason, a wide range of application fields are considered as application fields for Ga ₂ O ₃ -based power devices.

However, when considering the configuration of gallium oxide-based power devices, it is necessary to explore combinations of mixed crystal semiconductor layers (mixed crystal layers) that can form practical active layers. In addition, in order to configure power devices, it is necessary to develop technology that allows selective etching of each mixed crystal layer.

When considering device formation in general, the design of the active layer is extremely important. In the above-mentioned HEMTs, CMOS, PN diodes, and other devices, active layers are sometimes stacked to achieve high-performance devices, and the technology of selectively etching each layer to form a pattern plays a very important role.

There are two types of etching techniques: dry etching and wet etching. Dry etching has high etching directionality and produces a high aspect ratio in the etching pattern, but its mechanism raises concerns about damage to thin films and consumes a large amount of energy during operation.

On the other hand, wet etching has a worse aspect ratio than dry etching, but it is very simple and has low operating costs, and has a faster etching speed and better etching selectivity than dry etching.

Due to these advantages, wet etching is often used when forming displays, for example.

The present disclosure aims to solve the above problems and provide an etching method that can relatively easily obtain a desired structure for an etching target structure that includes multiple mixed crystal layers.

A first aspect of the etching method of the present disclosure includes: (a) obtaining a structure to be etched including first and second mixed crystal layers; and (b) performing at least one of a first etching process for selectively etching the first mixed crystal layer of the structure to be etched using a first etching agent and a second etching process for selectively etching the second mixed crystal layer of the structure to be etched using a second etching agent, wherein the first mixed crystal layer includes ( _{M1xGa1 -x} ) _2O3 (0 _< x≦1), the second mixed crystal layer includes ( _{M2yGa1 -y} ) _2O3 (0<y≦1), M1=Cr, and M2=one of {Al, In _, Fe}, the first mixed crystal layer has crystallinity when {x≠1}, and the second mixed crystal layer has crystallinity when {y≠1}.

A second aspect of the etching method of the present disclosure includes: (a) obtaining a structure to be etched including first and second mixed crystal layers and a silicon oxide layer; and (b) performing at least one of a first etching process for selectively etching the first mixed crystal layer of the structure to be etched using a first etching agent, a second etching process for selectively etching the second mixed crystal layer of the structure to be etched using a second etching agent, and a third etching process for selectively etching the silicon oxide layer of the structure to be etched using a third etching agent, wherein the first mixed crystal layer includes (M1 _x Ga _1-x ) ₂ O ₃ (0<x≦1), and the second mixed crystal layer includes (M2 _y Ga _1-y ) ₂ O _{3 .} (0<y≦1), M1=Cr, M2=one of {Al, In, Fe}, the first mixed crystal layer has crystallinity when {x≠1}, and the second mixed crystal layer has crystallinity when {y≠1}.

In the first aspect of the etching method of the present disclosure, by performing step (b), the first mixed crystal layer or the second mixed crystal layer can be selectively etched from the structure to be etched, so that the desired structure can be obtained with high accuracy from the structure to be etched by a relatively simple process.

In the second aspect of the etching method of the present disclosure, by performing step (b), the first mixed crystal layer, the second mixed crystal layer, or the silicon oxide film can be selectively etched from the structure to be etched, so that the desired structure can be obtained with high accuracy from the structure to be etched by a relatively simple process.

The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

1A to 1C are cross-sectional views showing a processing procedure of a first basic etching method in the first embodiment. 1A to 1C are cross-sectional views showing a processing procedure of a first basic etching method. 5A to 5C are cross-sectional views showing a processing procedure of a second basic etching method in the first embodiment. 10A to 10C are cross-sectional views showing a processing procedure of a second basic etching method. 11A to 11C are cross-sectional views showing a processing procedure of a third basic etching method in the second embodiment. 11A to 11C are cross-sectional views showing a processing procedure of a third basic etching method. 11A to 11C are cross-sectional views showing a processing procedure of a third basic etching method. 11A to 11C are cross-sectional views showing a processing procedure of a fourth basic etching method in the second embodiment. 11A to 11C are cross-sectional views showing a processing procedure of a fourth basic etching method. 11A to 11C are cross-sectional views showing a processing procedure of a fourth basic etching method. FIG. 2 is an explanatory diagram showing the characteristics of an etching agent in a table format. FIG. 2 is an explanatory diagram showing, in table form, the composition of an Al etching agent and a Cr etching agent. FIG. 11 is an explanatory diagram illustrating details of a third etching characteristic by a silicon oxide etchant in a graph form. FIG. 11 is an explanatory diagram illustrating details of a third etching characteristic by a silicon oxide etchant in a graph form. FIG. 11 is an explanatory diagram showing details of a second etching characteristic by an Al etchant in a graph form. FIG. 2 is an explanatory diagram showing details of a first etching characteristic by a Cr etchant in a graph form. 11A to 11C are cross-sectional views showing basic processing steps for obtaining a patterned structure in an etching method according to a third embodiment. 1A to 1C are cross-sectional views showing basic processing steps. 1A to 1C are cross-sectional views showing basic processing steps. FIG. 1 is an explanatory diagram showing an outline of a first thin film manufacturing technique for obtaining a chromium mixed crystal layer. FIG. 2 is an explanatory diagram showing an outline of a second thin film manufacturing technique for obtaining an aluminum mixed crystal layer. A cross-sectional view showing a mesa etching process step in embodiment 3. 1A-1C are cross-sectional views showing a mesa etching process. 1A-1C are cross-sectional views showing a mesa etching process. 1A-1C are cross-sectional views showing a mesa etching process. 1A-1C are cross-sectional views showing a mesa etching process. 1A-1C are cross-sectional views showing a mesa etching process. 1A-1C are cross-sectional views showing a mesa etching process. 13 is a cross-sectional view showing a second mask processing step in the third embodiment. FIG. 11 is a cross-sectional view showing a second mask processing step. FIG. 11 is a cross-sectional view showing a second mask processing step. FIG. 11 is a cross-sectional view showing a second mask processing step. FIG. 11 is a cross-sectional view showing a second mask processing step. FIG. 11 is a cross-sectional view showing a second mask processing step. FIG. FIG. 13 is a cross-sectional view showing a third mask processing step in the third embodiment. FIG. 11 is a cross-sectional view showing a third mask processing step. FIG. 11 is a cross-sectional view showing a third mask processing step. FIG. 11 is a cross-sectional view showing a third mask processing step. FIG. 11 is a cross-sectional view showing a third mask processing step. FIG. 2 is a plan view showing an example of a planar structure of an intermediate patterning structure. 13A to 13C are cross-sectional views showing a gate formation step in the third embodiment. 11A to 11C are cross-sectional views showing a gate forming step. 11A to 11C are cross-sectional views showing a gate forming step. 11A to 11C are cross-sectional views showing a gate forming step. 11A to 11C are cross-sectional views showing a gate forming step. 11A to 11C are cross-sectional views showing a gate forming step. 1A to 1C are cross-sectional views showing a method for forming an indium mixed crystal layer using a buffer layer. 1A to 1C are cross-sectional views showing a method for forming an indium mixed crystal layer using a buffer layer. 3A to 3C are cross-sectional views showing an outline of a manufacturing process for an iron mixed crystal layer.

<First embodiment>
The basic configuration and method of the present disclosure will be described.

First, gallium oxide crystals are polymorphic, with five types: α, β, γ, δ, and ε. The most stable material is the monoclinic β phase, but in this embodiment, the α phase is used as a representative. The reasons are as follows.

(1) α-Ga ₂ O ₃ has the same crystal structure as Al ₂ O ₃ , which is one of the general-purpose substrates (quartz, Si, sapphire), so epitaxial growth that promotes high-quality crystal growth is possible.
(2) There are many successful cases of producing mixed crystal films with corundum structure crystals.
(3) Thin films with the corundum structure can be formed into conductive films using elements such as V (vanadium) and In (indium), but they can also be used as insulators or semiconductors, as seen in elements such as Ga (gallium) and Al (aluminum), offering a wide range of options.
(4) It has been suggested that P-type and other types may also be possible.
For the reasons mentioned above, the α phase will be described as a representative example, but the same is also applicable to other phases.

Figures 1 and 2 are cross-sectional views showing the processing steps of the first basic etching method in the first embodiment of the present disclosure.

As shown in FIG. 1, the structure to be etched is a laminated structure 3 consisting of a chromium alloy layer 1 and an aluminum alloy layer 2 provided on the chromium alloy layer 1. The chromium alloy layer 1 corresponds to the "first alloy layer," and the aluminum alloy layer 2 corresponds to the "second alloy layer."

The chromium alloy layer 1 contains components that satisfy the following chemical formula (1), and the aluminum alloy layer 2 contains components that satisfy the following chemical formula (2). Furthermore, the chromium alloy layer 1 has crystallinity when {x≠1} in chemical formula (1), and the aluminum alloy layer 2 has crystallinity when {y≠1} in chemical formula (2).

Chromium mixed crystal layer 1...α-(Cr _x Ga _1-x ) ₂ O ₃ (where 0<x≦1)...(1)
Aluminum mixed crystal layer 2...α-( _{AlyGa1 -y} ) _2O3 (where 0 _< y≦1)...(2)

As shown in FIG. 1, the layers are stacked in the order of chromium alloy layer 1 → aluminum alloy layer 2 from the bottom up to produce the layered structure 3. That is, the chromium alloy layer 1 is formed on a specified substrate (not shown), and then the aluminum alloy layer 2 is formed on the chromium alloy layer 1 to obtain the layered structure 3. This layered structure 3 is the structure to be etched.

Next, a photoresist (not shown) is formed on the aluminum alloy layer 2 of the laminated structure 3 shown in FIG. 1, and then a patterned resist (not shown) is obtained by exposure processing.

Then, using the patterned resist as a mask, a second etching process is performed to selectively etch only the aluminum mixed crystal layer 2 using an Al etchant F2, which will be described in detail later. The Al etchant F2 corresponds to the "second etchant," and the etching process using the Al etchant F2 is the "second etching process."

As a result, as shown in FIG. 2, a patterned structure 13 can be obtained having an etched region R2 that penetrates a portion of the aluminum alloy layer 2 and exposes the surface of the chromium alloy layer 1. The patterned structure 13 includes a combination of the remaining laminated structure 3 other than the etched region R2 and a single layer structure consisting of only the chromium alloy layer 1 in the etched region R2.

That is, the patterning structure 13 shown in FIG. 2 includes a laminated structure 3 made of a chromium alloy layer 1 and an aluminum alloy layer 2, and a single-layer structure in which only the lower chromium alloy layer 1 is provided among the chromium alloy layer 1 and the aluminum alloy layer 2. In the patterning structure 13, the chromium alloy layer 1 and the aluminum alloy layer 2 are provided at different formation heights.

As a result, the laminated structure 3 remaining in the patterned structure 13 becomes the active layer (channel layer) that is the basis of the semiconductor device. For example, the chromium alloy layer 1 and the aluminum alloy layer 2 in the laminated structure 3 may become the basis of the electron generating layer and the electron passing layer of the HEMT.

Figures 3 and 4 are cross-sectional views showing the processing steps of the second basic etching method in the first embodiment of the present disclosure.

As shown in FIG. 3, the structure to be etched is a laminated structure 3B consisting of an aluminum alloy layer 2 and a chromium alloy layer 1 provided on the aluminum alloy layer 2. Below, the description of the same content as in the first basic etching method shown in FIG. 1 and FIG. 2 will be omitted as appropriate, and the characteristics of the second basic etching method will be mainly described.

As shown in FIG. 3, the aluminum alloy layer 2 is layered on the bottom, followed by the chromium alloy layer 1, to produce the laminated structure 3B. That is, the aluminum alloy layer 2 is formed on a specified substrate (not shown), and then the chromium alloy layer 1 is formed on the aluminum alloy layer 2 to obtain the laminated structure 3B.

Next, a photoresist (not shown) is formed on the chromium mixed crystal layer 1 of the laminated structure 3B shown in FIG. 3, and then a resist (not shown) that is patterned by exposure processing is provided.

Then, as shown in FIG. 4, a first etching process is performed using the patterned resist as a mask to selectively etch only the chromium mixed crystal layer 1 using a Cr etchant F1, which will be described in detail later. The Cr etchant F1 corresponds to the "first etchant," and the etching process using the Cr etchant F1 is the "first etching process."

As a result, as shown in FIG. 4, a patterned structure 13B can be obtained having an etched region R1 that penetrates a portion of the chromium alloy layer 1 and exposes the surface of the aluminum alloy layer 2. The patterned structure 13B includes a combination of the remaining laminated structure 3B other than the etched region R1 and a single-layer structure consisting of only the aluminum alloy layer 2 in the etched region R1.

That is, the patterned structure 13B shown in FIG. 4 includes a laminated structure 3B of the aluminum alloy layer 2 and the chromium alloy layer 1, and a single-layer structure in which only the lower aluminum alloy layer 2 is provided among the aluminum alloy layer 2 and the chromium alloy layer 1. In the patterned structure 13B, the aluminum alloy layer 2 and the chromium alloy layer 1 are provided at different formation heights.

As a result, the layered structure 3B remaining in the patterned structure 13B becomes the active layer (channel layer) that is the basis of the semiconductor device.

In addition, in each of the first and second basic etching methods described above, it is preferable to use a mist CVD device (not shown) as the thin film manufacturing device for forming the chromium alloy layer 1 and the aluminum alloy layer 2, respectively.

A mist CVD device generally has a mist generating section that generates multiple raw material mists by atomizing (turning into mist) multiple raw material solutions contained inside, a carrier gas inlet section into which a carrier gas for transporting the raw material mists is introduced, and a mist outlet section from which a mist flow containing the raw material mists in the carrier gas is delivered. Note that in addition to the CVD method, the layered structure 3 can also be obtained by the HVPE (Hydride Vapor Phase Epitaxy) method.

The patterned structure 13 (13B) obtained by the first (second) basic etching method described above has the following characteristics:

(1) It includes a laminated structure 3 (3B) made of a chromium alloy layer 1 and an aluminum alloy layer 2, and the chromium alloy layer 1 and the aluminum alloy layer 2 are formed to different heights.

(2) The final patterned structure 13 (13B) is a laminated structure 3 (3B) consisting of the chromium alloy layer 1 and the aluminum alloy layer 2.

(3) Of the chromium alloy layer 1 and the aluminum alloy layer 2, a single-layer structure exists in which only the lower alloy layer is formed.

The patterning structures 13 and 13B obtained by the first and second basic etching methods of the first embodiment can also be formed as intermediate layers of a semiconductor device, separated from the substrate, if necessary.

In addition, a predetermined thin film will be formed or a metal layer or the like will be connected to the etching region R2 shown in FIG. 2 and the etching region R1 shown in FIG. 4.

The first basic etching method of the first embodiment of the present disclosure performs a second etching process using an Al etchant F2, thereby selectively etching the aluminum alloy layer 2 from the stacked structure 3, which is the structure to be etched, using the chromium alloy layer 1 as an etching stopper.

Therefore, the desired patterning structure 13 can be obtained with high precision from the laminated structure 3 by the relatively simple first basic etching method.

Similarly, the second basic etching method of the first embodiment of the present disclosure performs a first etching process using Cr etchant F1, thereby selectively etching the chromium alloy layer 1 from the stacked structure 3B, which is the structure to be etched, using the aluminum alloy layer 2 as an etching stopper.

Therefore, the desired patterning structure 13B can be obtained with high precision from the laminated structure 3B by the relatively simple second basic etching method.

In addition, a semiconductor device having the patterning structure 13 shown in Figure 2 can be manufactured as follows.

By carrying out the first basic etching method using Al etching agent F2 with stacked structure 3 as the etching target structure, it is possible to selectively remove aluminum mixed crystal layer 2, which is the upper mixed crystal layer, by using chromium mixed crystal layer 1, which is the lower mixed crystal layer in stacked structure 3, as an etching stopper.

Therefore, by performing the relatively simple first basic etching method, the patterning structure 13 can be obtained with high precision.

Similarly, the semiconductor device having the patterning structure 13B shown in FIG. 4 can be manufactured with high accuracy by performing the second basic etching method using the Cr etching agent F1, in a relatively simple process.

In this way, we discovered a combination of Al and Cr that can be mixed with gallium oxide to form the active layer that is the basis of semiconductor devices.

<Embodiment 2>
5 to 7 are cross-sectional views showing a process procedure of the third basic etching method according to the second embodiment of the present disclosure.

As shown in FIG. 5, the structure to be etched is a laminated structure 4 consisting of a chromium alloy layer 1, an aluminum alloy layer 2 provided on the chromium alloy layer 1, and a silicon oxide layer 6 provided on the aluminum alloy layer 2. The chromium alloy layer 1 corresponds to the "first alloy layer," and the aluminum alloy layer 2 corresponds to the "second alloy layer."

Below, we will omit the explanation of the same contents as in the first embodiment shown in Figures 1 to 4 as appropriate, and will focus on the features of the second embodiment with reference to Figures 5 to 7.

As shown in FIG. 5, the layers are stacked in the order of chromium alloy layer 1, aluminum alloy layer 2, and silicon oxide layer 6 from the bottom up to produce the laminated structure 4. That is, the chromium alloy layer 1 is formed on a specified substrate (not shown), then the aluminum alloy layer 2 is formed on the chromium alloy layer 1, and then the silicon oxide layer 6 is formed on the aluminum alloy layer 2, thereby obtaining the laminated structure 4.

Next, a photoresist (first resist) (not shown) is formed on the silicon oxide layer 6 of the laminated structure 4 shown in FIG. 5, and then the first resist (not shown) is patterned by exposure processing.

Then, using the patterned first resist as a mask, a third etching process is performed to selectively etch only the silicon oxide layer 6 using a silicon oxide etchant F3, which will be described in detail later. The silicon oxide etchant F3 corresponds to the "third etchant," and the etching process using the silicon oxide etchant F3 is the "third etching process."

As a result, as shown in FIG. 6, an etching region R6 is obtained in which the silicon oxide layer 6 is penetrated and the surface of the aluminum alloy layer 2 is exposed.

Next, a photoresist (second resist) (not shown) is formed on the aluminum alloy layer 2 in the etching region R6 shown in FIG. 6, and then the second resist (not shown) is patterned by exposure processing.

Then, using the patterned second resist as a mask, an etching process is performed using an Al etchant F2 to selectively etch only the aluminum mixed crystal layer 2. The Al etchant F2 corresponds to the "second etchant," and the etching process using the Al etchant F2 is the "second etching process."

As a result, as shown in FIG. 7, a patterned structure 14 can be obtained in the etching region R6, which has an etching region R2 that penetrates a portion of the aluminum alloy layer 2 and exposes the surface of the chromium alloy layer 1.

The patterning structure 14 includes a triple-layered structure of the remaining chromium alloy layer 1, aluminum alloy layer 2, and silicon oxide layer 6 outside the etching region R6, a double-layered structure of the remaining chromium alloy layer 1 and aluminum alloy layer 2 outside the etching region R2 within the etching region R6, and a single-layered structure consisting of only the chromium alloy layer 1 in the etching region R2.

That is, the patterning structure 14 shown in FIG. 7 includes a laminated structure 4 (triple laminated structure) consisting of a chromium alloy layer 1, an aluminum alloy layer 2, and a silicon oxide layer 6, a double laminated structure consisting of two layers excluding the silicon oxide layer 6, which is the top layer of the laminated structure 4, and a single layer structure in which only the chromium alloy layer 1, which is the bottom layer of the laminated structure 4, is provided.

The chromium alloy layer 1, the aluminum alloy layer 2, and the silicon oxide layer 6 are formed at different heights.

As a result, the double-layered structure of the remaining chromium alloy layer 1 and aluminum alloy layer 2 in the patterning structure 14 becomes the active layer (channel layer) that is the basis of the semiconductor device.

Figures 8 to 10 are cross-sectional views showing the processing steps of the fourth basic etching method in the second embodiment of the present disclosure.

As shown in FIG. 8, the structure to be etched is a laminated structure 4B consisting of an aluminum alloy layer 2, a chromium alloy layer 1 provided on the aluminum alloy layer 2, and a silicon oxide layer 6 provided on the chromium alloy layer 1. Below, the description of the same content as in the third basic etching method shown in FIG. 5 to FIG. 7 will be omitted as appropriate, and the features of the fourth basic etching method will be mainly described with reference to FIG. 8 to FIG. 10.

As shown in FIG. 8, the layers are stacked in the order shown from the bottom up: aluminum alloy layer 2 → chromium alloy layer 1 → silicon oxide layer 6 to produce stacked structure 4B. That is, aluminum alloy layer 2 is formed on a specified substrate (not shown), then chromium alloy layer 1 is formed on aluminum alloy layer 2, and then silicon oxide layer 6 is formed on chromium alloy layer 1 to obtain stacked structure 4B.

Next, a photoresist (first resist) (not shown) is formed on the silicon oxide layer 6 of the laminated structure 4B shown in FIG. 8, and then the first resist (not shown) is patterned by exposure processing.

Then, using the patterned first resist as a mask, a third etching process is performed to selectively etch only the silicon oxide layer 6 using a silicon oxide etchant F3, which will be described in detail later.

As a result, as shown in FIG. 9, an etching region R6 is obtained in which the silicon oxide layer 6 is penetrated and the surface of the chromium mixed crystal layer 1 is exposed.

Next, a photoresist (second resist) (not shown) is formed on the chromium mixed crystal layer 1 in the etching region R6 shown in FIG. 9, and then the second resist (not shown) is patterned by exposure processing.

Then, using the patterned second resist as a mask, a first etching process is performed using Cr etchant F1 to selectively etch only the chromium mixed crystal layer 1.

As a result, as shown in FIG. 10, a patterned structure 14B can be obtained in the etching region R6, which has an etching region R1 that penetrates a portion of the chromium alloy layer 1 and exposes the surface of the aluminum alloy layer 2.

The patterning structure 14B includes a triple-layer structure of the remaining aluminum alloy layer 2, chromium alloy layer 1, and silicon oxide layer 6 outside the etching region R6, a double-layer structure of the aluminum alloy layer 2 and chromium alloy layer 1 outside the etching region R1 within the etching region R6, and a single-layer structure consisting of only the aluminum alloy layer 2 in the etching region R1.

That is, the patterning structure 14B shown in FIG. 10 includes a laminated structure 4B (triple laminated structure) made of an aluminum alloy layer 2, a chromium alloy layer 1, and a silicon oxide layer 6, a double laminated structure made of two layers excluding the silicon oxide layer 6, which is the top layer of the laminated structure 4B, and a single layer structure in which only the aluminum alloy layer 2, which is the bottom layer of the laminated structure 4B, is provided.

The aluminum alloy layer 2, the chromium alloy layer 1, and the silicon oxide layer 6 are formed at different heights.

The third basic etching method of the second embodiment of the present disclosure performs a third etching process using silicon oxide etchant F3, and can selectively etch the silicon oxide layer 6 from the stacked structure 4, which is the structure to be etched, using the aluminum alloy layer 2 as an etching stopper.

In the third basic etching method of the first embodiment of the present disclosure, after the third etching process, the second etching process using the Al etchant F2 is performed, whereby the aluminum alloy layer 2 can be selectively etched from the structure shown in FIG. 6, with the chromium alloy layer 1 acting as an etching stopper.

Therefore, the third basic etching method, which consists of the relatively simple processing steps shown in Figures 5 to 7, can accurately obtain the desired patterning structure 14 from the layered structure 4.

Similarly, the fourth basic etching method of the second embodiment of the present disclosure performs a third etching process using silicon oxide etchant F3, thereby selectively etching silicon oxide layer 6 from stacked structure 4B, which is the structure to be etched, using chromium mixed crystal layer 1 as an etching stopper.

In the fourth basic etching method of the present disclosure, after the third etching process, the first etching process is performed using the Cr etching agent F1, whereby the chromium alloy layer 1 can be selectively etched from the structure shown in FIG. 9, with the aluminum alloy layer 2 acting as an etching stopper.

Therefore, the desired patterning structure 14B can be obtained with high precision from the laminated structure 4B by the fourth basic etching method, which consists of the relatively simple processing steps shown in Figures 8 to 10.

In addition, a semiconductor device having the patterning structure 14 shown in FIG. 7 can be manufactured by a third basic etching method consisting of the relatively simple processing steps shown in FIG. 5 to FIG. 7.

Therefore, a semiconductor device having the patterning structure 14 shown in Figure 7 can be obtained relatively easily and with high precision.

Similarly, a semiconductor device having the patterning structure 14B shown in FIG. 10 can be manufactured by a third basic etching method consisting of the relatively simple processing steps shown in FIGS. 8 to 10.

Therefore, a semiconductor device having the patterning structure 14B shown in FIG. 10 can be obtained relatively easily and with high precision.

In this way, we discovered a combination of Al and Cr that can be mixed with gallium oxide to form the active layer that is the basis of semiconductor devices.

<Details of the etching agent>
11 is an explanatory diagram showing the characteristics of an etching agent in a table format, in which cases where etching is practically possible are indicated by "O" and cases where etching is not possible are indicated by "X".

11 shows a buffered hydrofluoric acid (BHF) solution as the silicon oxide etchant F3. A mixed solution of ultra-high purity hydrofluoric acid (HF) and ammonium fluoride solution (NH ₄ F) is generally used as the BHF solution. Of course, diluted and mixed HF may be used as the BHF solution.

Al etching solution is shown as Al etching agent F2, and Cr etching solution is shown as Cr etching agent F1. The Cr etching agent F1 and Al etching agent F2 are both shown to be used in a temperature environment of 135°C.

Furthermore, _SiOx is shown as the constituent material of the silicon oxide layer 6, the above-mentioned chemical formula (2) is shown as the constituent material of the aluminum mixed crystal layer 2, and the above-mentioned chemical formula (1) is shown as the constituent material of the chromium mixed crystal layer 1.

Figure 12 is an explanatory diagram showing the composition of Al etchant F2 and Cr etchant F1 in table format.

As shown in FIG. 12, the Al etchant F2 is an Al etching solution and contains HNO ₃ , CH ₃ COOH, H ₃ PO ₄ and H ₂ O as its components.

Specifically, the Al etchant F2 is a mixture of 5 to 15 weight percent _HNO3 , 5 to 15 weight percent _{CH3COOH ,} 60 to 80 weight percent _H3PO4 , and 10 to 20 weight percent _H2O , with the total weight percent adjusted to be 100%.

The second etching process using the Al etchant F2 is performed, for example, in a temperature environment of about 135°C.

As shown in FIG. 12, the Cr etching agent F1 is a Cr etching solution that contains (NH ₄ ) ₂ Ce(NO ₃ ) ₆ , HClO ₄ and H ₂ O as its components.

Specifically, 5 to 15% by weight of (NH ₄ ) ₂ Ce(NO ₃ ) ₆ , 60 to 80% by weight of HClO ₄ , and 10 to 20% by weight of H ₂ O are mixed together, with the total of the above three weight percentages being adjusted to be 100%.

The first etching process using Cr etching agent F1 is performed, for example, in a temperature environment of about 135°C.

As shown in FIG. 11, the chromium mixed crystal layer 1, which is formed to satisfy chemical formula (1), has a first etching characteristic in which, among the etching agents F1 to F3, it is etched only by the Cr etching agent F1, and is not etched by the Al etching agent F2 or the silicon oxide etching agent F3. The above-mentioned first etching characteristic can be applied not only to the chromium mixed crystal layer 1, but also to Cr oxide.

Furthermore, the aluminum alloy layer 2, which is configured to satisfy chemical formula (2), has a second etching characteristic in which it is etched only by the Al etchant F2 among the etchants F1 to F3, and is not etched by the Cr etchant F1 or the silicon oxide etchant F3. The above-mentioned second etching characteristic can be applied not only to the aluminum alloy layer 2, but also to Al oxide.

In addition, the silicon oxide layer 6 made of SiO _x has a third etching characteristic that it is etched only by the silicon oxide etchant F3 among the etchants F1 to F3, and is not etched by the Al etchant F2 and the Cr etchant F1. Generally, the specific composition of SiO _x is SiO ₂ .

(Silicon oxide etchant F3)
13 and 14 are explanatory diagrams showing in graph form the details of the third etching characteristic by the silicon oxide etchant F3.

In Figures 13 and 14, the horizontal axis indicates the etching time (unit: seconds (s)), and the vertical axis indicates the etching depth (unit: nm). Also, the etching rate (nm/s) is indicated as appropriate.

See the graph for the Al ₂ O ₃ system on the far left of Fig. 13. As shown by the etching characteristic L31, the sapphire substrate made of Al ₂ O ₃ is not etched by the silicon oxide etchant F3.

Al ₂ O ₃ corresponds to a layer in which the mixture ratio of Al and Ga in the AlGaO-based aluminum mixed crystal layer 2 satisfying the chemical formula (2) is (Al=100%, Ga=0%).

Next, let us look at the CrGaO-based graph, the second from the left in Figure 13. With regard to the mixture ratio of Cr and Ga in the CrGaO-based mixed crystal layer, the circle marks indicate a mixture ratio of (Cr = 42%, Ga = 58%), and the cross marks indicate a mixture ratio of (Cr = 100%, Ga = 0%).

As shown by the etching characteristic L32, the CrGaO-based chromium mixed crystal layer 1 that satisfies chemical formula (1) is not etched by the silicon oxide etchant F3.

Next, let us look at the third graph from the left in Figure 13 for the AlGaO system. With regard to the mixture ratio of Al and Ga in the second mixed crystal layer of the AlGaO system that satisfies chemical formula (2), the ▽ mark indicates a mixture ratio of (Al = 0%, Ga = 100%), and the ○ mark indicates a mixture ratio of (Al = 18%, Ga = 82%) (with Si added).

As shown by the etching characteristics L31 and L33 of _{the Al2O3} -based graph and the AlGaO-based graph, the aluminum mixed crystal layer 2 satisfying the above-mentioned chemical formula (2) is not etched by the silicon oxide etchant F3.

Next, let us look at the fourth graph from the left in Figure 13 for the InGaO system. With regard to the mixture ratio of In and Ga in the InGaO system mixed crystal layer, the circle marks indicate a mixture ratio of (In = 80%, Ga = 20%), and the cross marks indicate a mixture ratio of (In = 100%, Ga = 0%).

As shown in the InGaO-based etching characteristics L34 and L35, the indium mixed crystal layer 2X containing components that satisfy the following chemical formula (3) is not etched by the silicon oxide etchant F3.

Indium mixed crystal layer 2X: α-(In _y Ga _1-y ) ₂ O ₃ (where 0<y≦1) (3)

Next, let us refer to the fifth graph from the left in Figure 13 for the FeGaO system. With regard to the mixture ratio of Fe and Ga in the FeGaO system mixed crystal layer, the ◇ symbol indicates the mixture ratio of (Fe = 70%, Ga = 30%; (film formation temperature 335°C)), the □ symbol indicates the mixture ratio of (Fe = 70%, Ga = 30%; (film formation temperature 350°C)), and the △ symbol indicates the mixture ratio of (Fe = 100%, Ga = 0% (film formation temperature 350°C)).

As shown in the FeGaO-based etching characteristic L36, the iron alloy layer 2Y containing components that satisfy the following chemical formula (4) is not etched by the silicon oxide etchant F3.

Iron mixed crystal layer 2Y...α-(Fe _y Ga _1-y ) ₂ O ₃ (0<y≦1)...(4)

Next, the _SiO2 -based graphs in the rightmost part of Fig. 13 and Fig. 14 are referred to. Fig. 14 shows the details of the rightmost graph of Fig. 13. Note that the triangle marks indicate the first measured value, and the circles indicate the second measured value. Since the first etching of the silicon oxide layer 6 having the first thickness was completed in 10 seconds or less, the second etching of the silicon oxide layer 6 having the second thickness, which is thicker than the first thickness, was performed for confirmation, and the etching rate was measured.

As shown by the _SiOx -based etching characteristic L37, the silicon oxide layer 6 made of _SiOx , typically _SiO2 , is etched by the silicon oxide etchant F3.

In this way, from Figures 13 and 14, it can be recognized that the third etching characteristic for the chromium alloy layer 1, the aluminum alloy layer 2, and the silicon oxide layer 6 is correct for the silicon oxide etchant F3 shown in Figure 11.

Furthermore, it was recognized that the indium alloy layer 2X and the iron alloy layer 2Y, like the aluminum alloy layer 2, are not etched by the silicon oxide etching agent F3.

(Al Etching Agent F2)
FIG. 15 is an explanatory diagram showing in detail the second etching characteristic by the Al etchant F2 in a graph form.

In FIG. 15, the horizontal axis indicates the etching time (unit: seconds (s)), and the vertical axis indicates the etching depth (unit: nm). Also, the etching rate (nm/s) is indicated as appropriate.

Please refer to the graph of _{Al2O3 system} on the left side of Fig. _15. In the graph of _Al2O3 system, the mark _x indicates the case of the sapphire substrate, and the mark ◯ indicates the case of the _AlOx thin film. This AlOx thin film is a thin film formed by the mist CVD method.

As shown by the etching characteristic L11 in the graph of the _{Al2O3 system} , the sapphire substrate is not etched by the Al etchant F2.

On the other hand, as shown by the etching characteristic L12 in the graph of the Al ₂ O ₃ system, the AlO _x thin film is etched by the Al etchant F2.

The AlO _x thin film corresponds to a layer in which the mixture ratio of Al and Ga in the AlGaO-based aluminum mixed crystal layer 2 is (Al=100%, Ga=0%).

Next, let us refer to the CrGaO-based graph, the second from the left in Figure 15. With regard to the mixture ratio of Cr and Ga in the CrGaO-based chromium mixed crystal layer 1, the circle marks indicate a mixture ratio of (Cr = 32%, Ga = 68%), and the cross marks indicate a mixture ratio of (Cr = 100%, Ga = 0%).

As shown by the etching characteristic L13, the chromium mixed crystal layer 1 that satisfies chemical formula (1) is not etched by the Al etching agent F2.

Next, let us refer to the third graph from the left in Figure 15 for the AlGaO system. With regard to the mixture ratio of Al and Ga in the AlGaO system mixed crystal layer, the ▽ symbol indicates a mixture ratio of (Al = 0%, Ga = 100%), the △ symbol indicates a mixture ratio of (Al = 11%, Ga = 89%) (with Si added), the ◇ symbol indicates a mixture ratio of (Al = 12%, Ga = 88%) (with Si added), and the □ symbol indicates a mixture ratio of (Al = 25%, Ga = 75%) (with Si added).

As shown by the etching characteristics L12, L14 and L15 of the graphs of _{the Al2O3} system and the AlGaO system, the aluminum mixed crystal layer 2 satisfying the above-mentioned chemical formula (2) is etched by the Al etchant F2.

Next, let us refer to the fourth graph from the left in Figure 15 for the InGaO system. With regard to the mixture ratio of In and Ga in the InGaO system indium mixed crystal layer 2X, the circle and triangle marks indicate a mixture ratio of (In = 80%, Ga = 20%), and the cross mark indicates a mixture ratio of (In = 100%, Ga = 0%).

As shown in the InGaO-based etching characteristics L16 and L17, the indium mixed crystal layer 2X that satisfies chemical formula (3) is etched by the Al etching agent F2.

Next, let us refer to the fifth graph from the left in Figure 15 for the FeGaO system. With regard to the mixture ratio of Fe and Ga in the FeGaO system mixed crystal layer, the ◇ symbol indicates the mixture ratio of (Fe = 70%, Ga = 30%; (film formation temperature 335°C)), the □ symbol indicates the mixture ratio of (Fe = 70%, Ga = 30%; (film formation temperature 350°C)), and the ▽ symbol indicates the mixture ratio of (Fe = 100%, Ga = 0% (film formation temperature 400°C)).

As shown in the etching characteristics L18 and L19 of the FeGaO system, the iron alloy layer 2Y that satisfies chemical formula (4) is etched by the Al etching agent F2.

Next, reference is made to the _SiO2- based graph on the far right of FIG.

As shown by the _SiOx -based etching characteristic L20, the silicon oxide layer 6 made of _SiOx , such as _SiO2 , is not etched by the Al etchant F2.

In this way, from Figure 15, it can be recognized that the second etching characteristics for the chromium alloy layer 1, the aluminum alloy layer 2, and the silicon oxide layer 6 are correct for the Al etchant F2 shown in Figure 11.

However, in order to etch the AlO _x thin film corresponding to the aluminum mixed crystal layer 2 when {y=1} in the chemical formula (2) by the Al etching agent F2, it is preferable to form the AlO _x thin film by the mist method. Note that the mist method is not limited to the mist CVD method.

In addition, it was recognized that the indium alloy layer 2X and the iron alloy layer 2Y are etched in the same manner as the aluminum alloy layer 2 by the Al etching agent F2.

(Cr Etching Agent F1)
FIG. 16 is an explanatory diagram showing in a graph form the details of the first etching characteristic by the Cr etchant F1.

In FIG. 16, the horizontal axis indicates the etching time (unit: seconds (s)), and the vertical axis indicates the etching depth (unit: nm). Also, the etching rate (nm/s) is indicated as appropriate.

See the graph for the Al ₂ O ₃ system on the far left of Fig. 16. As shown by the etching characteristic L21, the sapphire substrate made of Al ₂ O ₃ is not etched by the Cr etching agent F1.

Next, let us refer to the CrGaO-based graph, the second from the left in Figure 16. With regard to the mixture ratio of Cr and Ga in the CrGaO-based mixed crystal layer, the △ mark indicates a mixture ratio of (Cr = 20%, Ga = 80%), the □ mark indicates a mixture ratio of (Cr = 32%, Ga = 68%), and the × mark indicates a mixture ratio of (Cr = 100%, Ga = 0%).

As shown by the etching characteristics L22 and L23, the chromium mixed crystal layer 1 that satisfies chemical formula (1) is etched by the Cr etching agent F1.

Next, let us refer to the third graph from the left in Figure 16 for the AlGaO system. Regarding the mixture ratio of Al and Ga in the AlGaO system mixed crystal layer, the ▽ symbol indicates a mixture ratio of (Al = 0%, Ga = 100%), and the ◇ symbol indicates a mixture ratio of (Al = 12%, Ga = 88%) (with Si added).

As shown by the etching characteristics L21 and L24 in the graphs of _{the Al2O3} system and the AlGaO system, the aluminum mixed crystal layer 2 satisfying the above-mentioned chemical formula (2) is not etched by the Cr etchant F1.

Next, let us look at the fourth graph from the left in Figure 16 for the InGaO system. With regard to the mixture ratio of In and Ga in the InGaO system mixed crystal layer, the circle marks indicate a mixture ratio of (In = 80%, Ga = 20%), and the cross marks indicate a mixture ratio of (In = 100%, Ga = 0%).

As shown in the InGaO-based etching characteristic L25, the indium mixed crystal layer 2X that satisfies chemical formula (3) is not etched by the Cr etching agent F1.

Next, let us refer to the fifth graph from the left in Figure 16 for the FeGaO system. With regard to the mixture ratio of Fe and Ga in the FeGaO system mixed crystal layer, the ◇ symbol indicates the mixture ratio of (Fe = 70%, Ga = 30%; (film formation temperature 335°C)), the □ symbol indicates the mixture ratio of (Fe = 70%, Ga = 30%; (film formation temperature 350°C)), and the ▽ symbol indicates the mixture ratio of (Fe = 100%, Ga = 0% (film formation temperature 400°C)).

As shown in the FeGaO-based etching characteristic L26, the iron mixed crystal layer 2Y that satisfies chemical formula (4) is not etched by the Cr etching agent F1.

Next, refer to the _SiO2 -based graph on the far right of Fig. 16. As shown by _{the SiOx} -based etching characteristic L27, the silicon oxide layer 6 made of _SiOx , such as _SiO2 , is not etched by the Cr etching agent F1.

In this way, from Figure 16, it can be recognized that the first etching characteristics for the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6 are correct for the Cr etching agent F1 shown in Figure 11.

Furthermore, it was recognized that the indium alloy layer 2X and the iron alloy layer 2Y are not etched by the Cr etching agent F1, just like the aluminum alloy layer 2.

<Summary and Effects of First and Second Embodiments>
From the facts shown in FIGS. 11 to 16, the first and second etching methods of the first embodiment can be summarized as follows.

The etching method of the first embodiment performs the following steps (a) and (b).

Step (a) is a step of obtaining an etching target structure including first and second mixed crystal layers.

Step (b) is a step of performing at least one of a first etching process for selectively etching the first mixed crystal layer of the etching target structure using a Cr etching agent F1, and a second etching process for selectively etching the second mixed crystal layer of the etching target structure using an Al etching agent F2.

The first mixed crystal layer contains components that satisfy the following chemical formula (5), and the second mixed crystal layer contains components that satisfy the following chemical formula (6).

(M1 _x Ga _1-x ) ₂ O ₃ (0<x≦1)…(5)
(M2 _y Ga _1-y ) ₂ O ₃ (0<y≦1)…(6)
In the chemical formula (5), M1=Cr, and in the chemical formula (6), M2=one of {Al, In, Fe}.

Furthermore, the first mixed crystal layer satisfying chemical formula (5) has crystallinity when {x≠1}, and the second mixed crystal layer satisfying chemical formula (6) has crystallinity when {y≠1}.

The etching method of embodiment 1 can selectively etch the first mixed crystal layer or the second mixed crystal layer from the structure to be etched by performing step (b) above, so that the desired structure can be obtained from the structure to be etched relatively easily.

In addition, by performing step (b) above, the semiconductor device having the patterning structure 13 (13B) shown in FIG. 2 (FIG. 4) can selectively remove the upper mixed crystal layer of the first and second mixed crystal layers by using the lower mixed crystal layer as an etching stopper.

Therefore, the patterning structure 13 (13B) of the semiconductor device manufactured in the first embodiment can be obtained with high accuracy by performing the relatively simple etching method of the first embodiment.

Furthermore, based on the facts shown in Figures 11 to 16, the third and fourth etching methods of embodiment 2 can be summarized as follows:

The etching method of the second embodiment performs the following steps (a) and (b).

Step (a) is a step of obtaining an etching target structure including first and second mixed crystal layers and a silicon oxide layer.

Step (b) is a step of performing at least one of a first etching process for selectively etching a first mixed crystal layer of the etching target structure using a first etching agent, a second etching process for selectively etching a second mixed crystal layer of the etching target structure using a second etching agent, and a third etching process for selectively etching a silicon oxide layer of the etching target structure using a third etching agent.

The constituent components of the first and second mixed crystal layers are the same as those in the embodiment 1. The silicon oxide layer is made of _SiOx .

The etching method of the second embodiment can selectively etch the first mixed crystal layer, the second mixed crystal layer, or the silicon oxide film from the structure to be etched by performing step (b) above, so that the desired structure can be obtained from the structure to be etched relatively easily.

In addition, in the semiconductor device having the patterning structure 14 (14B) shown in FIG. 7 (FIG. 10), by performing the third etching process included in the above step (b), the uppermost layer of the first and second mixed crystal layers and the silicon oxide layer can be selectively removed using the intermediate layer as an etching stopper.

Furthermore, as in embodiment 2, by performing the first etching process or the second etching process following the third etching process, the intermediate layer can be selectively removed using the first and second mixed crystal layers and the lowest layer of the silicon oxide layer as an etching stopper.

Therefore, the patterning structure 14 (14B) of the semiconductor device manufactured in the second embodiment can be obtained with high accuracy by performing the relatively simple etching method of the second embodiment.

In addition, in the second embodiment, a buffered hydrofluoric acid solution (BHF solution) is used as the silicon oxide etchant F3, so that the silicon oxide film can be selectively removed from the structure to be etched, which is the stacked structure 4 in the second embodiment.

Furthermore, as the Al etchant F2 in the first and second embodiments, an etching solution containing 5 to 15 weight % _HNO3 , 5 to 15 weight % _{CH3COOH , 60 to 80 weight % H3PO4, and 10 to 20 weight % H2O is used} .

In this way, by using an etching solution mixed in the above-mentioned ratio as the Al etchant F2, the aluminum mixed crystal layer 2 can be selectively removed from the structure to be etched, which is the laminate structure 3 of embodiment 1 or the laminate structure 4 of embodiment 2.

In addition, as the Cr etching agent F1 in the first and second embodiments, an etching solution containing 5 to 15 weight percent (NH ₄ ) ₂ Ce(NO ₃ ) ₆ , 60 to 80 weight percent HClO ₄ , and 10 to 20 weight percent H ₂ O is used.

In this way, by using an etching solution mixed in the above-mentioned ratio as the Cr etching agent F1, the chromium mixed crystal layer 1 can be selectively removed from the etching target structure, which is the laminate structure 3 (3B) of embodiment 1 or the laminate structure 4 (4B) of embodiment 2.

Regarding the effects of the above-mentioned etching agents F1 to F3, the same effects can be obtained by replacing the aluminum alloy layer 2 with an indium alloy layer 2X or an iron alloy layer 2Y.

When the chromium mixed crystal layer 1 has {x ≠ 1} in chemical formula (5), if it has crystallinity, it is estimated that it will exhibit the etching characteristics shown in Figures 13, 15, and 16, regardless of the ratio with Ga.

Similarly, it is presumed that the aluminum alloy layer 2, the indium alloy layer 2X, and the iron alloy layer 2Y, when {y ≠ 1} in chemical formula (6), will exhibit the etching characteristics shown in Figures 13, 15, and 16 if they have crystallinity, regardless of the ratio with Ga.

This is because, if it is confirmed that a mixed crystal layer in which elements E1 and E2 are mixed at a predetermined mixing ratio has a predetermined etching characteristic with respect to etching agent W, it can be inferred that the above-mentioned predetermined etching characteristic with respect to etching agent W will be the same even if the mixed crystal layer in which elements E1 and E2 are mixed at a ratio other than the predetermined ratio. However, the mixed crystal layer must have crystallinity, that is, be single crystal or polycrystalline.

In addition, in the case of layers that do not contain Ga, such as AlO _x , i.e., layers where x = 1 in chemical formulas (1) and (5) and layers where "y = 1" in chemical formulas (2) to (4) and (6), it is not necessary for them to be crystalline and they may be amorphous.

Conversely, the first mixed crystal layer including the chromium mixed crystal layer 1 that satisfies chemical formula (5) must have crystallinity when {x ≠ 1}. Similarly, the second mixed crystal layer including the aluminum mixed crystal layer 2, the indium mixed crystal layer 2X, and the iron mixed crystal layer 2Y, each of which satisfies chemical formula (6), must have crystallinity when {y ≠ 1}.

In addition, in the first and second embodiments, the first etching process using the Cr etchant F1, the second etching process using the Al etchant F2, and the third etching process using the silicon oxide etchant F3 are all wet etching.

<Third embodiment>
In the third embodiment, the etching method disclosed in the second embodiment is developed to manufacture a HEMT (High Electron Mobility Transistor) using a combination of first and second mixed crystal layers and a selective etching technique.

Figures 17 to 19 are cross-sectional views showing the basic processing steps for obtaining the laminated structure 4 in the third embodiment. Figure 20 is an explanatory diagram showing an outline of the first thin film manufacturing technique for obtaining the chromium alloy layer 1, and Figure 21 is an explanatory diagram showing an outline of the second thin film manufacturing technique for obtaining the aluminum alloy layer 2. Below, the basic processing steps will be explained with reference to each of Figures 17 to 21.

First, as shown in FIG. 17, a CrGaO-based chromium mixed crystal layer 1 is formed on a sapphire substrate 8 by mist CVD. The sapphire substrate 8 is a C-plane sapphire substrate.

As shown in FIG. 20, a Cr mist can be obtained by placing a Cr solution in the Cr chamber C1 and applying ultrasonic vibration to the Cr chamber C1. A Ga solution can be placed in the Ga chamber C2 and applying ultrasonic vibration to the Ga chamber C2, thereby obtaining a Ga mist. Then, the Cr mist obtained from the Cr chamber C1 and the Ga mist obtained from the Ga chamber C2 are mixed on the surface of the sapphire substrate 8, thereby forming a chromium mixed crystal layer 1 on the sapphire substrate 8.

Next, as shown in FIG. 18, an AlGaO-based aluminum alloy layer 2 is formed on the chromium alloy layer 1 by mist CVD.

As shown in FIG. 21, an Al mist can be obtained by storing an Al solution in the Al chamber C3 and applying ultrasonic vibration to the Ga chamber C2. A Ga solution can be stored in the Ga chamber C4 and applying ultrasonic vibration to the Ga chamber C4, thereby obtaining a Ga mist. Then, the Al mist obtained from the Al chamber C3 and the Ga mist obtained from the Ga chamber C4 are mixed on the surface of the chromium alloy layer 1, thereby forming an aluminum alloy layer 2 on the chromium alloy layer 1.

As shown in FIG. 18, when the aluminum alloy layer 2 is formed, a high-mobility two-dimensional electron gas (2DEG) due to the heterojunction can be generated near the interface between the chromium alloy layer 1 and the aluminum alloy layer 2. Therefore, it is possible to realize an active layer that generates 2DEG by using a stacked structure of the chromium alloy layer 1 and the aluminum alloy layer 2.

Then, as shown in FIG. 19, a silicon oxide layer 6 is formed on the aluminum alloy layer 2 by plasma CVD. As the plasma CVD method, a PECVD (plasma-enhanced chemical vapor deposition) method using TEOS as a raw material is adopted.

As a result, a layered structure 4 can be obtained in which a chromium alloy layer 1, an aluminum alloy layer 2, and a silicon oxide layer 6 are layered in this order on a sapphire substrate 8.

Figures 22 to 28 are cross-sectional views showing the mesa etching process (first mask processing process) in embodiment 3. The mesa etching process will be described below with reference to Figures 22 to 28.

After obtaining the layered structure 4 shown in FIG. 19, a photoresist 9 is applied onto the silicon oxide layer 6 using a spin coating method, as shown in FIG. 22.

Then, as shown in FIG. 23, ultraviolet light 10 is selectively irradiated from above the photoresist 9. The area of the photoresist 9 that is exposed to the ultraviolet light 10 becomes the ultraviolet light irradiated area.

Next, as shown in FIG. 24, the ultraviolet irradiated areas of the photoresist 9 are removed to pattern the photoresist 9.

Then, as shown in FIG. 25, a third etching process is performed to etch the silicon oxide layer 6 using the patterned photoresist 9 as a mask (first mask) and silicon oxide etchant F3.

At this time, since the aluminum alloy layer 2 directly below the silicon oxide layer 6 functions as an etching stopper against the silicon oxide etchant F3, only the silicon oxide layer 6 can be selectively removed by the third etching process. As a result, a patterned silicon oxide layer 6 can be obtained.

Then, acetone 12 is irradiated onto the entire surface of the photoresist 9, and then, as shown in FIG. 26, all of the photoresist 9 irradiated with acetone 12 is removed.

Next, as shown in FIG. 27, a second etching process is performed to etch the aluminum alloy layer 2 using the patterned silicon oxide layer 6 as a mask and an Al etchant F2. The second etching process is performed in a temperature environment of 135°C.

At this time, the chromium alloy layer 1 directly below the aluminum alloy layer 2 functions as an etching stopper against the Al etchant F2, so that only the aluminum alloy layer 2 can be selectively removed by the second etching process.

As a result, after the second etching process is performed, a patterned aluminum alloy layer 2 can be obtained. The second etching process can be performed simply without forming a photoresist. In addition, the silicon oxide layer 6 on the aluminum alloy layer 2 is not etched away by the second etching process.

Finally, as shown in FIG. 28, a first etching process is performed to etch the chromium mixed crystal layer 1 using the patterned silicon oxide layer 6 as a mask and Cr etching agent F1. The first etching process is performed in a temperature environment of 135°C. The first etching process may also be performed in a temperature environment of about 65°C.

At this time, the sapphire substrate 8 directly below the chromium mixed crystal layer 1 functions as an etching stopper against the Cr etchant F1, so that only the chromium mixed crystal layer 1 can be selectively removed by the first etching process. Furthermore, the aluminum mixed crystal layer 2 and silicon oxide layer 6 on the chromium mixed crystal layer 1 are not etched away by the Cr etchant F1 either.

As a result, after the first etching process is performed, a patterned chromium alloy layer 1 can be obtained. The first etching process can be performed simply without forming a photoresist. In addition, the aluminum alloy layer 2 and silicon oxide layer 6 on the chromium alloy layer 1 are not etched away by the first etching process.

It has also been confirmed that the temperature range for the first etching process can be between 65°C and 135°C, which is above 50°C, allowing for production with enhanced etching selectivity.

In this way, the intermediate patterning structure 34A can be obtained with high accuracy from the layered structure 4 by the mesa etching process. The intermediate patterning structure 34A has a layered structure of a chromium alloy layer 1, an aluminum alloy layer 2, and a silicon oxide layer 6.

(Second mask step)
29 to 34 are cross-sectional views showing the second mask processing step in the embodiment 3. The second mask processing step will be described below with reference to FIGS.

First, as shown in FIG. 29, photoresist 15 is applied by spin coating to cover the entire surface of the sapphire substrate 8 including the intermediate patterning structure 34A shown in FIG. 28.

Then, as shown in FIG. 30, ultraviolet light 16 is selectively irradiated from above the photoresist 15. The area of the photoresist 15 that is exposed to the ultraviolet light 16 becomes the ultraviolet light irradiated area.

Next, as shown in FIG. 31, the ultraviolet irradiated areas of the photoresist 15 are removed, and the photoresist 15 is patterned. The patterned photoresist 15 becomes the second mask.

Then, as shown in Figures 31 and 32, a third etching process is performed to etch the silicon oxide layer 6 using the patterned photoresist 15 as a mask and silicon oxide etchant F3.

At this time, since the aluminum alloy layer 2 directly below the silicon oxide layer 6 functions as an etching stopper against the silicon oxide etchant F3, only the silicon oxide layer 6 can be selectively removed by the third etching process. As a result, a patterned silicon oxide layer 6 can be obtained.

Then, acetone 12 is irradiated onto the entire surface of the photoresist 15, and then, as shown in FIG. 33, all of the photoresist 9 irradiated with acetone 12 is removed.

Next, as shown in FIG. 34, a second etching process is performed to etch the aluminum alloy layer 2 using the patterned silicon oxide layer 6 as a mask and an Al etchant F2.

At this time, the chromium alloy layer 1 directly below the aluminum alloy layer 2 functions as an etching stopper against the Al etchant F2, so that only the aluminum alloy layer 2 can be selectively removed by the second etching process. As a result, a patterned aluminum alloy layer 2 can be obtained.

In this way, the second mask processing step allows intermediate patterning structure 34B to be obtained with high accuracy from intermediate patterning structure 34A. Intermediate patterning structure 34B has a layered structure of chromium alloy layer 1, aluminum alloy layer 2, and silicon oxide layer 6.

Figures 35 to 39 are cross-sectional views showing the third mask processing step in embodiment 3. The third mask processing step will be described below with reference to Figures 35 to 39.

First, as shown in FIG. 35, photoresist 17 is applied by spin coating to cover the entire surface of the sapphire substrate 8 including the intermediate patterning structure 34B shown in FIG. 34.

Then, as shown in FIG. 36, ultraviolet light 18 is selectively irradiated from above the photoresist 17. The area of the photoresist 17 that is exposed to the ultraviolet light 18 becomes the ultraviolet light irradiated area.

Next, as shown in FIG. 37, the ultraviolet irradiated areas of the photoresist 17 are removed, and the photoresist 17 is patterned. As a result, through holes 57 are formed on the sides of the aluminum alloy layer 2 and the silicon oxide layer 6. The patterned photoresist 17 becomes a third mask.

After that, as shown in FIG. 38, a Ti metal layer 22 is formed by sputtering, and then an Au metal layer 23 is formed on the Ti metal layer 22 by thermal evaporation. As a result, a metal laminate structure 31 is obtained in which the Ti metal layer 22 and the Au metal layer 23 are laminated in this order. The metal laminate structure 31 is also formed inside the through-hole 57.

Finally, as shown in FIG. 39, a lift-off process is performed to leave a pair of metal laminate structures 31 adjacent to the aluminum alloy layer 2 and the silicon oxide layer 6 on the chromium alloy layer 1. One of the pair of metal laminate structures 31 functions as a source electrode, and the other functions as a drain electrode.

In this way, the intermediate patterning structure 34C can be obtained with high accuracy from the intermediate patterning structure 34B by the third mask processing step. The intermediate patterning structure 34B includes a layered structure of a chromium alloy layer 1, an aluminum alloy layer 2, and a silicon oxide layer 6, and a pair of metal layered structures 31.

The pair of metal laminate structures 31 are formed directly on the surface of the chromium alloy layer 1. This structure was made possible by discovering an Al etchant F2 that can selectively etch only the aluminum alloy layer 2 of the laminate structure that includes the chromium alloy layer 1 and the aluminum alloy layer 2.

Figure 40 is a plan view showing an example of the planar structure of intermediate patterning structure 34B. In this figure, the metal laminate structure 31 is omitted. As shown in this figure, a pair of metal laminate structures 31 (not shown) is formed on two chromium alloy layers 1 selectively and separately formed in circular regions of a sapphire substrate 8. Note that an aluminum alloy layer 2 is formed directly below the silicon oxide layer 6 in Figure 39.

Figures 41 to 46 are cross-sectional views showing the gate formation process in embodiment 3. The gate formation process will be described below with reference to Figures 41 to 46.

First, as shown in FIG. 41, a photoresist 19 is applied by spin coating to cover the entire surface of the sapphire substrate 8 including the intermediate patterning structure 34C shown in FIG. 39.

Then, as shown in FIG. 42, ultraviolet light 20 is selectively irradiated from above the photoresist 19. The area of the photoresist 19 that is exposed to the ultraviolet light 20 becomes the ultraviolet light irradiated area.

Next, as shown in FIG. 43, the ultraviolet irradiated areas of the photoresist 19 are removed, and the photoresist 19 is patterned. As a result, a part of the surface of the silicon oxide layer 6 is exposed, and a through hole 59 is formed in the silicon oxide layer 6.

Then, as shown in FIG. 44, a third etching process is performed to etch the silicon oxide layer 6 using the patterned photoresist 19 as a mask and silicon oxide etchant F3.

At this time, since the aluminum alloy layer 2 directly below the silicon oxide layer 6 functions as an etching stopper against the silicon oxide etchant F3, only the silicon oxide layer 6 can be selectively removed by the third etching process. As a result, a patterned silicon oxide layer 6 having through holes 60 extending from the through holes 59 can be obtained.

After that, as shown in FIG. 45, a Ti electrode layer 25 is formed by sputtering, and then an Au electrode layer 26 is formed on the Ti electrode layer 25 by thermal evaporation. As a result, a metal laminate structure 32 is obtained in which the Ti electrode layer 25 and the Au electrode layer 26 are laminated in this order. The metal laminate structure 32 is also formed inside the through-hole 60.

Finally, as shown in FIG. 46, a lift-off process is performed, leaving only the metal laminate structure 32 on the silicon oxide layer 6. The remaining metal laminate structure 32 functions as the gate electrode.

In this way, the gate formation process allows the HEMT final structure 35 to be obtained from the intermediate patterning structure 34C. The HEMT final structure 35 includes a stacked structure of a chromium alloy layer 1, an aluminum alloy layer 2, and a silicon oxide layer 6, a pair of metal stacked structures 32, and one metal stacked structure 32.

<Specific manufacturing details>
Hereinafter, a detailed description will be given of the manufacturing methods of the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, the indium mixed crystal layer 2X, the iron mixed crystal layer 2Y, and the silicon oxide layer 6 shown in the first to third embodiments. Note that the following content is merely an example, and it goes without saying that the manufacturing methods are not limited to these.

(Chromium mixed crystal layer 1)...Thickness: about 500 nm "Chromium-based film-forming material"
Raw material solution: Ammonium dychronite ((NH ₄ ) ₂ Cr ₂ O ₇ ) solution Solvent: Pure water: Hydrochloric acid (99.5:0.5) mixed solvent Solute concentration: 0.040 mol/L

"Gallium-based film forming materials"
Raw material solution: Gallium acetylacetonate solution Solvent: Pure water: Hydrochloric acid (99.5:0.5) mixed solvent Solute concentration: 0.020 mol/L

(Aluminum mixed crystal layer 2)...film thickness about 300 nm "Aluminum-based film-forming material"
Raw material solution: Aluminum acetylacetonate solution Solvent: Pure water: Hydrochloric acid (99.5:0.5) mixed solvent Solute concentration: 0.040 mol/L

"Gallium-based film forming materials"
Same as chromium mixed crystal layer

(Indium mixed crystal layer 2X)
"Indium-based film forming materials"
Raw material solution: _{In2O3 solution} Solvent: Pure water Solute concentration: 0.050 mol/L

"Gallium-based film forming materials"
Same as chromium mixed crystal layer

(Iron mixed crystal layer 2Y)
"Iron-based film forming materials"
Raw material solution: Fecl _{3.6H 2} O solution Solvent...pure water Solute concentration: 0.1 mol/L

"Gallium-based film forming materials"
Raw material solution: GaCl ₃ aqueous solution Solvent: Pure water Solute concentration: 0.1 mol/L

"Auxiliary materials"
Raw material solution: Ammonia water (NH ₃ aq)
Solvent: Pure water

(Common Items)
"Gas type"
Carrier gas: Nitrogen gas Dilution gas: Nitrogen gas

"Sapphire substrate 8"
Material: C-face sapphire substrate Heating temperature: 400°C

"Mist generating means"
Ultrasonic transducer: 2.4MHz, 24V, 0.625A, 3 pieces used

(Silicon oxide layer 6)
Film thickness: about 300 nm

＜Other＞
In the first to third embodiments, the same effect can be obtained by using the indium alloy layer 2X or the iron alloy layer 2Y instead of the aluminum alloy layer 2. This is because the aluminum alloy layer 2, the indium alloy layer 2X, and the iron alloy layer 2Y have a common second etching characteristic as the second alloy layer satisfying the chemical formula (6).

When forming the indium alloy layer 2X, it is preferable to form a buffer layer. Figures 47 and 48 are cross-sectional views showing a method for forming the indium alloy layer 2X using a buffer layer.

As shown in FIG. 47, a buffer layer 41 is formed on a substrate 40 such as a sapphire substrate 8. Then, as shown in FIG. 48, an indium mixed crystal layer 2X is formed on the buffer layer 41.

Furthermore, when forming the iron mixed crystal layer 2Y, as described above, it is desirable to use _NH3 mist (ammonia mist) obtained by turning an ammonia solution into a mist as an auxiliary material in addition to the gallium-based film-forming material and the iron-based film-forming material.

Figure 49 is an explanatory diagram that shows a schematic outline of the manufacturing process for the iron alloy layer 2Y. Figure 49 shows the manufacturing process for the iron alloy layer 2Y on a substrate 40 such as a sapphire substrate 8. The iron alloy layer 2Y is manufactured by the following steps (1) to (4).

(1) obtaining an Fe mist M1;
(2) obtaining Ga mist M2;
(3) obtaining _NH3 mist M3;
(4) A step of supplying the Fe mist M1, the Ga mist M2, and the _NH3 mist M3 obtained in steps (1) to (3) onto the substrate 40 to form an iron mixed crystal layer 2Y on the substrate 40.

The _NH3 mist M3 in step (3) can be obtained by turning the ammonia solution, which is the "auxiliary material" described above, into a mist.

In this way, by forming the iron mixed crystal layer 2Y using ammonia mist as an auxiliary material, it is possible to obtain the iron mixed crystal layer 2Y with the desired film thickness with high precision.

In the etching method of the first embodiment, the layered structure 3 (3B) of the chromium alloy layer 1 and the aluminum alloy layer 2 is the structure to be etched. However, the structure to be etched is not limited to the layered structure 3.

For example, a two-layer independent structure including a chromium alloy layer 1 and an aluminum alloy layer 2 formed independently on a sapphire substrate 8 without contacting each other can be the etching target structure. That is, at least one of the first etching process using the Cr etchant F1 and the second etching process using the Al etchant F2 may be performed on the two-layer independent structure.

For example, a first etching process using Cr etchant F1 can be performed on the two-layer independent structure using a resist patterned on the chromium alloy layer 1 as a mask, to pattern only the chromium alloy layer 1. In this case, since the aluminum alloy layer 2 is not etched by the Cr etchant F1, there is no need to form a resist on the aluminum alloy layer 2.

In addition, in the etching methods shown in the second and third embodiments, the layered structure 4 (4B) including the chromium alloy layer 1, the aluminum alloy layer 2, and the silicon oxide layer 6 is the structure to be etched. However, the structure to be etched is not limited to the layered structure 4.

For example, the etching target structure may be a three-layer independent structure including a chromium alloy layer 1, an aluminum alloy layer 2, and a silicon oxide layer 6 formed independently on a sapphire substrate 8 without contacting each other. That is, at least one of the following etching processes may be performed on the three-layer independent structure: a first etching process using a Cr etchant F1, a second etching process using an Al etchant F2, and a third etching process using a silicon oxide etchant F3.

For example, the three-layer independent structure can be subjected to a first etching process using Cr etchant F1, using a resist patterned on the chromium alloy layer 1 as a mask, to pattern the chromium alloy layer 1. In this case, since the aluminum alloy layer 2 and the silicon oxide layer 6 are not etched by the Cr etchant F1, there is no need to form a resist on the aluminum alloy layer 2 and the silicon oxide layer 6.

In addition, within the scope of this disclosure, it is possible to freely combine the various embodiments, modify or omit each embodiment as appropriate.

The etching method and semiconductor device disclosed herein can form an etching technique for a semiconductor device using gallium oxide and an active layer for the semiconductor device, providing basic technology for gallium oxide-based semiconductor devices and being extremely useful in industry.

REFERENCE SIGNS LIST 1 Chromium alloy layer 2 Aluminum alloy layer 2X Indium alloy layer 2Y Iron alloy layer 3, 3B, 4, 4B Laminated structure 6 Silicon oxide layer 13, 13B, 14, 14B Patterned structure 31, 32 Metal laminated structure 34A to 34C Intermediate patterned structure 35 HEMT final structure

Claims (8)

(a) obtaining a structure to be etched comprising first and second mixed crystal layers;
(b) performing at least one of a first etching process for selectively etching a first mixed crystal layer with a first etching agent on the etching target structure and a second etching process for selectively etching the second mixed crystal layer with a second etching agent on the etching target structure;
The first mixed crystal layer contains (M1 _x Ga _1-x ) ₂ O ₃ (0<x≦1),
the second mixed crystal layer contains (M2 _y Ga _1-y ) ₂ O ₃ (0<y≦1);
M1=Cr;
M2=one of {Al, In, Fe};
the first mixed crystal layer has crystallinity when {x≠1};
The second mixed crystal layer has crystallinity when {y≠1}.
Etching method. (a) obtaining a structure to be etched, the structure including first and second mixed crystal layers and a silicon oxide layer;
(b) performing at least one of a first etching process for selectively etching a first mixed crystal layer with a first etching agent on the structure to be etched, a second etching process for selectively etching the second mixed crystal layer with a second etching agent on the structure to be etched, and a third etching process for selectively etching the silicon oxide layer with a third etching agent on the structure to be etched;
The first mixed crystal layer contains (M1 _x Ga _1-x ) ₂ O ₃ (0<x≦1),
the second mixed crystal layer contains (M2 _y Ga _1-y ) ₂ O ₃ (0<y≦1);
M1=Cr;
M2=one of {Al, In, Fe};
the first mixed crystal layer has crystallinity when {x≠1};
The second mixed crystal layer has crystallinity when {y≠1}.
Etching method. 3. The etching method according to claim 2,
the third etchant comprises a buffered hydrofluoric acid solution;
Etching method. The etching method according to any one of claims 1 to 3,
The second etchant includes _HNO3 , _CH3COOH , and _{H3PO4 ;}
Etching method. 5. The etching method according to claim 4,
_the second etchant comprises _HNO3 , _CH3COOH , _H3PO4 , and _H2O ;
The second etching agent is a mixture of 5-15% by _weight of HNO3, 5-15% by weight of _CH3COOH , 60-80% by weight _{of H3PO4} , and 10-20% by weight of _H2O ;
Etching method. The etching method according to any one of claims 1 to 5,
The first etchant includes ( _NH4 ) _2Ce ( _NO3 ) ₆ and _HClO4 ;
Etching method. 7. The etching method according to claim 6,
the first etchant comprises ( _NH4 ) _2Ce ( _NO3 ) ₆ , _HClO4 and _H2O ;
The first etching agent is a mixture of 5-15% by weight of (NH ₄ ) ₂ Ce(NO ₃ ) ₆ , 60-80% by weight of HClO ₄ , and 10-20% by weight of H ₂ O;
Etching method. The etching method according to any one of claims 1 to 7,
M2=Fe;
The step (a)
(a-1) supplying an ammonia mist to form the second mixed crystal layer;
Etching method.

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