JP7548111B2 - Electronic Control Unit - Google Patents

Description

The present invention relates to an electronic control device.

In recent years, for example in electronic control devices for automobiles, efforts are being made to improve the processing power of microcomputers due to the increasing complexity of control. One example is a microcomputer equipped with multiple cores and a parallel processor, where the core requests the parallel processor to process a set of arithmetic instructions, which is a collection of arithmetic instructions, and the parallel processor processes the arithmetic instructions in parallel, thereby speeding up arithmetic processing.

JP 2016-95796 A

The parallel processor extracts an instruction from a set of instructions requested by the core, and uses the hardware functions to automatically allocate optimal resources to multiple processors, enabling high-speed parallel calculations. This makes it possible to reduce the processing time of the core by having the parallel processor process tasks that require high-speed processing.

However, the information used for processing by the parallel processor needs to be loaded from the shared memory to the internal memory of the parallel processor for each control period, and the overhead incurred during this process increases processing time, potentially reducing the benefits of using the parallel processor.

The present invention was made in consideration of the above circumstances, and its purpose is to provide an electronic control device that can shorten the processing time when a control unit processes a group of arithmetic instructions using a parallel arithmetic processor.

According to the invention of claim 1, when the control unit (12a-12c) controls the control target based on the control information, if it becomes necessary to perform calculation based on the map in the parallel processor, the control unit (12a-12c) loads the map information in the shared memory to a predetermined address in the internal memory (23) provided in the parallel processor, and provides the parallel processor (13) with variables required for obtaining the control information as arguments. The parallel processor performs pre-calculation and stores the map information stored in the predetermined address and the arguments provided from the control unit, and provides the calculation result to the control unit if a calculation result of the map interpolation value by the pre-calculation is stored corresponding to the arguments provided at the time of actual calculation. The control unit obtains control information based on the calculation result provided from the parallel processor, and controls the control target using the control information. If the argument provided from the control unit is outside the range of the pre-calculation, the control unit is notified that the argument is outside the range, and the map interpolation value is calculated by either the control unit or the parallel processor, which is predetermined according to the number of dimensions and scale of the map.

FIG. 1 is a functional block diagram showing a configuration of a microcomputer according to a first embodiment; A block diagram showing the connections between the engine ECU and each ECU. A block diagram showing the configuration of a parallel arithmetic processor. A diagram showing the structure of the operation instruction group Diagram showing the operations involved in precomputation A diagram showing a one-dimensional map Diagram showing the search method Diagram showing calculation points Diagram showing the scope around the arguments A diagram showing transmission and reception between a core and a parallel processor FIG. 13 is a diagram showing transmission and reception between a core and a parallel processor according to the second embodiment. FIG. 13 is a diagram showing transmission and reception between a core and a parallel processor according to the third embodiment. FIG. 13 is a diagram showing a two-dimensional map according to the fourth embodiment; Diagram showing calculation points Diagram showing linear interpolation in the X-axis direction (part 1) Diagram showing linear interpolation in the X-axis direction (part 2) A diagram showing linear interpolation in the Y-axis direction. Diagram showing the scope around the arguments

Several embodiments will be described below with reference to the drawings. In several embodiments, functionally or structurally corresponding parts may be given the same reference numerals.

First Embodiment
The first embodiment will be described with reference to FIGS.
As shown in Fig. 2, the vehicle is equipped with an engine ECU (Electronic Control Unit) 1. The engine ECU 1 corresponds to an electronic control device. The engine ECU 1 is communicably connected to other ECUs, such as an automatic transmission ECU 3, a meter ECU 4, and an air conditioning ECU 5, via an in-vehicle LAN 2. The protocol of the in-vehicle LAN 2 is, for example, CAN (Controller Area Network). CAN is a registered trademark.

The engine ECU 1 is mainly composed of a microcomputer 11. As shown in FIG. 1, the microcomputer 11 is composed of a core group 12 consisting of multiple cores 12a to 12c and a parallel calculation processor 13, and these cores 12a to 12c and the parallel calculation processor 13 process multiple calculations in parallel to achieve high-speed processing.

The cores 12a to 12c and the parallel processor 13 are connected to each other via an internal bus 14, and are also connected to memories such as ROM 15 and RAM 16, and to I/O 17 such as a CAN interface. The microcomputer 11 is also connected to other microcomputers 18 and peripheral circuits 19 such as AD converters.

The cores 12a to 12c receive detection signals from various sensors for detecting the operating state of the engine via the input circuit 20, and process the detection values indicated by the detection signals to control actuators for controlling the engine via the output circuit 21, and send and receive communication signals with other ECUs via the communication circuit 22. When specific calculation processing is required to control the engine, the cores 12a to 12c request the parallel calculation processor 13 to perform the processing.

As shown in FIG. 3, the parallel arithmetic processor 13 is composed of a memory 23, a control circuit 24, and multiple arithmetic units 25. The memory 23 sequentially stores information for processing groups of arithmetic instructions provided by the multiple cores 12a to 12c.

The control circuit 24 performs calculations on the set of calculation instructions stored in the memory 23 in cooperation with the arithmetic unit 25. In other words, the control circuit 24 has a scheduler function and automatically allocates the calculation instructions constituting the set of calculation instructions stored in the memory 23 to the corresponding arithmetic unit 25.

The calculator 25 sequentially processes the calculation instructions assigned by the control circuit 24. The calculators 25 may be of the same type or different types, and parallel processing is possible by assigning the same type or different types of calculation instructions to the calculators 25. The calculator 25 stores the calculation processing results in the memory 23.

When the multiple cores 12a to 12c request the parallel processor 13 to process a group of arithmetic instructions, they obtain the results of the arithmetic via the memory 23 and execute subsequent processing based on the results of the arithmetic.

The processing order of the calculation instructions requested by the cores 12a to 12c is specified. For example, the calculation instruction group shown in FIG. 4 specifies that the processing of the calculation instruction A is completed before the next calculation instructions B to D are processed, and that the processing of the next calculation instruction E is completed after all the calculation instructions B to D are processed.

Now, in order to reduce the processing time of the cores 12a to 12c, it is conceivable to have the parallel processor 13 process tasks that require high-speed processing; however, the information used in the processing of the parallel processor 13 needs to be loaded from the shared memory of the electronic control device to the internal memory 23 of the parallel processor 13 for each control cycle. For this reason, the overhead generated at that time increases the processing time, and there is a risk that the effect of using the parallel processor 13 will be reduced.

In view of these circumstances, in this embodiment, if there is processing that can be pre-calculated by the parallel arithmetic processor 13, a processing request is made to the parallel arithmetic processor 13 in advance. When making this processing request, information required for the pre-calculation is passed to the parallel arithmetic processor 13. Upon receiving the processing request, the parallel arithmetic processor 13 performs pre-calculation based on the information and stores the calculation results. The range of pre-calculation is determined according to the characteristics of the information. For example, a parameter indicated by a time constant is determined, and if the range of fluctuation of the information is likely to change for each control cycle, the parameter is set large to set a large range of pre-calculation.

In the following, map calculation is exemplified as a process that can be pre-calculated by the parallel calculation processor 13, but the process is not limited to map calculation and may be any process that can be pre-calculated.
As shown in FIG. 5, map information for control is stored in the shared memory 26 of the electronic control unit, and when it becomes necessary for the parallel processor 13 to perform calculations based on the map, the map information is loaded into a specified address in the internal memory 23 of the parallel processor.

Addresses for loading map information corresponding to the requesting cores 12a to 12c are set in the internal memory 23, and when loading map information into the parallel arithmetic processor 13, it is loaded into the corresponding address. When a variable is given from the cores 12a to 12c, the parallel arithmetic processor 13 performs map calculations based on the map information stored in the corresponding address and returns the calculation results to the cores 12a to 12c.

The above operation will now be described in detail.
The cores 12a to 12c store in advance a one-dimensional map as shown in Fig. 6. This one-dimensional map shows the correspondence between map points X and corresponding value points Y. A corresponding value Y1 is set corresponding to map point X1, a corresponding value Y2 is set corresponding to map value X2, ... a corresponding value Y9 is set corresponding to map value X9.

When using such a one-dimensional map to determine a map interpolation value corresponding to a variable, if the variable is a map point (X1, X2, ...) defined on the X-axis of the one-dimensional map, the corresponding value (Y1, Y2, ...) can be directly determined, but if the variable is not defined on the X-axis, the map interpolation value YA cannot be directly determined from the variable XA.

In such a case, map point A can be interpolated based on the map points of the X-axis and Y-axis, but if cores 12a to 12c were to perform the interpolation based on a one-dimensional map, the processing time of cores 12a to 12c would become too long and there is a risk that they would not be able to keep up with the calculations. Therefore, the interpolation process, which requires high speed processing, is performed by parallel calculation processor 13, thereby reducing the processing time of cores 12a to 12c.

When the cores 12a to 12c obtain a map interpolation value corresponding to a variable in the next periodic task, they provide the current variable or a variable predicted from the current variable to be used in the next periodic task as an argument XA to the parallel calculation processor 13.
A method of calculating the map interpolation value YA corresponding to the argument XA by the interpolation process in the parallel calculation processor 13 will be described below, where X1≦XA≦X2 is assumed.

The parallel calculation processor 13 first performs an axis search. In the axis search, as shown in FIG. 7, a magnitude judgment is performed starting from map point X9 to determine whether the calculation point is between map points X1 to X9, and the corresponding calculation point is searched for. The axis search may start from map point X1, or from an intermediate map point. If the calculation point is between X1 and X2 when searching from X9, it is predicted that the number of searches will continue to increase. Therefore, it is desirable to improve the efficiency of the search by changing the search start point for each control cycle based on the calculation point from the previous axis search.

If the axis search by magnitude judgment finds that X1≦XA≦X2 as shown in Fig. 8, one-dimensional map interpolation processing is executed. In this interpolation processing, a map interpolation value YA corresponding to the argument XA is calculated from map points (X1, Y1) and (X2, Y2) using the following linear interpolation formula of the first degree.
YA=((Y2-Y1)/(X2-X1))*(XA-X1)+Y1
By executing the axis search and interpolation processing of the arguments as described above, map calculation is performed, and a map interpolation value YA corresponding to the argument XA can be obtained as shown in FIG.

Next, since X1≦XA≦X2, the range indicated by diagonal lines in Figure 9 is defined as the range around the argument, and interpolation processing is performed for each lattice point. The range around the argument on the X-axis is expressed as ±pLSB from the argument point in the X-axis direction. LSB is the amount of change in the physical value when the RAM value indicating XA changes by 1, in other words, the minimum amount of change in the variable. p is a parameter that indicates the axis characteristics as a time constant. The range around the argument is set by predicting the fluctuations for each control cycle.

Next, the operation of performing map calculations in the parallel arithmetic processor 13 in response to processing requests from the cores 12a to 12c will be described. This embodiment is characterized in that the parallel arithmetic processor 13 pre-calculates and stores map interpolation values, processes the next periodic task based on the map interpolation values associated with the arguments sent from the cores 12a to 12c, and passes the calculation results to the cores 12a to 12c.

As shown in FIG. 10, information is transmitted and received between the cores 12a to 12c and the parallel processor 13 as follows.
[Precalculation]
(1) The cores 12a to 12c transmit the arguments of the map to be used in the next periodic task and map information around the arguments.
(2) The parallel calculation processor 13 performs map calculations by executing axis search and interpolation processing around the arguments, and stores the arguments and the map interpolated values in association with each other.
(3) The parallel calculation processor 13 transmits the address of the internal memory 23 that holds the map interpolation value.

[Periodic task processing]
(4) When the next control period begins, the cores 12a to 12c request processing.
(5) The parallel processor 13 performs a process to obtain a calculation value associated with the argument from the cores 12a to 12c. At this time, the map used is the map calculation stored in (2).
(6) If the argument to be used is within the range of values stored in (2), the parallel processor 13 returns the calculation result of (5). On the other hand, if the argument to be used is outside the range, the parallel processor 13 notifies the cores 12a to 12c that the argument is outside the range.

(7) When cores 12a to 12c receive information indicating that the value is outside the range, they perform axis search and interpolation processing to calculate the map. Depending on the number of dimensions and scale of the map, calculations are performed by parallel processor 13, which may be faster. It is determined in advance whether calculations should be performed by cores 12a to 12c or parallel processor 13, depending on the number of dimensions and scale of the map.

(8) The cores 12a to 12c transmit the map interpolation value and the map information when it is faster to have the parallel calculation processor 13 perform the calculation.
(9) The parallel calculation processor 13 performs map calculations based on the received information.
(10) The parallel processor 13 returns the calculation result, so that the cores 12a to 12c execute the subsequent processing based on the calculation result.

[Precalculate next periodic task]
(11) For the recalculated map, the cores 12a to 12c transmit the arguments of the map to be used in the next periodic task and map information around the arguments.
(12) The parallel calculation processor 13 performs the same process as in (2) and updates the results it has stored.
(13) The parallel calculation processor 13 transmits the address holding the map interpolation value.

According to this embodiment, the following effects can be obtained.
The parallel processor 13 pre-calculates and stores map interpolation values corresponding to arguments and their periphery from the stored map based on arguments provided from the cores 12a to 12c, and if a calculation result of the pre-calculation corresponding to an argument provided in the next periodic task is stored, the parallel processor 13 provides the calculation result to the cores 12a to 12c, and the cores 12a to 12c execute subsequent processing using the map interpolation values calculated based on the calculation result provided from the parallel processor 13. This makes it possible to suppress overhead, thereby shortening the processing time using the parallel processor 13.

Since the range around the argument by the parallel calculation processor 13 is set in accordance with the characteristics of the map axis, the range around the argument can be set appropriately.
The cores 12a to 12c can receive the calculation results by transmitting arguments at the desired timing after pre-calculation, so that the subsequent processing can be executed quickly.

The parallel computing unit 13 changes the memory area in which the calculation results are stored depending on the destination of the calculation results, so that the cores 12a to 12c can receive the calculation results at any time.

Second Embodiment
The second embodiment will be described with reference to Fig. 11. The second embodiment is characterized in that the parallel arithmetic processor 13 pre-calculates and holds map interpolation values, and in the next periodic task, passes the map interpolation values associated with arguments transmitted from the cores 12a to 12c to the cores 12a to 12c, and the cores 12a to 12c execute calculations based on the map interpolation values.

As shown in FIG. 11, information is transmitted and received between the cores 12a to 12c and the parallel processor 13 as follows.
[Precalculation]
(1) The cores 12a to 12c transmit the arguments of the map to be used in the next periodic task and map information around the arguments.
(2) The parallel calculation processor 13 performs map calculations by executing axis search and interpolation processing around the arguments, and stores the arguments and the map interpolated values in association with each other.
(3) The parallel calculation processor 13 transmits the address of the internal memory 23 that holds the map interpolation value.

[Periodic task processing]
(4) When the next control cycle begins, the cores 12a to 12c transmit the map arguments.
(5) If the argument to be used is within the range of the information held in (2), the parallel processor 13 returns a map interpolation value associated with the argument. On the other hand, if the argument to be used is outside the range of the information held in (2), the parallel processor 13 notifies the user that the argument is outside the range.

(6) Cores 12a to 12c process based on the received map interpolation value. On the other hand, if it receives information indicating that the value is outside the range, it performs the map calculation by executing axis search and interpolation processing. If it is better to have the calculation performed by the parallel calculation processor 13 due to the number of dimensions and scale of the map, the map information is sent to the parallel calculation processor 13, and the calculation is performed by the parallel calculation processor 13. In this case, it is determined in advance which method should be used for the calculation depending on the number of dimensions and scale of the map.

(7) The parallel processor 13 transmits map information when the parallel processor 13 is to perform map calculations.
(8) The parallel calculation processor 13 performs map calculations.
(9) The parallel calculation processor 13 transmits the map interpolated value.
(10) The cores 12a to 12c process the received map interpolated values using the interpolated values.

[Precalculate next periodic task]
(11) For the recalculated map, the cores 12a to 12c transmit the arguments of the map to be used in the next periodic task and map information around the arguments.
(12) The parallel calculation processor 13 performs the same process as in (2) and updates the results it has stored.
(13) The parallel calculation processor 13 transmits the address holding the map interpolation value.

In this embodiment, the parallel arithmetic processor 13 pre-calculates and stores the map interpolation value, passes the map interpolation value associated with the argument sent from the cores 12a to 12c to the cores 12a to 12c in the next periodic task, and executes calculations based on the map interpolation value in the cores 12a to 12c. Therefore, even if the processing power of the parallel arithmetic processor 13 is reduced, the overall processing time can be shortened.

Third Embodiment
The third embodiment will be described with reference to Fig. 12. The third embodiment is characterized in that the parallel calculation processor 13 pre-calculates map interpolation values, the cores 12a to 12c hold information related to the pre-calculation, and the next periodic task is processed based on the map interpolation values associated with arguments.

[Precalculation]
(1) The cores 12a to 12c transmit the arguments of the map to be used in the next periodic task and map information around the arguments.
(2) The parallel calculation processor 13 performs map calculations by executing axis search and interpolation processing around the arguments, and associates the arguments with map interpolated values.
(3) The parallel processor 13 transmits the information in (2).
(4) The cores 12a to 12c store the received information.

[Periodic task processing]
(5) The cores 12a to 12c use the stored information to carry out processing. If the result corresponding to the argument is not stored, the cores 12a to 12c perform a map calculation before carrying out processing.

[Precalculate next periodic task]
(6) For the recalculated map, the cores 12a to 12c transmit the arguments of the map to be used in the next periodic task and map information around the arguments.
(7) The parallel calculation processor 13 performs the same process as in (2).
(8) The parallel processor 13 transmits the processed information.
(9) The cores 12a to 12c update the information in (4).

In this embodiment, the map is calculated by sending arguments and map information to the parallel arithmetic processor 13 in advance, and the cores 12a to 12c hold the related information. The next periodic task is processed based on the map interpolation value associated with the arguments, so that the overall processing time can be shortened even if the processing capacity of the parallel arithmetic processor 13 is extremely reduced.

(Fourth embodiment)
The fourth embodiment will be described with reference to Figures 13 to 16. The fourth embodiment is characterized in that a two-dimensional map is used as the target map.

As shown in FIG. 13, in the two-dimensional map, a corresponding value Z11 is set corresponding to map point (X1 (X1≦XA≦X2), Y1 (Y1≦YA≦Y2)), a corresponding value Z12 is set corresponding to map point (X2, Y2), ... a corresponding value Z99 is set corresponding to map point (X9, Y9).
As shown in FIG. 14, the method of calculating an interpolated value ZA of an arbitrary point (XA, YA) in a two-dimensional map is a combination of linear interpolations using linear expressions in the X-axis and Y-axis directions.

That is, by searching for the calculation point of the map point of an arbitrary point (XA, YA), the calculation point can be determined as shown in FIG. 14. Since the calculation point is between four points (X1, Y1, Z11), (X2, Y1, Z12), (X1, Y2, Z21), and (X2, Y2, Z22), the interpolated value ZA of the map point (XA, YA) is calculated by combining linear interpolation using the first-order equations of the following interpolation processes 1 to 3.

First, Zi corresponding to the point (XA, Y1) is found by the interpolation process 1.
In the interpolation process 1, as shown in FIG. 15, an interpolation value Zi is calculated from map points (X1, Y1, Z11), (X2, Y1, Z12) based on the search result of point (XA (X1≦XA≦X2), Y1).
The linear interpolation equation in the X-axis direction is Zi = ((Z12 - Z11) / (X2 - X1)) * (XA - X1) + Z11.

Next, Zii corresponding to point (XA, Y2) is found by the interpolation process 1.
In the second interpolation process, as shown in FIG. 16, an interpolated value Zii is calculated from map points (X1, Y2, Z21), (X2, Y2, Z22) based on the search result of point (XA (X1≦XA≦X2), Y2).
The linear interpolation equation in the X-axis direction is Zii = ((Z22 - Z21) / (X2 - X1)) * (XA - X1) + Z21.

Finally, ZA corresponding to point YA is obtained by the interpolation process 3.
As shown in FIG. 17, the interpolation process 3 calculates an interpolation value ZA for a point YA (Y1≦YA≦Y2) from the two points (XA, Y1, Zi) and (XA, Y2, Zii) of the interpolated values calculated in the interpolation processes 1 and 2.
The linear interpolation equation in the Y-axis direction is ZA=((Zii-Zi)/(Y2-Y1))*(YA-Y1)+Zi.
Instead of first interpolating the X-axis direction and then the Y-axis direction, the Y-axis direction may be interpolated first and then the X-axis direction.

As shown in Figure 18, for example, if the argument is a point (X (X1 <= X <= X2), Y (Y1 <= Y <= Y2)), the area around the argument is defined as the diagonal line range, and interpolation is performed for each lattice point. In other words, the axis is calculated as ±pLSB in the X-axis direction and ±qLSB in the Y-axis direction from the argument point. LSB is the amount of change in the physical value when the RAM value changes by 1. In this case, which should be calculated is determined in advance depending on the number of dimensions and scale of the map. For example, if the X-axis is water temperature and the Y-axis is engine speed, engine speed is basically the parameter that changes more easily, so the Y-axis is set to be wider.

According to this embodiment, even if the target map is a two-dimensional map, map calculations can be performed appropriately by sequentially interpolating the X-axis direction and the Y-axis direction.

Other Embodiments
If the parallel processor 13 does not store the calculation result corresponding to the argument given in advance in the current periodic task, the parallel processor 13 may perform a calculation based on the argument given in the current task and transmit the calculation result to the cores 12a to 12c. In this case, the interpolation process can be performed even if the periphery of the argument has not been interpolated.

The parallel arithmetic processor 13 may perform calculations on the currently given arguments and related arguments before executing the next periodic task, and update the stored calculation results. In this case, even if the parallel arithmetic processor 13 does not store the calculation results corresponding to the arguments, it is possible to prevent the effect of using the parallel arithmetic processor 13 from decreasing.

The first to third embodiments may be combined according to the processing capacity of the parallel arithmetic processor 13. In other words, when the processing capacity of the parallel arithmetic processor 13 is high, it may operate as in the first embodiment, and when the processing capacity decreases, it may operate as in the second or third embodiment.

The target map may be three or more dimensional.
The electronic control device is not limited to the engine ECU, and may be any device that controls a controlled object.

Although the present disclosure has been described with reference to an embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

In the drawing, reference numeral 1 denotes an engine ECU (electronic control unit), 11 denotes a microcomputer, 12a to 12c denote cores (control units), 13 denotes a parallel arithmetic processor, and 25 denotes a computing unit.

Claims (7)

An electronic control device including a microcomputer (11) equipped with a parallel arithmetic processor (13) capable of performing parallel processing by a plurality of arithmetic units (25),
A shared memory (26) in which map information for control is stored;
A control unit (12a to 12c) that controls a control target based on control information ,
When it becomes necessary for the parallel processor to perform a calculation based on a map, the control unit loads the map information of the shared memory into a predetermined address of an internal memory (23) provided in the parallel processor, provides the parallel processor with variables required for a calculation to obtain the control information as arguments, and obtains the control information based on the calculation result provided by the parallel processor.
The parallel calculation processor performs pre-calculation and stores the map interpolation value based on the map information stored at the specified address and the arguments provided by the control unit, and if a calculation result of a map interpolation value by pre-calculation has been stored corresponding to the arguments provided by the control unit at the time of actual calculation, it provides the calculation result to the control unit , and if the arguments provided by the control unit are outside the pre-calculated range, it notifies the control unit that the arguments are outside the range, and calculates the map interpolation value using either the control unit or the parallel calculation processor, which is predetermined depending on the number of dimensions and scale of the map . The electronic control device according to claim 1, wherein the parallel calculation processor performs calculations on arguments and their surroundings as pre-calculation. The variables are set as axes of the map;
3. The electronic control device according to claim 2, wherein a range around an argument by the parallel processor is set according to characteristics of the axis. The electronic control device according to any one of claims 1 to 3, wherein the control unit receives the calculation result of the pre-calculation by sending arguments at a timing when the control unit desires to receive the calculation result after the pre-calculation. The electronic control device according to claim 4, wherein the parallel processor changes the memory area in which the pre-calculated calculation results are stored depending on the destination of the calculation results. The electronic control device according to any one of claims 1 to 5, wherein, when the parallel arithmetic processor does not store the calculation result corresponding to the argument given in the pre-calculation at the time of the actual calculation, the parallel arithmetic processor performs the calculation based on the currently given argument and transmits the calculation result to the control unit. The electronic control device according to claim 6, wherein when the parallel processor performs a calculation based on the currently given argument in a case where the calculation result corresponding to the argument given in the pre-calculation is not stored at the time of the actual calculation, the parallel processor calculates the argument and its surroundings and updates the stored calculation result.

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