JP7303021B2 - capacitance measurement circuit, capacitance measurement method, power supply circuit, data storage device, power management circuit - Google Patents

Description

The present invention relates to capacitance measurement circuits.

A stable power supply voltage is essential for electronic components. In a storage device such as a solid state drive or a hard disk, if the power supply voltage is interrupted momentarily, the stored data may be destroyed or lost. Even after the input voltage is cut off, it is required to maintain the power supply voltage during the period when the load performs necessary protection processing such as data saving. Such functions are called power loss protection, PLP (Power Loss Protection), PLI (Power Loss Imminent), PFP (Power Failure Protection), and the like.

FIG. 1 is a block diagram of a system with PLP functionality. System 2 comprises main power supply 10 , load 20 and power supply circuit 30 . A main power supply 10 produces a DC input voltage _VIN .

The power supply circuit 30 is provided in the main power supply 10 and the load 20 . The input terminal VIN of the power supply circuit 30 is supplied with the input voltage _VIN generated by the main power supply 10, and the load 20 is connected to the output terminal VSYS.

The power supply circuit 30 includes switches SW11, SW12, SW13, a backup capacitor Cb, and a controller . The switch SW11 is provided on a power supply line 38 connecting the main power supply 10 and the load 20 . As long as a valid input voltage V _IN is present, the switch SW11 is turned on and the input voltage V _IN is provided to the load 20 as the power supply voltage V _SYS . The switch SW13 is provided between the input terminal VIN and the backup capacitor Cb. By turning on the switch SW13, the backup capacitor Cb is charged.

The switch SW12 is provided between the backup capacitor Cb and the output terminal VSYS. Controller 34 _monitors the input voltage VIN at input terminal VIN to determine whether it is in a normal condition or a power loss condition. When controller 34 detects a power loss condition, it turns off switches SW11 and SW13 and turns on SW12.

If the backup capacitor Cb is deteriorated or damaged, the backup operation cannot be performed. Therefore, it is required to detect deterioration/loss of the backup capacitor Cb in advance.

The present invention has been made in this context, and one exemplary object of some aspects thereof is to provide a highly accurate capacitance measurement circuit.

One aspect of the present invention relates to a capacitance measurement circuit that measures capacitance of a capacitor. The capacitance measurement circuit includes a current source that sources into or sinks from the capacitor a current that is proportional to the reference voltage and inversely proportional to the resistance of the first resistor, and a current source that is inversely proportional to the reference voltage and has accuracy relative to the first resistor. An oscillator that generates a clock signal having a period proportional to the guaranteed resistance value of the second resistor, and a timer circuit that counts the time required for the voltage of the capacitor to change by a predetermined voltage width using the clock signal. And prepare.

Another aspect of the invention is also a capacitance measurement circuit. The capacitance measuring circuit includes a current source that sources into or sinks from the capacitor a current that is proportional to the reference voltage and inversely proportional to the resistance of the first resistor, and a current source that is inversely proportional to the reference voltage and has accuracy relative to the first resistor. An oscillator that generates a clock signal having a period proportional to the guaranteed resistance value of the second resistor, a counter that counts the clock signal for a predetermined number of counts, and a digital value that indicates the voltage fluctuation range generated in the capacitor during counting by the counter. an A/D converter that generates

Arbitrary combinations of the above constituent elements, and mutual replacement of the constituent elements and expressions of the present invention between methods, devices, systems, etc. are also effective as aspects of the present invention.

According to one aspect of the present invention, the capacitance of the capacitor can be measured accurately.

1 is a block diagram of a system with PLP functionality; FIG. 1 is a block diagram of a semiconductor device including a capacitance measurement circuit according to Embodiment 1; FIG. 3 is an operation waveform diagram of the capacitance measurement circuit of FIG. 2; FIG. 4 is a circuit diagram showing a configuration example of a current source; FIG. 4 is a circuit diagram showing a configuration example of an oscillator; FIG. It is a circuit diagram which shows the structural example of a timer circuit. 7 is a diagram for explaining the operation of the timer circuit of FIG. 6; FIG. It is a circuit diagram of a timer circuit according to a modification. 10 is a block diagram of a semiconductor device including a capacitance measurement circuit according to a second embodiment; FIG. FIG. 10 is an operation waveform diagram of the capacitance measurement circuit of FIG. 9; 1 is a block diagram of a system including a power supply circuit according to an embodiment; FIG. 12 is a diagram for explaining the operation of the power supply circuit of FIG. 11 at startup; FIG. FIG. 12 is a diagram for explaining the operation of the power supply circuit of FIG. 11 when power is cut off; It is a block diagram of a power supply circuit according to a modification. 1 is a block diagram of a data storage device with PLP functionality; FIG. 16 is a block diagram of a system including a semiconductor device in which the power supply circuit with the PLP function of FIG. 15 and a PMIC are integrated; FIG.

(Embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

In the present specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, as well as a case in which member A and member B are electrically connected. Indirect connection through other members that do not affect the connected state or impede the function is also included. Further, "the state in which the member C is provided between the member A and the member B" means the case where the member A and the member C or the member B and the member C are directly connected, as well as the case where the electrical connection is made. It also includes the case of being indirectly connected through other members that do not affect the state or impede the function.

(Embodiment 1)
FIG. 2 is a block diagram of a semiconductor device 600A including the capacitance measurement circuit 500A according to the first embodiment. The capacitance measurement circuit 500A is integrated in the semiconductor device 600A. The semiconductor device 600 includes a reference voltage source 602 and a capacitor connection pin (hereinafter, CAP pin) in addition to the capacitance measurement circuit 500A. A reference voltage source 602 is a bandgap reference circuit or the like, and generates a constant reference voltage V _REF that is not affected by process variations and temperature fluctuations.

Capacitance measurement circuit 500A receives reference voltage _VREF and measures the capacitance of external capacitor C1 connected to the CAP pin.

The capacitance measurement circuit 500A includes a current source 510, an oscillator 520, a timer circuit 530, and a controller 540.

Current source 510 includes a first resistor R1. Current source 510 sources or sinks current I _C to or from capacitor C1 that is proportional to reference voltage V _REF and inversely proportional to the resistance of first resistor R1. In this embodiment, the current source 510 is of the current sink type and discharges the capacitor C1 with a constant current _IC .
I _C =α×V _REF /R1 (1)
Discharging the capacitor C1 by the current source 510 causes a voltage change with a constant slope in the capacitor C1. α is a constant that has no temperature dependence.

Oscillator 520 includes a second resistor R2. The second resistor R2 is formed so as to ensure relative accuracy with the first resistor R1. Specific resistors R1 and R2 have the same device structure and are formed adjacently (pairing) on a semiconductor substrate.

The oscillator 520 generates a clock signal CLK having a period T _CLK that is inversely proportional to the reference voltage V _REF and proportional to the resistance value of the second resistor R2.
_TCLK =β×R2/ _VREF (2)
β is a constant that has no temperature dependence.
The frequency f, which is the inverse of the period T _CLK of the clock signal CLK, is proportional to the reference voltage V _REF and inversely proportional to the resistance of the second resistor R2.
f=V _REF /(β×R ₂ ) (3)

The timer circuit 530 counts the time required for the voltage _VCAP of the capacitor C1 to change by a predetermined voltage width ΔV using the clock signal CLK. ΔV is a constant that is independent of temperature and process variations. For example, voltage swing ΔV can be generated based on reference voltage V _REF . γ is a constant that has no temperature dependence.
ΔV=γ× _VREF (4)
The count value N obtained by timer circuit 530 represents the capacitance value of capacitor C1.

Controller 540 integrally controls capacitance measurement circuit 500A. The controller 540 can be composed of logic circuits.

The above is the basic configuration of the capacitance measurement circuit 500A. Next, the operation will be explained. FIG. 3 is an operation waveform diagram of the capacitance measurement circuit 500A of FIG.

Prior to time _t0 , capacitor C1 has been charged to some initial voltage _{V_INIT} . Controller 540 begins the capacitance measurement at time _t0 . Specifically, current source 510 is enabled to start discharging capacitor C1 with current _IC . It also enables the oscillator 520 and starts generating the clock signal CLK.

A timer circuit 530 monitors the capacitor voltage V _CAP . The time Δt required for the capacitor voltage V _CAP to change by a predetermined voltage width ΔV is expressed by equation (5). C is the capacitance of the capacitor.
Δt=ΔV×C/I _C (5)

A count number N when this time Δt is counted by the clock signal CLK is represented by the equation (6).
N=Δt/ _TCLK
=ΔV×C/( _IC × _TCLK ) (6)

By substituting equations (1) and (2) into equation (6), equation (7) is obtained.
N=ΔV×C/(α× _VREF /R1×β×R2/ _VREF )
=ΔV×C/(α・β・R2/R1) (7)

The two resistors R1 and R2 are paired, and the accuracy of the relative value against process variations and temperature fluctuations is very high. Therefore, the accuracy of R2/R1 can be increased to about ±1%. Also, since ΔV, α, and β are constants that are not affected by process variations and temperature fluctuations, the count value represented by Equation (7) is a value obtained by measuring the capacitor C with an accuracy of ±1%. .

The above is the operation of the capacitance measurement circuit 500A. According to this capacitance measurement circuit 500A, the capacitance value of the capacitor C1 can be measured with extremely high accuracy regardless of temperature fluctuations and process variations.

Next, a specific configuration example of the capacitance measurement circuit 500A will be described. FIG. 4 is a circuit diagram showing a configuration example of the current source 510. As shown in FIG. Current source 510 includes a V/I conversion circuit 512 and current mirror circuits 514 and 516 . The V/I conversion circuit 512 includes a first resistor R1, a transistor M1, and an error amplifier EA1. V/I conversion circuit 512 generates reference current I _REF1 represented by equation (8).
I _REF1 =V _REF /R1 (8)
Current mirror circuits 514 and 516 fold back the reference current I _REF1 and multiply it by a constant to generate a constant current I _C .
I _C =K1×K2×I _REF1 =K1×K2×V _REF /R1
The mirror ratios K1 and K2 of the current mirror circuits 514 and 516 are constants that are not affected by process variations and temperature _fluctuations . be. In FIG. 4, the current mirror circuits 514 and 516 may be omitted, and the V/I conversion circuit 512 may directly sink the current I _C =I _REF1 from the CAP pin, the conjunction, and the capacitor C1.

FIG. 5 is a circuit diagram showing a configuration example of the oscillator 520. As shown in FIG. Oscillator 520 includes a V/I conversion circuit 522 and capacitor C2. The V/I conversion circuit 522 includes a second resistor R2, a transistor M2, and an error amplifier EA2, and generates a reference current _IREF2 represented by Equation (9). Second resistor R2 is paired with first resistor R1 of current source 510 .
I _REF2 =V _REF /R2 (9)

Oscillator 520 charges (or discharges) capacitor C2 with a current based on reference current I _REF2 , and generates clock signal CLK by comparing voltage V _C2 generated in capacitor C2 with a threshold. The period T _CLK of the clock signal CLK is proportional to the capacitance value of the capacitor C2 and inversely proportional to the reference current I _REF2 .
T _CLK = δ·C2/I _REF2 (10)
Substituting equation (9) into equation (10) yields equation (2). However, β=δ·C2.

The configuration of oscillator 520 based on reference current _IREF2 is not particularly limited, and a known technique may be used. For example, oscillator 520 may include current source 524 , discharge switch 526 and comparator 528 in addition to capacitor C 2 and V/I conversion circuit 522 .

Current source 524 charges capacitor C2 with a current I _CHG proportional to reference current I _REF2 . Discharge switch 526 is controlled according to the output of comparator 528 and turns on when voltage V _C2 of capacitor C2 exceeds threshold V _TH to discharge the charge of capacitor C2 and reset voltage V _C2 . Instead of the discharge switch 526, a discharge circuit for discharging the capacitor C2 with a current _{I_DIS} proportional to the reference current _{I_REF2} may be provided to alternately repeat charging and discharging.

FIG. 6 is a circuit diagram showing a configuration example of the timer circuit 530. As shown in FIG. The timer circuit 530 includes a voltage dividing circuit 532 , a selector 534 , a comparator 536 and a counter 538 . A voltage divider circuit 532 divides the reference voltage V _REF to produce a first reference voltage V _REFH and a second reference voltage V _REFL . The difference between the first reference voltage V _REFH and the second reference voltage V _REFL corresponds to the predetermined voltage width ΔV described above. Voltage dividing circuit 532 includes three resistors R31 to R33 connected in series. The resistors R31 to R33 have the same element structure and are arranged close to each other on the semiconductor substrate so as to ensure relative accuracy with each other.

A selector 534 receives two reference voltages V _REFH and V _REFL and selects one of them. A comparator 536 compares the voltage V _CAP on capacitor C 1 to the output voltage V _TH of selector 534 . The controller 540 switches the state of the selector 534 according to the output COMPOUT of the comparator 536 . The output of comparator 536 represents the time Δt required for the capacitor voltage V _CAP to change by a predetermined voltage width ΔV. A counter 538 counts the clock signal CLK for a period Δt based on the output of the comparator 536 .

FIG. 7 is a diagram for explaining the operation of timer circuit 530 of FIG. Initially, selector 534 has selected the first reference voltage V _REFH , where V _TH =V _REFH . At time _t0 , current source 510 is enabled, capacitor C1 begins to discharge, and capacitor voltage V _CAP ramps down.

At time t ₁ , when V _CAP <V _TH (ie, V _CAP <V _REFH ), the output COMPOUT of comparator 536 goes low. Controller 540 switches the state of selector 534 in response to the output COMPOUT of comparator 536 . As a result, the selector 534 selects the second reference voltage V _REFL and V _TH =V _REFH . At time t ₂ , when V _CAP <V _TH (ie, V _CAP <V _REFL ), the output COMPOUT of comparator 536 goes low.

The counter 538 starts counting when the COMPOUT signal goes low for the first time, and stops counting when it goes low for the second time. The output N of counter 538 represents the time required for the capacitor voltage V _CAP to change by a predetermined voltage width ΔV.

Timer circuit 530 of FIG. 6 has the advantage of being able to measure a change in predetermined voltage width ΔV without being affected by comparator 536 having an offset voltage _VOFS . This advantage becomes clear by comparison with the variant of FIG.

FIG. 8 is a circuit diagram of a timer circuit 531 according to a modification. This timer circuit 531 has two comparators 536 and 537 . A comparator 536 compares the capacitor voltage V _CAP to a first reference voltage V _REFH and a comparator 537 compares the capacitor voltage V _CAP to a second reference voltage V _REFL . The counter 538 uses the clock signal CLK to measure the time from when the output COMPH of the comparator 536 changes to when the output COMPL of the comparator 537 changes.

In FIG. 8, if the two comparators 536, 537 have different offset voltages, the voltage width ΔV will be affected by the offset voltages. Also, when the two comparators 536 and 537 have different response times (response delays), an error occurs in the time difference Δt. According to the timer circuit 530 of FIG. 6, the problem caused by the circuit of FIG. 8 can be solved, and since only one comparator is required, the circuit area can be reduced. Note that the timer circuit 531 of FIG. 8 may be employed if a comparator with a sufficiently small offset voltage and a sufficiently short response delay can be designed.

(Embodiment 2)
FIG. 9 is a block diagram of a semiconductor device 600B including a capacitance measurement circuit 500B according to the second embodiment. Capacitance measurement circuit 500B receives reference voltage V _REF and measures the capacitance of external capacitor C1 connected to the CAP pin.

The capacitance measurement circuit 500B includes a current source 510, an oscillator 520, a controller 540, a counter 550 and an A/D converter 560. Current source 510 and oscillator 520 are the same as in the first embodiment.

Controller 540 controls capacitance measurement circuit 500B. A reference voltage V _REF is applied to the A/D converter 560, and when the number of bits of the A/D converter 560 is M, the voltage (resolution) corresponding to 1 LSB is V _LSB =V _REF / ^2M. . The digital value DV of the output of the A/D converter 560 when any given voltage _V is input is expressed in decimal by Equation (11).
_DV =V/ _VLSB = ^2M *V/ _VREF (11)

The counter 550 is enabled while the current source 510 is discharging (or charging) the capacitor C1, and counts the clock signal CLK a predetermined number N of times. The A/D converter 560 takes in the voltage _VCAP of the capacitor C1 when the counter 550 starts counting and when the counting ends, and generates two digital values _DV1 and _DV2 . The difference between the two digital values D _V1 and D _V2 is the fluctuation width ΔV of the voltage V _CAP of the capacitor C1 occurring during the period of T _CLK ×N.

The above is the configuration of the capacitance measurement circuit 500B. Next, the operation will be explained. FIG. 10 is an operation waveform diagram of the capacitance measurement circuit 500B of FIG.

Prior to time _t0 , capacitor C1 has been charged to some initial voltage _{V_INIT} . Controller 540 begins the capacitance measurement at time _t0 . Specifically, current source 510 is enabled to start discharging capacitor C1 with current _IC . It also enables the oscillator 520 and starts generating the clock signal CLK.

Controller 540 operates A/D converter 560 at time _t1 . The capacitor voltage V _CAP1 at this time is converted into a digital value D _V1 . Also, the operation of the counter 550 is started at time _t1 . When the number of counts in counter 550 reaches N, that is, at time _t2 after the discharge time of Δt=T _CLK ×N has elapsed from time _t1 , A/D converter 560 performs the second operation, Capacitor voltage V _CAP2 is converted to a digital value D _V2 . The controller 540 calculates the difference ΔD _V between the two digital values D _V1 and D _V2 . _ΔDV is obtained by quantizing the voltage fluctuation width ΔV occurring in the capacitor C1, and is expressed by Equation (12).
ΔD _V =ΔV/V _LSB (12)

The fluctuation width ΔV of the capacitor voltage V _CAP when the capacitor having the capacitance value _C is discharged with the constant current IC for a certain period Δt is given by the equation (13).
ΔV=Δt×IC/ _C (13)

Substituting equation (13) into equation (12) yields equation (14).
ΔD _V =Δt×I _C /(C×V _LSB ) (14)

In formula (14),
Δt=N× _TCLK =N×(β×R2/ _VREF )
I _C =α×V _REF /R1
Substituting , we obtain the equation (15).
ΔD _V =N×(β×R2/V _REF )×α×V _REF /R1/(C×V _LSB )
=N×α×β×(R2/R1)/(C×V _LSB ) (15)

The two resistors R1 and R2 are paired, and the accuracy of the relative value against process variations and temperature fluctuations is very high. Therefore, the accuracy of R2/R1 can be increased to about ±1%. Also, since α, β, and V _LSB are constants that are not affected by process variations and temperature fluctuations, the digital value difference ΔD _V represented by Equation (15) can be used to measure capacitor C with an accuracy of ±1%. Measured value.

The above is the operation of the capacitance measurement circuit 500B. According to this capacitance measurement circuit 500B, the capacitance value of the capacitor C1 can be measured with very high accuracy regardless of temperature fluctuations and process variations.

Next, the application of the capacitance measurement circuits 500A and 500B (hereinafter collectively referred to as 500) will be described. FIG. 11 is a block diagram of system 2A including power supply circuit 100A according to the embodiment. The system 2A comprises a main power supply 10, a load 20 and a power supply circuit 100A. Main power supply 10 supplies a DC input voltage _VIN at a predetermined first voltage level to power supply circuit 100A.

The power supply circuit 100A includes a power supply IC 102A and a backup capacitor Cb. The power supply IC 102A is a functional IC in which main components of the power supply circuit 100A are integrated.

The power supply IC 102A has an input terminal (VIN pin), an output terminal (VSYS pin), and a capacitor connection terminal (VCAP pin). A DC input voltage _VIN is supplied from the main power supply 10 to the VIN pin. A load 20 is connected to the VSYS pin. A large-capacity backup capacitor Cb is connected to the VCAP pin.

The first switch SW1 is provided between the input terminal VIN and the output terminal VSYS. The charging circuit 110 boosts the input voltage _VIN to charge the backup capacitor Cb. Charging circuit 110 can use, for example, a step-up charge pump. The boost rate of the charge pump is not particularly limited. The charging circuit 110 can be switched between enabled and disabled according to the enable signal CP_EN. Charging circuit 110 may be a boost converter instead of a charge pump.

The second switch SW2 is provided between the VCAP pin to which the backup capacitor Cb is connected and the output terminal VSYS.

The controller 130 comprehensively controls the power supply IC 102A. The controller 130 monitors the input voltage V _IN to determine normal conditions or power loss conditions. The controller 130 turns on the first switch SW1 and turns off the second switch SW2 in a normal state. As a result, an output voltage VSYS equal to the input voltage _VIN is generated at the output terminal _VSYS .

The controller 130 also enables the charging circuit 110 under normal conditions. Thereby, the charging circuit 110 charges the backup capacitor Cb. Controller 130 may negate the CP_EN signal to stop operation of charging circuit 110 after charging is complete.

Controller 130 asserts a first enable signal PLP_EN when it detects the loss of input voltage _VIN . The soft start circuit 120 gently turns on the second switch SW2 in response to the assertion of the first enable signal PLP_EN.

A capacitance measurement circuit 500 is connected to the VCAP pin and measures the capacitance of an external backup capacitor Cb. By incorporating the capacitance measurement circuit 500 in the power supply circuit 100, the capacitance of the backup capacitor Cb can be accurately measured, and deterioration or loss of the backup capacitor Cb can be detected based on the measurement result.

The above is the basic configuration of the power supply circuit 100A. Further features of the power supply circuit 100A will now be described. The controller 130 asserts the second enable signal AMP_EN prior to the first enable signal PLP_EN.

Soft start circuit 120 includes a soft start voltage generation circuit 122 and an amplifier 124 . The soft-start voltage generation circuit 122 generates a soft-start voltage _VSS that slowly changes over time in response to the assertion of the first enable signal PLP_EN. The amplifier 124 changes the gate signal SW_G2 of the second switch SW2 based on the soft start voltage _VSS to control the degree of ON. The amplifier 124 is enabled (idle state) in response to the assertion of the second enable signal AMP_EN before the soft start voltage _VSS is generated. In the idle state, the amplifier 124 keeps the second switch SW2 off.

FIG. 12 is a diagram for explaining the operation of the power supply circuit 100A of FIG. 11 at startup. An input voltage V _IN is provided at time _t0 . When the input voltage _VIN exceeds a predetermined threshold value _VTH1 at time _t1 , the first switch SW1 is turned on and the output voltage _VSYS rises. Also, the CP_EN signal is asserted, the backup capacitor Cb is charged by the charging circuit 110, and the capacitor voltage V _CAP rises. During startup, the second switch SW2 is fixed to be off. When the charging of the backup capacitor Cb is completed at time _t2 , the CP_EN signal is negated, the charging operation by the charging circuit 110 is stopped, and the power consumption of the charging circuit 110 is reduced. After that, the backup capacitor Cb becomes a backup power source that stores energy of E=C·V _CAP ² /2.

The energy E stored in the backup capacitor Cb is represented by E=C·V _CAP ² /2. C is the capacitance of the backup capacitor and V _CAP is the charging voltage of the backup capacitor. By increasing the charging voltage V _CAP by the booster circuit, the energy E can be increased for the same capacity, and the time for which the load continues to operate after the power is cut off can be lengthened. Alternatively, the capacity C of the backup capacitor Cb for holding the same energy E can be reduced, and the cost of the system can be reduced.

FIG. 13 is a diagram for explaining the operation of the power supply circuit 100A of FIG. 11 when the power supply is cut off. At time _t3 , the input voltage V _IN is cut off. When controller 130 detects a power loss condition, it proactively asserts a second enable signal AMP_EN at time _t4 . This causes the amplifier 124 to enter an idle state, and the amplifier 124 keeps the second switch SW2 off.

At subsequent time _t5 , controller 130 asserts first enable signal PLP_EN. As a result, the soft start voltage _VSS begins to change gradually. The amplifier 124 changes the gate signal SW_G2 of the second switch SW2 in accordance with the soft start voltage _VSS , and gradually shifts the second switch SW2 from the off state to the on state.

If the second switch SW2 is abruptly turned on, a large current (rush current) may flow from the backup capacitor Cb holding the high voltage _VCAP to the external capacitor connected to the output terminal VSYS. By gently turning on the second switch SW2, a large current can be suppressed.

At time _t5 when _the soft-start voltage _VSS begins to change, the amplifier 124 is in an idle state and has already started up. The gate signal SW_G2 of the second switch SW2 can be changed without delay with respect to _SS , and the second switch SW2 is gently shifted from the off state to the on state.

In FIG. 13, the output voltage V _SYS ' when the amplifier 124 is enabled at time _t5 , which coincides with the start of generation of the soft start voltage V _SS , is indicated by a dashed line. Since the amplifier 124 starts to start up at time _t5 , it cannot respond to the soft start voltage _VSS until time _t6 when the start-up is completed. Therefore, during time t ₅ to t ₆ , power is not supplied to the output terminal VSYS, so the output voltage V _SYS ′ further drops by ΔV. In the present embodiment, the drop width ΔV of the output voltage _VSYS can be reduced by asserting the AMP_EN signal to activate the amplifier 124 prior to the PLP_EN signal.

(Modification)
FIG. 14 is a block diagram of a power supply circuit 100B according to a modification. In FIG. 11, the charging circuit 110 is supplied with the input voltage V _IN without passing through the first switch SW1. 14, the input of the charging circuit 110 is connected to the output side of the first switch SW1, and the input voltage V _IN is supplied to the charging circuit 110 via the first switch SW1. be done. Others are the same as in FIG.

(Application)
The power supply circuits 100A and 100B (hereinafter collectively referred to as the power supply circuit 100) according to the embodiment can be used in the data storage device 300. FIG. FIG. 15 is a block diagram of a data storage device 300 with PLP functionality. The data storage device 300 is, for example, an SSD (Solid State Drive), and includes a power supply circuit 100 , a PMIC 302 , a controller 304 , a NAND memory 306 , a cache memory 308 and an interface 310 .

The data storage device 300 may be built in a computer or may be a portable SSD. Or it may be for servers.

The power supply circuit 100 receives a DC input voltage V _DC from an AC/DC converter or a USB bus (main power supply 10 described above, not shown in FIG. 15), and supplies a power supply voltage V _SYS of a predetermined voltage level to the PMIC 302 . do. The PMIC 302 supplies power supply voltage to the controller 304 , NAND memory 306 , cache memory 308 and interface 310 .

Note that the application of the power supply circuit 100 is not limited to the data storage device 300, and can be used for applications in which the power supply voltage must be maintained for a certain period of time even after power is cut off.

FIG. 16 is a block diagram of a system 400 including a semiconductor device 200 in which the power supply circuit 100 with PLP function and the PMIC 302 of FIG. 15 are integrated. The semiconductor device 200 includes PMOS transistors M1 and M2, a load switch controller 202, a PLP controller 204, a charge pump circuit 206, an A/D converter 208, an internal power supply 210, a clock generator 212, an interface circuit 214, a sequencer 216, and a converter controller 218. , 220 and LDO (Low Drop Output) circuits 222 and 224 . The semiconductor device 200 is a PMIC that includes power supplies of multiple channels (in this example, a 2-channel step-down converter and a 2-channel LDO circuit).

The PMOS transistor M1 corresponds to the first switch SW1 and is called a load switch. The load switch controller 202 has a part of the functions of the controller 130 in FIG. 11, and controls on/off of the PMOS transistor M1. In addition, the load switch controller 202 performs control to switch the connection of the back gate BG of the PMOS transistor M1 to the VIN pin or the VSYS_0 pin, whichever has the higher potential.

The back gate BG of _the PMOS transistor M1 is an OR power supply of the voltage VIN of the VIN pin and the voltage of the VSYS_0 pin, and is supplied to the internal power supply 210 . Before the PMOS transistor M1 is turned on, only VIN exists as a power supply, and during PLP, only VSYS_0 exists. can be done.

The PMOS transistor M2 corresponds to the second switch SW2. PLP controller 204 corresponds to some of the functionality of soft start circuit 120 and controller 130 of FIG. The charge pump circuit 206 is the charging circuit 110 in FIG. 11, and uses an external flying capacitor Cf to boost the input voltage _VIN and charge the backup capacitor Cb. The VSYS_0 pin in FIG. 16 corresponds to the VSYS pin described above. Also, the PLP controller 204 performs control to switch the back gate of the PMOS transistor M2 to the VSYS_0 pin or the VCAP pin, whichever has the higher potential.

The A/D converter 208 converts the capacitor voltage V _CAP , the input voltage V _IN , the voltage indicating the temperature information, the detection signal indicating the current flowing through the first switch SW1, and the like into digital signals.

The internal power supply 210 includes a power supply circuit that generates an internal power supply voltage _VDD , a reference voltage source associated therewith, a power-on reset circuit, a UVLO (Under Voltage Lockout) circuit, a thermal shutdown circuit, and the like. Clock generator 212 is an oscillator that generates a clock signal.

The interface circuit 214 is an interface for communicating with the external host controller 402 and SSD-ASIC 404 . The semiconductor device 200 may be a master PMIC, and a slave PMIC may be connected to the semiconductor device 200 . In this case, the semiconductor device 200 uses the interface circuit 214 to control the slave PMIC.

A sequencer 216 controls the startup sequence and shutdown sequence of a plurality of power supplies based on commands from the outside. Converter controllers 218 and 220 control the step-down converters. LDO circuits 222 and 224 control constant current. The voltage of the VSYS_0 pin is supplied to the input terminals of the step-down converter and the LDO circuit.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the scope of claims. Many modifications and changes in arrangement are permitted without departing from the spirit of the present invention.

2 system 10 main power supply 20 load Cb backup capacitor 100 power supply circuit 102 power supply IC
SW1 first switch SW2 second switch VIN input terminal VSYS output terminal 600 semiconductor device 602 reference voltage source C1 capacitor 500 capacitance measurement circuit 510 current source R1 first resistor 512 V/I conversion circuit 514, 516 current mirror circuit 520 oscillator R2 second 2 resistors 522 V/I conversion circuit 524 current source 526 discharge switch 528 comparator 530 timer circuit 532 voltage dividing circuit 534 selector 536 comparator 538 counter 540 controller 550 counter 560 A/D converter 300 data storage device 302 PMIC
304 controller 306 NAND memory 308 cache memory 310 interface

Claims (9)

A capacitance measurement circuit for measuring the capacitance of a capacitor,
a current source that sources into or sinks from the capacitor a current proportional to the reference voltage and inversely proportional to the resistance of the first resistor;
an oscillator that generates a clock signal having a period that is inversely proportional to the reference voltage and proportional to the resistance value of the first resistor and a second resistor whose relative accuracy is ensured;
a timer circuit that counts the time required for the voltage of the capacitor to change by a predetermined voltage width using the clock signal;
A capacitance measurement circuit, comprising: The timer circuit
a voltage dividing circuit that divides the reference voltage to generate a first reference voltage and a second reference voltage;
a selector that receives the first reference voltage and the second reference voltage and selects one of them;
a comparator that compares the voltage of the capacitor with the output of the selector;
a counter that counts the clock signal for a period based on the output of the comparator;
2. The capacitance measurement circuit of claim 1, comprising: The timer circuit
a voltage dividing circuit that divides the reference voltage to generate a first reference voltage and a second reference voltage;
a first comparator that compares the voltage of the capacitor with the first reference voltage;
a second comparator that compares the voltage of the capacitor with the second reference voltage;
a counter that counts the clock signal for a period defined by the output of the first comparator and the output of the second comparator;
2. The capacitance measurement circuit of claim 1, comprising: A capacitance measurement circuit for measuring the capacitance of a capacitor,
a current source that sources into or sinks from the capacitor a current that is proportional to the reference voltage and inversely proportional to the resistance of the first resistor;
an oscillator that generates a clock signal having a frequency that is inversely proportional to the reference voltage and proportional to the resistance value of the first resistor and a second resistor whose relative accuracy is ensured;
a counter that counts the clock signal for a predetermined number of counts;
an A/D converter that generates a digital value indicating a voltage fluctuation range occurring in the capacitor during counting by the counter;
A capacitance measurement circuit, comprising: a pin to which the backup capacitor is connected;
a backup power supply circuit that charges the backup capacitor and supplies power from the backup capacitor to a load when power is cut off;
The capacitance measurement circuit according to any one of claims 1 to 4, which measures the capacitance of the backup capacitor;
A power supply circuit comprising: A data storage device comprising the power supply circuit according to claim 5 . a pin to which the backup capacitor is connected;
a plurality of DC/DC converters;
a backup power supply circuit that charges the backup capacitor and supplies power from the backup capacitor to the plurality of DC/DC converters when power is cut off;
The capacitance measurement circuit according to any one of claims 1 to 4, which measures the capacitance of the backup capacitor;
A power management circuit, comprising: A method for measuring the capacitance of a capacitor,
varying the voltage of the capacitor by sourcing to or sinking from the capacitor a current proportional to a reference voltage and inversely proportional to the resistance of a first resistor;
generating a clock signal having a period inversely proportional to the reference voltage and proportional to the resistance value of the first resistor and a second resistor whose relative accuracy is ensured;
counting the time required for the voltage of the capacitor to change by a predetermined voltage width using the clock signal;
A capacitance measurement method, comprising: A method for measuring the capacitance of a capacitor,
sourcing to or sinking from the capacitor a current proportional to the reference voltage and inversely proportional to the resistance of the first resistor;
generating a clock signal having a frequency inversely proportional to the reference voltage and proportional to a resistance value of the first resistor and a second resistor whose relative accuracy is ensured;
a step of counting the clock signal by a predetermined count number with a counter;
converting the variation width of the voltage of the capacitor into a digital value by an A/D converter based on the reference voltage while the counter is counting;
A capacitance measurement method, comprising:

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