JP7269073B2 - Power control circuits, power management circuits and electronic devices - Google Patents

Description

The present invention relates to power management technology for managing and controlling a plurality of power sources.

Mobile phones, tablet terminals, notebook personal computers (PCs), desktop PCs, and game machines are equipped with microprocessors such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units) that perform arithmetic processing.

Electronic devices equipped with microprocessors have been subdivided into dozens of circuit blocks in line with the miniaturization of semiconductor manufacturing processes, the increase in the number of peripheral circuits to be mounted, and the demand for lower power consumption. can control the power supply voltage.

In such devices, power supply control circuits are used to control dozens of power supply systems corresponding to dozens of circuit blocks. A power supply control circuit is required to reliably control the on/off of a plurality of power supplies according to a predetermined sequence.

The power control circuit includes a state machine capable of transitioning between multiple states. Each state has a different combination of on and off power supplies and a different output voltage level. When a predetermined event occurs, the sequencer executes the corresponding instruction and causes the state machine to transition. The commands include turning on/off each power supply, changing the set value of the output voltage, and the like.

JP 2013-089060 A JP 2015-195690 A

Designers of electronic equipment (sets) equipped with a power control circuit want to dynamically use a state other than a predetermined state in the power control circuit.

In order to meet this demand, the present inventors have studied an architecture that can change the states of multiple power supplies (for example, on, off, and voltage levels) by register access from the outside, in addition to control by a sequencer.

For example, it is assumed that the set value of the output voltage of any power supply can be changed by external register access (user control). In this case, the following problems occur.

FIG. 1 is a diagram illustrating problems associated with user control. Consider the following two situations. For the sake of simplicity, it is assumed that there are two systems of power sources A and B, and three states S0, S1 and S2 are defined as follows.
S0 = 2 power supplies A and B off (disabled)
S1 = Only power supply A is on (enable)
S2 = both power supplies A and B on

Also, it is assumed that the ON/OFF of each of the power sources A and B and the set value of the output voltage of the power source A in the state S1 can be controlled by register access (user control). A register that specifies the output voltage of power supply A in S1 is denoted as VOUT_A1.

Prior to time _T0 is state S0. At time _T0 , when an event triggering a transition to state S1 occurs, the sequencer turns on power source A. FIG. At this time, the output voltage of the power supply A is the initial value (1.0 V) of the set value stored in the register VOUT_A1.

At time _T1 , the value of the setting register for the output voltage of power supply A is changed (1.1 V) by register access from the outside. As a result, the voltage level of the output voltage of the power supply A changes to 1.1V. This state is denoted as S1'.

At time _T2 , when an event triggering a transition to state S2 occurs, the sequencer turns on power supply B further. The voltage level of the output voltage of power supply A is changed to the set value (assumed to be 1.2 V) in state S2.

At time _T3 , an event occurs that triggers a transition from state S2 to state S1. The sequencer turns off the power supply B and changes the output voltage of the power supply A to the set value of the register VOUT_A1. Since the set value at this time is 1.1 V, the state after the transition should be S1. , S1' instead of S1, resulting in a mismatch.

In this way, when state transitions due to user control and event driving are mixed, it becomes impossible to supply the correct voltage to the load.

It is in this context that the present invention has been made, and one exemplary object of certain aspects thereof is to provide a more robust power control circuit and PMIC.

One aspect of the present invention relates to a power supply control circuit. A power supply control circuit controls the states of a plurality of power supplies. The power supply control circuit includes a non-volatile memory that stores a plurality of command groups corresponding to a plurality of events, a sequencer that executes the corresponding command group when one of the plurality of events occurs, and controls the plurality of power sources. It comprises a register block and an interface circuit for accessing the register block from the outside. The power supply control circuit is configured to be able to control a plurality of power supply states by externally changing the values of the register blocks, and to allow the sequencer to execute instructions for changing the values of the register blocks.

According to this aspect, assuming that the register value is changed by the register block from the outside, the instruction group corresponding to each event writes the value of the register back to the value expected in the post-transition state. can contain instructions. As a result, conflicts and inconsistencies between user control and sequence control due to register access can be resolved, and robustness can be enhanced.

A register block may include voltage setting registers for specifying the voltage level of a particular power supply in a particular state. The power control circuit may support commands to change the value of the voltage setting register.

The register block may include enable setting registers for specifying on/off of specific power supplies. The power control circuit may support instructions to change the value of the enable setting register.

The power supply control circuit may be configured to be switchable between a mode in which the on/off of a specific power supply is controlled based on the value of the enable setting register and a mode in which it is controlled by the sequencer. A register block may include a mode setting register for specifying a mode. The power control circuit may support instructions to change the value of the mode setting register.

The sequencer includes at least a first state in which all of the plurality of power supplies are off, a second state in which some of the plurality of power supplies are on, and a third state in which all of the plurality of power supplies are on. It may also include a state machine.

Another aspect of the invention relates to a power management circuit. A power management circuit includes a plurality of power supplies and any of the power management circuits described above for controlling the plurality of power supplies. The power management circuit may be monolithically integrated on one semiconductor substrate.

Another aspect of the invention relates to an electronic device. An electronic device includes a processor having a plurality of power supply terminals, and the power management circuit described above that supplies a power supply voltage to the plurality of power supply terminals of the processor.

Another aspect of the invention relates to an electronic device. The electronic device may include a processor having a plurality of power supply terminals and the power management circuit described above that supplies a power supply voltage to the plurality of power supply terminals of the processor.

Arbitrary combinations of the above constituent elements, and mutual replacement of the constituent elements and expressions of the present invention between methods, devices, systems, etc. are also effective as aspects of the present invention.

According to one aspect of the present invention, the robustness of the power supply control circuit and PMIC can be enhanced.

It is a figure explaining the problem accompanying user control. 2 is a block diagram of a power management circuit including the power control circuit according to Embodiment 1; FIG. 3 is a state transition diagram of the PMU of FIG. 2; FIG. It is a time chart at the time of power-on. It is a time chart when the power is turned off. It is a time chart when transitioning in the order of the third state S3-the second state S2-the third state S3. It is a time chart when user control occurs during transitions in the order of the third state S3-the second state S2-the third state S3. 3 is a block diagram of a PMIC according to Embodiment 2; FIG. FIG. 9 is a time chart for explaining the operation of the PMIC of FIG. 8; FIG. 1 is a perspective view of an electronic device including a PMIC; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

In the present specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, as well as a case in which member A and member B are electrically connected. It also includes the case where it is indirectly connected via another member that does not affect the connection state. Further, "the state in which the member C is provided between the member A and the member B" means the case where the member A and the member C or the member B and the member C are directly connected, as well as the case where the electrical connection is made. Including the case of being indirectly connected through other members that do not affect the state.

(Embodiment 1)
FIG. 2 is a block diagram of a power management circuit (hereinafter referred to as PMIC: Power Management IC) 100 including the power control circuit 200 according to the first embodiment. The PMIC 100 is a functional IC that includes a plurality (N) of power supplies 101_1 to 101_N and a power supply control circuit 200 that controls them, and their main parts are integrated on one semiconductor substrate. Some of the plurality of power supplies 101 are buck, boost or buck-boost type DC/DC converters, and some of the plurality of power supplies 101 are LDO regulators. Hereinafter, assuming that N=4, the power supplies 101_1 and 101_2 are called DCDC1 and DCDC2, and the power supplies 101_3 and 101_4 are called LDO1 and LDO2.

Note that inductors, output capacitors, switching transistors, and synchronous rectification transistors, which are component parts of the DC/DC converter, may be externally attached to the PMIC 100 . Also, the output capacitor, which is a component of the LDO regulator, may be externally attached to the PMIC 100 .

The power control circuit 200 includes a nonvolatile memory 210 , a memory 212 , a power management unit (PMU) 220 , an interface circuit 230 and a register block 240 .

The power supply control circuit 200 supports state control (user control) by register access in addition to event-driven state transition.

The nonvolatile memory 210 stores a plurality of command groups (also called sequences) corresponding to a plurality of events that trigger state transitions. The instructions are loaded into memory 212 and executable by PMU 220 .

Instructions are programmed, compiled, and written to non-volatile memory 210 by a designer during the design stage of PMIC 100 . The nonvolatile memory 210 may be a mask ROM, an OTP (One Time Programmable) ROM such as a fuse ROM (Read Only Memory) or an anti-fuse ROM, or an EPROM (Erasable Programmable Read Only Memory). may be

PMU 220 includes a sequencer and state machine. When one of a plurality of events occurs, the sequencer of PMU 220 executes the corresponding set of instructions to control the plurality of power supplies 101_1-101_N.

In the following description, the PMIC 100 is assumed to have two systems of DC/DC converters DCDC1 and DCDC2 and two systems of LDO regulators LDO1 and LDO2.

It is also assumed that the state machine of PMU 220 can take the following three states.
・First state S1
All power supplies 101_1 to 101_4 are off

・Second state S2
Power supplies 101_1 and 101_2 are on, 101_3 and 101_4 are off

・Third state S3
Power supplies 101_1 to 101_4 are all on

Note that PMU 220 may support more states.

FIG. 3 is a state transition diagram of PMU 220 of FIG. An event that triggers a transition from the i-th state Si to the j-th state Sj (i, jε(1, 2, 3), i≠j) is denoted by EVTij. Also, a group of instructions executed when transitioning from the i-th state Si to the j-th state Sj (i, j∈(1, 2, 3), i≠j) is denoted by SEQij.

Return to FIG. Register block 240 includes a plurality of registers. The register block 240 can include registers that store output voltage setting values in predetermined states for each of the plurality of power supplies 101_1 to 101_4.

In the present embodiment, register block 240 includes voltage setting registers DCDC1_VOLT_S2 and DCDC1_VOLT_S3 that store voltage setting values of DC/DC converter DCDC1 in second state S2 and third state S3.

The register block 240 includes voltage setting registers LDO1_VOLT_S3 and LDO2_VOLT_S3 that store respective voltage setting values of the LDO regulators LDO1 and LDO2 in the third state S3.

An electronic device 300 incorporating the PMIC 100 is provided with a user interface 302 and a host controller 304 . The host controller 304 is a CPU (Central Processing Unit) or a microcomputer that controls the electronic device 300 in an integrated manner. User interface 302 may include a power button, a reset button, and the like of electronic device 300 .

The user interface 302 and the host controller 304 generate events that trigger state transitions. For example, pressing the power button or reset button can be an event that triggers a state transition.

An interface circuit 230 is provided for accessing register block 240 from an external host controller 304 . Although the type of interface is not particularly limited, for example, an ^I2C (Inter IC) interface or an SPI (Serial Peripheral Interface) may be used.

The register block 240 may include a register that triggers state transition (called a trigger register). The PMU 220 monitors the register block 240 and can trigger the state transition when the host controller 304 changes the value of the trigger register (event).

The host controller 304 also knows the addresses of the voltage setting registers DCDC1_VOLT_S2, DCDC1_VOLT_S3, LDO1_VOLT_S3, and LDO2_VOLT_S3 of the register block 240, and can rewrite their values (user control).

In this manner, the power supply control circuit 200 can control the states of the plurality of power supplies 101_1 to 101_N by the external host controller 304 changing the values of the register block 240. FIG.

Next, commands supported by the power control circuit 200 will be described.

・Enable command (turn-on command)
This is an instruction to turn on each power supply after the specified time t has elapsed. Separate enable instructions may be provided for each power supply, as described herein.
・ON_DCDC1 (t0)
After t0, turn on the DC/DC converter DCDC1 (101_1) ・ON_DCDC2 (t1)
After t1, turn on the DC/DC converter DCDC2 (101_2) ・ON_LDO1 (t3)
After t3 has elapsed, turn on the LDO regulator LDO1 (101_3) ・ON_LDO2 (t4)
After t4, turn on the LDO regulator LDO2 (101_4)

・Disable instruction (turn-off instruction)
This is an instruction to turn off each power supply after the specified time has elapsed. A separate disable command may be provided for each power supply, as shown here.
・OFF_DCDC1 (t9)
After t9, turn off the DC/DC converter DCDC1 (101_1) OFF_DCDC2 (t8)
After t8, turn off the DC/DC converter DCDC2 (101_2) OFF_LDO1 (t6)
After t6, turn off the LDO regulator LDO1 (101_3) OFF_LDO2 (t5)
After t5, turn off the LDO regulator LDO2 (101_4)

It should be noted that the enable command and the disable command may be common to all power supplies, and the identification number of the power supply may be given as an argument (parameter). Alternatively, the wait time setting may be separated from the enable command and the disable command, and a separate wait command may be prepared.

- Voltage change command In this example, the voltage of the DC/DC converter DCDC1 is set separately in the second state S2 and the third state S3. Therefore, in the state transition between them, an instruction is prepared to change the voltage value of DC/DC converter DCDC1.
・CHANGE_DCDC1_S3 (t2)
After t2 has elapsed, change the output voltage of the DC/DC converter DCDC1 to the value of the voltage setting register DCDC1_VOLT_S3

・CHANGE_DCDC1_S2 (t7)
After t7, change the output voltage of the DC/DC converter DCDC1 to the value of the voltage setting register DCDC1_VOLT_S2

・Register change instruction This is an instruction to write a specified value to a specific register. A register modification instruction may be prepared for each specific register. Alternatively, a general-purpose instruction may be prepared by giving the address of the register as an argument so that the value of any register can be changed. By supporting this register change command, the power supply control circuit 200 allows the PMU 220 to change the value of the register block 240 .

The present embodiment supports instructions that change the values of the voltage setting registers DCDC1_VOLT_S2, DCDC1_VOLT_S3 and LDO1_VOLT_S3, LDO2_VOLT_S3.
・SET_DCDC1_VOLT_S2 (v1)
Change the value of DCDC1_VOLT_S2 to v1 ・SET_DCDC1_VOLT_S3 (v2)
Change the value of DCDC1_VOLT_S3 to v2 ・SET_LDO1_VOLT_S3 (v3)
Change the value of LDO1_VOLT_S3 to v3 ・SET_LDO2_VOLT_S3 (v4)
Change LDO2_VOLT_S3 value to v4

The configuration of the PMIC 100 is as described above. Next, the operation will be explained.

FIG. 4 is a time chart when power is turned on. The initial state is the first state S1 in which all power supplies are off. At time _T1 , an event occurs that triggers a transition to state S2. As a result, the instruction group SEQ12 for transitioning from state S1 to state S2 is executed. This instruction group SEQ12 includes the following instructions.

(i) SET_DCDC1_VOLT_S2 (V1)
This command ensures that the output voltage of the DC/DC converter DCDC1 is at the default set value v1 before transitioning to the second state S2.
(ii) ON_DCDC1(t0)
By this command, the DC/DC converter DCDC1 is turned on after time t0 has elapsed.
(iii) ON_DCDC2 (t1)
By this command, the DC/DC converter DCDC2 is turned on after time t1 has elapsed.
The second state S2 is entered upon completion of the execution of the instruction group SEQ12.

At time _T2 , an event occurs that triggers a transition to state S3. As a result, the instruction group SEQ23 for transitioning from state S2 to S3 is executed. This instruction group SEQ23 includes the following enable instructions.
(2) Instruction group SEQ23 when transitioning from second state S2 to third state S3
(i) SET_DCDC1_VOLT_S3 (v2)
(ii) SET_LDO1_VOLT_S3 (v3)
(iii) SET_LDO2_VOLT_S3 (v4)
These instructions ensure that the output voltages of the DC/DC converter DCDC1 and the LDO regulators LDO1 and LDO2 are at their respective default set values v2-v4 before transitioning to the third state S3.
(iv) CHANGE_DCDC1_S3 (t2)
By this command, the output voltage of DC/DC converter DCDC1 is changed to the voltage level according to DCDC1_VOLT_S3 after time t2 has elapsed.
(v) ON_LDO1(t3)
After t3 has elapsed, the LDO regulator LDO1 is turned on.
(vi) ON_LDO2(t4)
The third state S3 is entered upon completion of the execution of the instruction group SEQ23. The above is the sequence when the power is turned on.

FIG. 5 is a time chart when the power is turned off. The initial state is the third state S3 in which all power sources are on. At time _T1 , an event occurs that triggers a transition to state S2. As a result, the instruction group SEQ32 for transitioning from state S3 to S2 is executed. This instruction group SEQ32 includes the following instructions.
(i) SET_DCDC1_VOLT_S2 (v1)
This command ensures that the output voltage of the DC/DC converter DCDC1 is at the default set value v1 before transitioning to the second state S2.
(ii) OFF_LDO2 (t5)
(iii) OFF_LDO1 (t6)
These instructions turn off the LDO regulator LDO2 after time t5, and turn off the LDO regulator LDO1 after time t6.
(iv) CHANGE_DCDC1_S2 (t7)
By this command, the output voltage of DC/DC converter DCDC1 is changed to the voltage level according to DCDC1_VOLT_S2 after time t7 has elapsed.
The second state S2 is entered upon completion of execution of the instruction group SEQ32.

At time _T2 , an event occurs that triggers a transition to state S1. As a result, the instruction group SEQ21 for transitioning from state S2 to state S1 is executed. This instruction group SEQ21 includes the following instructions.
(i) OFF_DCDC2 (t8)
(ii) OFF_DCDC1 (t9)
These commands turn off the DC/DC converter DCDC2 after time t8, and then turn off the DC/DC converter DCDC1 after time t9. Upon completion of the execution of the instruction group SEQ21, the first state S1 is entered.

FIG. 6 is a time chart showing transitions in the order of the third state S3--the second state S2--the third state S3. The initial state is the third state S3. At time _T1 , an event occurs that triggers a transition to state S2. As a result, the instruction group SEQ32 for transitioning from state S3 to S2 is executed. At time _T2 , an event occurs that triggers a transition to state S3. As a result, the instruction group SEQ23 for transitioning from state S2 to S3 is executed.

FIG. 7 is a time chart when a user control occurs during transitions in the order of the third state S3-the second state S2-the third state S3. At time _T0 , the value of the voltage setting register DCDC1_VOLT_S2 is rewritten from 1.2V to 1.3V by user control (register access from the host controller 304). In response, PMU 220 changes the output voltage of DC/DC converter DCDC1 to a voltage level of 1.3 V according to DCDC1_VOLT_S2.

At time _T1 , the instruction group SEQ32 is executed, and the state transitions to the second state S2. At time _T2 , the instruction group SEQ23 is executed, and the instruction SET_DCDC1_VOLT_S2 (V1) included therein resets the value of DCDC1_VOLT_S3 to the default value of 1.2V. Then, the command CHANGE_DCDC1_S3 (t2) executed after the elapse of time t2 ensures that the output voltage of the DC/DC converter DCDC1 returns to the correct voltage value of 1.2V.

The above is the operation of the PMIC 100 . According to this PMIC 100, when the voltage value of a certain power supply is changed by user access in a certain state and then returns to the original state after transitioning to another state, the voltage value of that power supply returns to the correct state. We can guarantee that.

(Embodiment 2)
In Embodiment 1, the voltage set value could be changed by user control. Alternatively or additionally, in the second embodiment, the on/off of each power supply can be controlled by user control. FIG. 8 is a block diagram of PMIC 100A according to the second embodiment. The basic configuration of PMIC 100A is similar to that of PMIC 100 in FIG.

In the second embodiment, register block 240A includes enable setting registers USER_EN1 to USER_EN4 for specifying on/off of specific power supplies 101_1 to 101_4.

Also, for each power supply, it is possible to switch between a register control mode that switches on and off based on the value of the enable setting register USER_EN, and a PMU control mode that specifies whether to switch on and off by a control signal from the PMU 220. Mode setting registers MODE1 to MODE4 are provided for designating control modes of the power sources 101_1 to 101_4, respectively.

The PMU 220 generates control signals PMU_EN1 to PMU_EN4 that designate on/off of the plurality of power supplies 101_1 to 101_4, respectively.

The power control circuit 200A includes multiplexers 250_1 to 250_4. Multiplexer 250_# receives control signal PMU_EN# generated by PMU 220 and corresponding register USER_EN# of register block 240A, and selects one according to the value of corresponding mode setting register MODE#.

The PMIC 100A supports an instruction SET_USER_EN# for changing the value of the enable setting register USER_EN# and an instruction SET_MODE# for changing the value of the mode setting register MODE#. Any set of instructions can contain these instructions.

FIG. 9 is a time chart explaining the operation of PMIC 100A in FIG. Here, attention is focused on the operation of the power supply 101_3 (LDO1).

At time _T1 , an event occurs that triggers a transition to state S2. As a result, the instruction group SEQ32 for transitioning from state S3 to S2 is executed. The power supply 101_3 is turned off by this instruction group SEQ32.

In a subsequent second state S2, user control occurs at time _T2 to switch on power supply 101_3.

At time _T3 , an event occurs that triggers a transition to state S1. As a result, the instruction group SEQ21 for transitioning from state S2 to state S1 is executed. This instruction group SEQ21 includes instructions for resetting registers MODE3 and USER_EN3 to zero. When this reset command is executed at time _T4 , control of power supply 101_3 is transferred to PMU 220, ensuring that power supply 101_3 is turned off.

After time _T5 , the above-described activation sequence is performed, and transitions are made in order up to the third state S3.

The above is the operation of the power supply control circuit 200A. According to this power supply control circuit 200A, it is possible to prevent inconsistency between turning on and off of the power supply.

(Application)
Finally, the application of the PM controller 100 will be explained. FIG. 10 is a perspective view of electronic device 500 including PMIC 200. As shown in FIG. Electronic device 500 is, for example, a tablet terminal or a smart phone. The housing 520 houses the CPU 502 , RAM 504 , HDD 506 , battery 508 and PMIC 200 . The PMIC 200 may provide power supply voltages for the display panel 510 to its drivers, audio circuits, and the like. Note that the electronic device 500 may be a notebook PC, a console game device, a portable game device, a wearable PC, a portable audio player, a digital camera, or the like.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the scope of claims. Many modifications and changes in arrangement are permitted without departing from the spirit of the present invention.

300 electronic device 302 user interface 304 host controller 100 PMIC
101 power supply 200 power supply control circuit 210 nonvolatile memory 212 memory 220 PMU
230 interface circuit 240 register block 250 multiplexer 500 electronic device 502 CPU
504 RAM
506 HDDs
508 battery

Claims (6)

A power supply control circuit for controlling states of a plurality of power supplies,
a non-volatile memory storing a plurality of command groups corresponding to a plurality of events;
a sequencer that, upon occurrence of one of the plurality of events, executes the corresponding instruction group and controls the states of the plurality of power supplies;
a register block;
an interface circuit for accessing the register block from the outside;
with
The power supply control circuit can control the states of the plurality of power supplies by externally changing the value of the register block, and the sequencer can execute an instruction for changing the value of the register block. configured,
the register block includes a voltage setting register for specifying a voltage level of a particular power supply in a particular state;
A power control circuit, wherein the power control circuit supports an instruction to change the value of the voltage setting register. A power supply control circuit for controlling states of a plurality of power supplies,
a non-volatile memory storing a plurality of command groups corresponding to a plurality of events;
a sequencer that, upon occurrence of one of the plurality of events, executes the corresponding instruction group and controls the states of the plurality of power supplies;
a register block;
an interface circuit for accessing the register block from the outside;
with
The power supply control circuit can control the states of the plurality of power supplies by externally changing the value of the register block, and the sequencer can execute an instruction for changing the value of the register block. configured,
The register block includes an enable setting register for specifying ON/OFF of a specific power supply,
the power control circuit supports an instruction to change the value of the enable setting register;
The power supply control circuit is configured to be switchable between a mode of controlling on/off of the specific power supply based on the value of the enable setting register and a mode of being controlled by the sequencer,
the register block includes a mode setting register for specifying the mode;
A power control circuit, wherein the power control circuit supports an instruction to change the value of the mode setting register. The sequencer at least:
a first state in which all of the plurality of power sources are off;
a second state in which some of the plurality of power supplies are on;
a third state in which all of the plurality of power sources are on;
3. The power supply control circuit according to claim 1, further comprising a state machine for transitioning between. multiple power supplies;
a power supply control circuit according to any one of claims 1 to 3 , which controls states of the plurality of power supplies;
A power management circuit, comprising: 5. The power management circuit according to claim 4 , wherein the power management circuit is monolithically integrated on one semiconductor substrate. a processor having a plurality of power supply terminals;
a power management circuit according to claim 4 or 5, which supplies a power supply voltage to a plurality of power supply terminals of the processor;
An electronic device comprising:

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