JP7011981B2 - Semiconductor package and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor package, and more particularly to a semiconductor package to which a fan-out packaging technique is applied, and a method for manufacturing the same.

Electronic products require high-capacity data processing while their volumes are small. As a result, there is an increasing need to improve the degree of integration of semiconductor devices used in such electronic products. In the packaging process, in the wire bonding process, the thickness of the semiconductor package becomes thick, stacking of four or more layers is difficult, and T-topology may occur when the rewiring layer is used in two or more layers. .. As a result, recently, in the semiconductor packaging process, PLP (panel level package) technology and WLP (wafer level package) technology for improving the degree of integration and cost have been researched and developed.

Japanese Patent Application Laid-Open No. 2014-096496

An object to be solved by the present invention is to apply a fan-out packaging technique to provide a semiconductor package including a stack structure and a method for manufacturing the same.

A semiconductor package according to one aspect of the technical idea of the present invention for achieving the above-mentioned object includes one or more first semiconductor chips having a first surface to which one or more first pads are exposed. A first layer and a second layer comprising one or more second semiconductor chips arranged in a first direction on top of the first layer and having a second surface with one or more second pads exposed. A first rewiring layer arranged between the first layer and the second layer and electrically connected to the one or more first pads is included, and the first layer is the first layer. The one or more first semiconductor chips and the one, including one or more first TPV (throwpanel via) penetrating in the first direction and electrically connected to the first rewiring layer. The one or more second semiconductor chips are arranged such that the first surface and the second surface face each other with the first rewiring layer interposed therebetween, and the one or more second pads face each other. The first semiconductor chip and the second semiconductor chip are electrically connected to the first rewiring layer, and the first semiconductor chip and the second semiconductor chip are arranged so as to face each other while being symmetrical with respect to the first rewiring layer. It is characterized by sharing a rewiring layer .

A semiconductor package according to another aspect of the technical idea of the present invention includes a first semiconductor chip having a first surface on which one or more first pads are exposed, and a first accommodating portion for accommodating the first semiconductor chip. The first panel provided and the first layer containing one or more first TPVs penetrating the first panel in the first direction are laminated on the first layer in the first direction, and the one or more are laminated. A first pad, a first rewiring layer electrically connected to the one or more first TPV, and one or more second pads laminated on the first rewiring layer in the first direction. A second semiconductor chip having an exposed second surface, a second layer including a second panel including a second accommodating portion for accommodating the second semiconductor chip, the first accommodating portion and the second accommodating portion. The accommodating portion is arranged symmetrically with respect to the first rewiring layer, and the one or more second pads are electrically connected to the first rewiring layer, and the first semiconductor chip and the said. The second semiconductor chip is characterized in that it is arranged so as to face each other while being symmetrical with respect to the first rewiring layer and shares the first rewiring layer .

A method of manufacturing a semiconductor package according to still another aspect of the technical idea of the present invention is a method of manufacturing a semiconductor package, wherein the first panel has one or more first semiconductor chips having a first surface to which one or more first pads are exposed. And one having a step of forming a first layer by arranging one or more first TPVs penetrating the first panel and a second surface of the second panel to which one or more second pads are exposed. By arranging two or more second semiconductor chips, a step of forming a second layer, a first pad electrically connected to the one or more first pads on the first layer, and a first TPV. The first step includes a step of forming a rewiring layer and a step of forming a first stack structure by laminating the second layer on the first rewiring layer in the first direction . The step of forming the one-stack structure includes a step of laminating the second layer so that the first surface and the second surface face each other so as to sandwich the first rewiring layer. The first semiconductor chip and the second semiconductor chip are arranged so as to face each other while being symmetrical with respect to the first rewiring layer, and share the first rewiring layer .

A semiconductor package according to still another aspect of the technical idea of the present invention is a first semiconductor chip having a first surface on which one or more first pads are exposed, and a first accommodating portion for accommodating the first semiconductor chip. A first panel comprising, and a first layer containing one or more first TPVs that vertically penetrate the first panel, and one or more first layers arranged vertically on the first layer. A first rewiring layer electrically connected to one pad and one or more first TPVs is vertically laminated on the first rewiring layer and electrically connected to the first rewiring layer. A second semiconductor chip having a second surface on which one or more second pads to be connected are exposed, a second panel provided with a second accommodating portion for accommodating the second semiconductor chip, and the second panel vertically. The first rewiring layer includes a second layer including a second TPV that penetrates in the direction and is electrically connected to the first rewiring layer, and the first semiconductor chip and the second semiconductor chip are the first rewiring layer. It is characterized in that it is arranged so as to face each other while forming symmetry with respect to the above, and shares the first rewiring layer .

The semiconductor package according to the technical idea of the present invention and the manufacturing method thereof are thin and not limited to the number of layers by electrically connecting the chips by using the TPV and the rewiring layer without wire bonding. Can embody a semiconductor package.

Further, the semiconductor package according to the technical idea of the present invention and the manufacturing method thereof are semiconductors in which signal integrity is improved by having a structure in which a plurality of laminated semiconductor chips share a rewiring layer. We can provide packages.

Further, the semiconductor package according to the technical idea of the present invention and the manufacturing method thereof can realize the stack package even in the rewiring step for a relatively small number of semiconductor chips.

It is a drawing for demonstrating the structure of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the structure of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the structure of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the structure of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a cross-sectional view which enlarged and illustrated a part of the semiconductor package by an exemplary embodiment of this invention. It is a drawing which illustrates the cross-sectional structure of the semiconductor package by an exemplary embodiment of this invention. It is a drawing which illustrates the cross-sectional structure of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing for demonstrating the manufacturing process of the semiconductor package by an exemplary embodiment of this invention. It is a drawing which illustrates the semiconductor package by the exemplary embodiment of this invention. It is a block diagram schematically illustrating an electronic system including a semiconductor package according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
1 and 2 are drawings for explaining the structure of a semiconductor package according to an exemplary embodiment of the present invention. Specifically, FIG. 1 shows a cross-sectional structure of a semiconductor package, and FIG. 2 shows a cross-sectional view in which a part of FIG. 1 is enlarged. FIG. 2 is an enlarged cross-sectional view of the A portion of the semiconductor package 100 shown in FIG.

Referring to FIG. 1, the semiconductor package 100 includes a solder ball SB, a first layer L1 and a second layer L2, a first rewired layer RDL1 and a second rewiring layer RDL2. The first layer L1 includes one or more first semiconductor chips 110 and one or more first TPV (throw panel via) TPV1s. Further, the first layer L1 includes a first panel PNL1 including a first accommodating portion AC1 in which the first semiconductor chip 110 is accommodated.

The second layer L2 includes one or more second semiconductor chips 120 and one or more second TPV TPV2. Further, the second layer L2 includes a second panel PNL2 including a second accommodating portion AC2 in which the second semiconductor chip 120 is accommodated.

The first semiconductor chip 110 includes one or more first pads 111. In an exemplary embodiment, the first semiconductor chip 110 has a first surface F1 to which one or more first pads 111 are exposed. For example, the first pad 111 is exposed via the first surface F1 and is electrically connected to the first rewiring layer RDL1.
The second semiconductor chip 120 includes one or more second pads 121. In an exemplary embodiment, the second semiconductor chip 120 has a second surface F2 to which one or more second pads 121 are exposed. For example, the second pad 121 is exposed via the second surface F2 and is electrically connected to the second rewiring layer RDL2.

In an exemplary embodiment, the first pad 111 and the second pad 121 may include metal. For example, the first pad 111 and the second pad 121 are also plated pads, and may contain any one of Au, Ni / Au, and Ni / Pd / Au.

The first semiconductor chip 110 and the second semiconductor chip 120 are, for example, non-volatile memory devices, and more specifically, an EEPROM (electrically erasable programmable read-only memory), a flash memory, a phase change memory (PRAM), and a resistor. Memory (RRAM (registered trademark)), strong dielectric memory (FeRAM), solid magnetic memory (MRAM), polymer RAM (PoRAM), nanofloating gate memory (NFGM), molecular electronic memory element, insulation It is also a resistance change memory, but is not limited to them.

Further, the first semiconductor chip 110 and the second semiconductor chip 120 are also, for example, volatile memories, and more specifically, DRAM (dynamic random access memory), SRAM (static random access memory), and SDRAM (synchronous dynamic random). Access memory), RRAM (Rambos dynamic random access memory), etc., but are not limited thereto. Further, the first semiconductor chip 110 and the second semiconductor chip 120 are also logic chips, and as an example, they are also a controller that controls a memory chip.

The first semiconductor chip 110 and the second semiconductor chip 120 are both the same semiconductor chip and different semiconductor chips from each other. When the first layer L1 (or the second layer L2) includes a plurality of first semiconductor chips 110 (or second semiconductor chips 120), the plurality of first semiconductor chips 110 (or second semiconductor chips 120) are included. Some of the 120) are the same semiconductor chips, and the remaining semiconductor chips are also different semiconductor chips. The plurality of first semiconductor chips 110 (or second semiconductor chips 120) are adjacent to or in contact with each other along the second direction (Y) and the third direction (Z), and the first layer L1 (or the second layer) It is arranged in L2).

The first TPV TPV1 penetrates the first layer L1 in the first direction (X), and is electrically connected to the solder ball SB on one side and the first rewiring layer RDL1 on the other side. Further, the second TPV TPV2 penetrates the second layer L2 in the first direction (X), and one side is electrically connected to the first rewiring layer RDL1 and the other side is electrically connected to the second rewiring layer RDL2. .. The solder ball SB is electrically connected to the first rewiring layer RDL1 via the first TPV TPV1, and the first rewiring layer RDL1 is electrically connected to the second rewiring layer RDL2 via the second TPV TPV2. Will be done.

In an exemplary embodiment, the first TPV TPV1 and the second TPV TPV2 include at least one of copper (Cu) and tungsten (W). For example, the first TPV TPV1 and the second TPV TPV2 are copper (Cu), copper tin (CuSn), copper magnesium (CuMg), copper nickel (CuNi), copper zinc (CuZn), copper lead (CuPd), and copper gold (CuAu). ), Copper Renium (CuRe), Copper Tungsten (CuW) and Tungsten (W) alloys, but are not limited thereto. For example, the first TPV TPV1 and the second TPV TPV2 are formed by at least one of the steps of electroless plating, electroplating, sputtering and printing.

The first panel PNL1 accommodates one or more first semiconductor chips 110 via one or more first accommodating portions AC1. Further, the second panel PNL2 accommodates one or more second semiconductor chips 120 via one or more second accommodating portions AC2.

In an exemplary embodiment, the first panel PNL1 and the second panel PNL2 may include an insulating substrate. The insulating substrate may contain an insulating material, for example silicon, glass, ceramic, plastic or polymer. The first panel PNL1 and the second panel PNL2 are embodied in a flat plate shape, and are embodied in various shapes such as a circle or a polygon.

The first rewiring layer RDL1 is laminated in the first direction (X) on the first layer L1, and the second layer L2 is laminated in the first direction (X) on the first rewiring layer RDL1. In other words, the first rewiring layer RDL1 is arranged between the first layer L1 and the second layer L2. Further, the second rewiring layer RDL2 is laminated on the second layer L2 in the first direction (X).

The first rewiring layer RDL1 and the second rewiring layer RDL2 contain a conductive substance. The conductive substance may contain a metal, for example, copper (Cu), a copper alloy, aluminum (Al) or an aluminum alloy. The first rewiring layer RDL1 and the second rewiring layer RDL2 are laminated on the first layer L1 and the second layer L2, respectively, via, for example, a rewiring step.

The first rewiring layer RDL1 and the second rewiring layer RDL2 form rewiring patterns on the first layer L1 and the second layer L2, respectively, thereby miniaturizing the input / output terminals of the semiconductor chips 110 and 120. Increase the number of input / output terminals to enable a fan-out structure. Further, the first rewiring layer RDL1 and the second rewiring layer RDL2 form a rewiring pattern on the first layer L1 and the second layer L2, respectively, to enable a fan-out structure, thereby achieving high performance and high performance. It embodies a semiconductor package 100 that is advantageous for high-speed signal processing.

Further referring to FIG. 2, the first TPV TPV1 and the first rewiring layer RDL1 and the first rewiring layer RDL1 and the second TPV TPV2 are physically / electrically connected, respectively. For example, the upper surface of the first TPV TPV1 comes into contact with the lower surface of the first rewiring layer RDL1. In an exemplary embodiment, the top surface of the first TPV TPV1 forms substantially the same plane as the bottom surface of the first rewiring layer RDL1.

Further, the lower surface of the second TPV TPV2 comes into contact with the upper surface of the first rewiring layer RDL1. In an exemplary embodiment, the lower surface of the second TVPTPV2 forms substantially the same plane as the upper surface of the first rewiring layer RDL1.

The semiconductor package according to the technical idea of the present invention can electrically connect semiconductor chips by using TPV and a rewiring layer without wire bonding. For example, the first semiconductor chip 110 is electrically connected to each other via the first rewiring layer RDL1. Further, the first semiconductor chip 110 and the second semiconductor chip 120 are electrically connected to each other via the first rewiring layer RDL1, the second TPV TPV2, and the second rewiring layer RDL2. Further, the first semiconductor chip 110 and the second semiconductor chip 120 are electrically connected to the outside via the solder ball SB. Thereby, it is possible to have a thin thickness without being limited to the number of layers.

3 to 6 show enlarged cross sections of a part of a semiconductor package according to an exemplary embodiment of the present invention. For example, FIGS. 3 to 6 show examples of the A portion of the semiconductor package 100 of FIG. 1, respectively.

Referring to FIG. 3, the bump BP_V is arranged between the first rewiring layer RDL1 and the second TPV TPV2. Although one bump is shown in FIG. 3, the number of bumps is not limited thereto. The bump is also named a ball. For example, bump BP_V may include an alloy containing Cu, Au, Ni, Al, Ag, or one or more of those metals. As a result, the first rewiring layer RDL1 and the second TPV TPV2 are electrically connected to each other via the bump BP_V. The cross section of the bump BP_V is, for example, circular, but is not limited thereto.

Referring to FIG. 4, the second TPV TPV2 includes a protrusion WDV_b projecting towards the first rewiring layer RDL1. Further, the first rewiring layer RDL1 includes a groove GV_b coupled to the protrusion WDV_b. In an exemplary embodiment, the cross-sectional shape of the protrusion WDV_b and the groove GV_b is rectangular. Hereinafter, in FIGS. 4 to 6, the protrusions and the grooves connected to the protrusions are shown one by one, but the number of the protrusions and the grooves is not limited thereto.

Referring to FIG. 5, the second TPV TPV2 includes a protrusion WDV_c that projects toward the first rewiring layer RDL1. Further, the first rewiring layer RDL1 includes a groove GV_c coupled to the protrusion WDV_c. In an exemplary embodiment, the lower surface of the overhang WDV_c has a convex profile towards the first rewiring layer RDL1. In other words, the first rewiring layer RDL1 includes a groove GV_c comprising a lower surface having a concave profile towards the second TPV TPV2 so as to be coupled to a protrusion WDV_c having a convex profile.

Referring to FIG. 6, the second TPV TPV2 includes a protrusion WDV_d that projects toward the first rewiring layer RDL1. Further, the first rewiring layer RDL1 includes a groove GV_d coupled to the protrusion WDV_d. In an exemplary embodiment, the cross-sectional shape of the protrusion WDV_d and the groove GV_d is triangular.

7 and 8 are drawings for explaining the structure of a semiconductor package according to an exemplary embodiment of the present invention. Specifically, FIG. 7 shows a cross-sectional structure of a semiconductor package, and FIG. 8 shows a cross-sectional view showing a part of FIG. 7 in an enlarged view. For example, FIG. 8 is an enlarged cross section of the B portion in the semiconductor package 200 shown in FIG. 7. In the configurations disclosed in FIGS. 7 and 8, comparison with FIGS. 1 and 2 and overlapping explanations are avoided.

Referring to FIG. 7, the semiconductor package 200 includes a solder ball SB, a first layer L1 and a second layer L2, and a first rewiring layer RDL1. The first rewiring layer RDL1 is arranged between the first layer L1 and the second layer L2, and the solder ball SB is electrically connected to the first rewiring layer RDL1 via the first TPV TPV1.

In an exemplary embodiment, in the first semiconductor chip 210 and the second semiconductor chip 220, the first surface F1 and the second surface F2 sandwich the first rewiring layer RDL1 and face-to-face with each other. Arranged to face each other. Alternatively, the first panel PNL1 and the second panel PNL2 are arranged so that the first accommodating portion AC1 and the second accommodating portion AC2 face each other with the first rewiring layer RDL1 interposed therebetween. Alternatively, the first layer L1 and the second layer L2 are arranged so that the first semiconductor chip 210 and the second semiconductor chip 220 face each other while forming symmetry with respect to the first rewiring layer RDL1. As a result, the first semiconductor chip 210 and the second semiconductor chip 220 share the first rewiring layer RDL1.

In another exemplary embodiment, the second rewiring layer is also arranged on the second layer L2. Further, a third layer containing one or more semiconductor chips and / or one or more TPVs may be further formed on the second rewiring layer.

Further referring to FIG. 8, the second pad 221 and the first rewiring layer RDL1 are physically / electrically connected. In an exemplary embodiment, the lower surface of the second pad 221 contacts the upper surface of the first rewiring layer RDL1. Further, the second surface F2 of the second semiconductor chip 220 comes into contact with the upper surface of the first rewiring layer RDL1. For example, the lower surface of the second pad 221 forms substantially the same plane as the second surface F2.

The semiconductor package according to the technical idea of the present invention can electrically connect the chips by using the TPV and the rewiring layer without wire bonding. Thereby, it is possible to have a thin thickness without being limited to the number of layers. Further, by having a structure in which a plurality of stacked semiconductor chips share a rewiring layer, signal integrity is improved. Further, the stack structure can be realized even in the rewiring step for a relatively small number of semiconductor chips.

9 to 12 show enlarged cross sections of a part of a semiconductor package according to an exemplary embodiment of the present invention. For example, FIGS. 9 to 12 illustrate each embodiment for the B portion of the semiconductor package 200 of FIG. 7.

With reference to FIG. 9, the bump BP_P may be arranged between the first rewiring layer RDL1 and the second pad 221_a. Although one bump is shown in FIG. 9, the number of the bumps is not limited thereto. For example, the bump BP_P may include an alloy containing Cu, Au, Ni, Al, Ag, or one or more of those metals. As a result, the first rewiring layer RDL1 and the second pad 221_a are electrically connected to each other via the bump BP_P.

Referring to FIG. 10, the second pad 221_b includes a protrusion WDP_b that projects toward the first rewiring layer RDL1. Further, the first rewiring layer RDL1 includes a groove GR_b coupled to the protrusion WDP_b. In an exemplary embodiment, the cross-sectional shape of the protrusion WDP_b and the groove GR_b is rectangular. By inserting the protrusion WDP_b into the groove GR_b, the second surface F2 comes into contact with the upper surface of the first rewiring layer RDL1. Hereinafter, in FIGS. 10 to 12, the protrusion and the groove connected to the protrusion are shown one by one, but the number of the protrusion and the groove is not limited thereto.

Referring to FIG. 11, the second pad 221_c includes a protrusion WDP_c that projects toward the first rewiring layer RDL1. Further, the first rewiring layer RDL1 includes a groove GR_c coupled to the protrusion WDP_c. In an exemplary embodiment, the lower surface of the overhang WDP_c has a convex profile towards the first rewiring layer RDL1. In other words, the first rewiring layer RDL1 includes a groove GR_c having a lower surface with a concave profile towards the second pad 221_c so as to be coupled to a protrusion WDP_c with a convex profile. By inserting the protrusion WDP_c into the groove GR_c, the second surface F2 comes into contact with the upper surface of the first rewiring layer RDL1.

Referring to FIG. 12, the second pad 221_d includes a protrusion WDP_d that projects toward the first rewiring layer RDL1. Further, the first rewiring layer RDL1 includes a groove GR_d coupled to the protrusion WDP_d. In an exemplary embodiment, the cross-sectional shape of the protrusion WDP_d and the groove GR_d is triangular. By inserting the protrusion WDP_d into the groove GR_d, the second surface F2 comes into contact with the upper surface of the first rewiring layer RDL1.

FIG. 13 illustrates a cross-sectional structure of a semiconductor package according to an exemplary embodiment of the present invention.
Referring to FIG. 13, the semiconductor package 300 includes a solder ball SB, a first stack structure ST_1 and a second stack structure ST_1. The second stack structure ST_1 is laminated on the first stack structure ST_1 in the first direction (X).

The first stack structure ST_1 includes a first layer L1, a first rearranged layer RDL1 laminated on the first layer L1, and a second layer L2 laminated on the first rearranged layer RDL1. The first layer L1 includes a first panel PNL1 including one or more first semiconductor chips 310, a first TPV TPV1 penetrating the first layer L1, and a first accommodating portion AC1 in which the first semiconductor chip 310 is accommodated. include. Further, the second layer L2 includes a second panel including a second semiconductor chip 320, a second TPV TPV2 penetrating the second layer L2, and a second accommodating portion AC2 in which the second semiconductor chip 320 is accommodated. Includes PNL2.

The first semiconductor chip 310 has a first surface F1 to which the first pad 311 is exposed, and the second semiconductor chip 320 has a second surface F2 to which the second pad 321 is exposed. In an exemplary embodiment, the first semiconductor chip 310 and the second semiconductor chip 320 are arranged such that the first surface F1 and the second surface F2 face each other with the first rewiring layer RDL1 interposed therebetween. .. Alternatively, the first panel PNL1 and the second panel PNL2 are arranged so that the first accommodating portion AC1 and the second accommodating portion AC2 face each other with the first rewiring layer RDL1 interposed therebetween. Alternatively, the first layer L1 and the second layer L2 are also arranged such that the first semiconductor chip 310 and the second semiconductor chip 320 face each other while forming symmetry with respect to the first rewiring layer RDL1. As a result, the first semiconductor chip 310 and the second semiconductor chip 320 share the first rewiring layer RDL1.

The second stack structure ST_2 includes a third layer L3, a second rearranged layer RDL2 laminated on the third layer L3, and a fourth layer L4 laminated on the second rearranged layer RDL2. The third layer L3 includes a third panel PNL3 including one or more third semiconductor chips 330, a third TPV TPV3 penetrating the third layer L3, and a third accommodating portion AC3 in which the third semiconductor chip 330 is accommodated. include. Further, the fourth layer L4 includes a fourth panel including a fourth semiconductor chip 340, a fourth TPV TPV4 penetrating the fourth layer L4, and a fourth accommodating portion AC4 in which the fourth semiconductor chip 340 is accommodated. Includes PNL4.

The third semiconductor chip 330 has a third surface F3 from which the third pad 331 is exposed, and the fourth semiconductor chip 340 has a fourth surface F4 from which the fourth pad 341 is exposed. In an exemplary embodiment, the third semiconductor chip 330 and the fourth semiconductor chip 340 are arranged such that the third surface F3 and the fourth surface F4 face each other with the second rewiring layer RDL2 interposed therebetween. .. Alternatively, the third panel PNL3 and the fourth panel PNL4 are arranged so that the third accommodating portion AC3 and the fourth accommodating portion AC4 face each other with the second rewiring layer RDL2 interposed therebetween. Alternatively, the third layer L3 and the fourth layer L4 are arranged so that the third semiconductor chip 330 and the fourth semiconductor chip 340 face each other while forming symmetry with respect to the second rewiring layer RDL2. As a result, the third semiconductor chip 330 and the fourth semiconductor chip 340 share the second rewiring layer RDL2.

In other words, the arrangement of each configuration included in the second stack structure ST_1 is similar to the arrangement of each configuration included in the first stack structure ST_1. Further, the second TPV TPV2 and the third TPV TPV3 are electrically connected. Although not shown in FIG. 13, for example, a bump containing a conductive substance, a protrusion, or the like may be arranged between the second TPV TPV2 and the third TPV TPV3.

In other words, the semiconductor chips 310, 320, 330, 340 included in the first stack structure ST_1 and the second stack structure ST_2 are signals of various types to each other via the electrical connection between the second TPV TPV2 and the third TPV TPV3. To send and receive. When the solder ball SB is electrically connected to the outside of the semiconductor package 300, the semiconductor chips 310, 320, 330, and 340 transmit and receive various signals to and from the outside of the semiconductor package 300.

FIG. 14 illustrates a cross-sectional structure of a semiconductor package according to an exemplary embodiment of the present invention.
Referring to FIG. 14, the semiconductor package 400 includes a solder ball SB, a first stack structure ST_1a, a second stack structure ST_2a and a first rewiring layer RDL1a. The second stack structure ST_2a is arranged in the first direction (X) on the upper part of the first stack structure ST_1a. The first rewiring layer RDL1a is arranged between the first stack structure ST_1a and the second stack structure ST_2a.

The first stack structure ST_1a includes a first layer L1a and a second layer L2a laminated on the first layer L1a. The first layer L1a includes a first panel PNL1a including one or more first semiconductor chips 410, a first TPV TPV1 penetrating the first layer L1a, and a first accommodating portion AC1_a in which the first semiconductor chip 410 is accommodated. include. Further, the second layer L2a includes a second panel including a second semiconductor chip 420, a second TPV TPV2 penetrating the second layer L2a, and a second accommodating portion AC2_a in which the second semiconductor chip 420 is accommodated. Includes PNL2a.

In an exemplary embodiment, the first accommodating portion AC1_a and the first panel PNL1a have the same height in the first direction (X). Further, the second accommodating portion AC2_a and the second panel PNL2a have the same height in the first direction (X). That is, the first semiconductor chip 410 and the second semiconductor chip 420 are accommodated in the first accommodating portion AC1_a and the second accommodating portion AC2_a, respectively, and have the same height in the first direction (X) as the first panel PNL1a and the second panel PNL2a. Has a height.

In an exemplary embodiment, the first stack structure ST_1a comprises one or more TSVs (Through Silicon Vias). Specifically, the first stack structure ST_1a includes one or more first TSV TSV1s that penetrate the first stack structure ST_1a in the first direction (X).

For example, the first TSV TSV1 penetrates the first semiconductor chip 410 and the second semiconductor chip 420. Alternatively, when the second semiconductor chip 420 includes a pad (not shown) exposed on the second surface F2, the first TSV TSV1 moves in the first direction (X) from the pad exposed on the second surface F2. It is extended and penetrates the first semiconductor chip 410 and the second semiconductor chip 420.

For example, the first TSV TSV1 contains a conductive substance. The conductive substance may contain a metal, for example, copper (Cu), copper tin (CuSn), copper magnesium (CuMg), copper nickel (CuNi), copper zinc (CuZn), copper lead (CuPd), copper. It includes, but is not limited to, at least one of gold (CuAu), copper renium (CuRe), copper tungsten (CuW), tungsten (W) and tungsten (W) alloys. Although not shown, the first TSV TSV1 may include a conductive plug and a via insulating film surrounding the conductive plug. The via insulating film includes, for example, an oxide film, a nitride film, a carbonized film, a polymer film, or a combination thereof.

The second stack structure ST_2a includes a third layer L3a and a fourth layer L4a laminated on the third layer L3a. The third layer L3a includes a third panel PNL3a including one or more third semiconductor chips 430, a third TPV TPV3 penetrating the third layer L3a, and a third accommodating portion AC3_a in which the third semiconductor chip 430 is accommodated. include. Further, the fourth layer L4a includes a fourth panel including a fourth semiconductor chip 440, a fourth TPV TPV4 penetrating the fourth layer L4a, and a fourth accommodating portion AC4_a in which the fourth semiconductor chip 440 is accommodated. Includes PNL4a.

In an exemplary embodiment, the third containment AC3_a and the third panel PNL3a have the same height in the first direction (X). Further, the fourth accommodating portion AC4_a and the fourth panel PNL4a have the same height in the first direction (X). That is, the third semiconductor chip 430 and the fourth semiconductor chip 440 are accommodated in the third accommodating portion AC3_a and the fourth accommodating portion AC4_a, respectively, and have the same height as the third panel PNL3a and the fourth panel PNL4a in the first direction (X). Has a height.

In an exemplary embodiment, the second stack structure ST_2a comprises one or more TSVs. Specifically, the second stack structure ST_2a includes one or more second TSV TSV2s that penetrate the second stack structure ST_2a in the first direction (X).

For example, the second TSV TSV2 penetrates the third semiconductor chip 430 and the fourth semiconductor chip 440. Alternatively, when the third semiconductor chip 430 includes a pad (not shown) exposed on the third surface F3, the second TSV TSV2 moves in the first direction (X) from the pad exposed on the third surface F3. It is extended and penetrates the third semiconductor chip 430 and the fourth semiconductor chip 440.

In an exemplary embodiment, the arrangement of each configuration included in the second stack structure ST_1a is similar to the arrangement of each configuration included in the first stack structure ST_1a. Further, the first TSV TSV1 and the second TSV TSV2 are electrically connected to the first rewiring layer RDL1a, respectively. Although not shown in FIG. 14, for example, a bump containing a conductive substance, a protrusion, or the like may be arranged between the second TSV TSV2 and the first rewiring layer RDL1a.

In other words, the semiconductor chips 410, 420, 430, and 440 included in the first stack structure ST_1a and the second stack structure ST_2a are the TSV TSV1, TSV2 and the first rewiring layer RDL1a contained in the chips, respectively. Various signals are transmitted and received from each other via electrical connection. When the solder ball SB is electrically connected to the outside of the semiconductor package 400, the semiconductor chips 410, 420, 430, and 440 transmit and receive various signals to and from the outside of the semiconductor package 400.

15 to 18 are drawings for explaining a manufacturing process of a semiconductor package according to an exemplary embodiment of the present invention. Specifically, FIG. 15 illustrates a flowchart of a process process of a semiconductor package according to an exemplary embodiment of the present invention, and FIGS. 16 to 18 show an example according to each stage of FIG. 15 to 18 show, for example, a manufacturing process relating to a part of the semiconductor package 300 of FIG.

With reference to FIGS. 15 to 18, semiconductor chips 310, 320 and TPV TPV1 and TPV2 can be arranged on the first panel PNL1 and the second panel PNL2, respectively, to form the first layer L1 and the second layer L2 (S10). ). For example, each of the first panel PNL1 and the second panel PNL2 is a part of a panel different from each other, or a part different from each other contained in the same panel.

In an exemplary embodiment, the first layer L1 and / or the second layer L2 is formed on the basis of a wafer level package (WLP) step. Also, in an exemplary embodiment, the first layer L1 and / or the second layer L2 is also formed based on a panel level package (PLP) step.

In the present embodiment, the TPV TPV1 and TPV2 are arranged on the first panel PNL1 and the second panel PNL2, but the present invention is not limited thereto. That is, for example, the TPV may not be arranged on the second panel PNL2.

In an exemplary embodiment, the first TPV TPV1 and the second TPV TPV2 are arranged in the first panel PNL1 and the second panel PNL2, respectively, and the first storage unit AC1 and the second storage unit AC1 for accommodating the first semiconductor chip 310 and the second semiconductor chip 320, respectively. The second accommodating portion AC2 is formed. For example, the first accommodating portion AC1 and the second accommodating portion AC2 are also formed through a cavity generation step for the first panel PNL1 and the second panel PNL2. After the first accommodating portion AC1 and the second accommodating portion AC2 are formed, the semiconductor chips 310 and 320 are arranged in the accommodating portions AC1 and AC2. For example, the first semiconductor chip 310 has a first surface F1 to which one or more first pads 311 are exposed. Further, the second semiconductor chip 320 has a second surface F2 to which one or more second pads 321 are exposed.

Next, the first rewiring layer RDL1 is formed on the first layer L1 (S20). In an exemplary embodiment, the first rewiring layer RDL1 is electrically coupled to the first pad 311 and the first TPV TPV1. For example, the first rewiring layer RDL1 is formed through various vapor deposition steps such as sputtering, electroplating, electroless plating or printing.

Next, the first stack structure ST_1 is formed by laminating the second layer L2 on the first rewiring layer RDL1 in the first direction (x) (S30). In an exemplary embodiment, the first rewiring layer RDL1 is sandwiched, and the second layer L2 is laminated on the first rewiring layer RDL1 so that the first surface F1 and the second surface F2 face each other face to face. .. As a result, the first rewiring layer RDL1 is electrically connected to the first pad 311 and the second pad 321. For example, when the first layer L1 and the second layer L2 have the same configuration, the first layer L1 and the second layer L2 are symmetrical with respect to the first rewiring layer RDL1.

In an exemplary embodiment, the upper surface of the first rewiring layer RDL1 electrically connected to the second pad 321 is provided on the same plane as the lower surface of the second pad 321. In another exemplary embodiment, the second pad 321 comprises one or more protrusions projecting towards the first rewiring layer RDL1, and the first rewiring layer RDL1 is coupled to one or more protrusions. Contains one or more grooves to be. In yet another exemplary embodiment, one or more bumps are arranged between the second pad 321 and the first rewiring layer RDL1.

Further, in the exemplary embodiment, the upper surface of the first rewiring layer RDL1 electrically connected to the second TPV TPV2 is provided on the same plane as the lower surface of the second TPV TPV2. In another exemplary embodiment, the second TPV TPV2 comprises one or more protrusions projecting towards the first rewiring layer RDL1, and the first rewiring layer RDL1 is coupled to one or more protrusions. Includes one or more grooves. In yet another exemplary embodiment, one or more bumps are arranged between the second TPV TPV2 and the first rewiring layer RDL1.

19 to 22 are drawings for explaining a manufacturing process of a semiconductor package according to an exemplary embodiment of the present invention. Specifically, FIG. 19 illustrates a flowchart of a process process of a semiconductor package according to an exemplary embodiment of the present invention, and FIGS. 20 to 22 show an example according to each stage of FIG. 19 to 22 show, for example, the manufacturing process according to the semiconductor package 300 of FIG.

With reference to FIGS. 19 to 22, the first stack structure ST_1 and the second stack structure ST_1 are combined (S40). For example, the second stack structure ST_1 is laminated on the first stack structure ST_1 in the first direction (X).

In an exemplary embodiment, the second stack structure ST_1 is the same as, or has a similar structure to, the first stack structure ST_1 by a similar process. It may be included. For example, the second stack structure ST_2 is placed on the second rewiring layer RDL2 and the second rewiring layer RDL2 laminated in the first direction (X) on the third layer L3 and the third layer L3. The fourth layer L4 laminated in one direction (X) is included. The third layer L3 and the fourth layer L4 include a third semiconductor chip 330 and a fourth semiconductor chip 340, and a third TPV TPV3 and a fourth TPV TPV4, respectively.

In an exemplary embodiment, the third surface F3 of the third semiconductor chip 330 and the fourth surface F4 of the fourth semiconductor chip 340 sandwich the second rewiring layer RDL2 and face each other so as to face each other. The four layers L4 are laminated on the second rewiring layer RDL2. As a result, the second rewiring layer RDL2 is electrically connected to the third pad 331 of the third semiconductor chip 330 and the fourth pad 341 of the fourth semiconductor chip 340. For example, when the third layer L3 and the fourth layer L4 include the same configuration, the third layer L3 and the fourth layer L4 are symmetrical with respect to the second rewiring layer RDL2.

Next, a laminating step for the structure to which the first stack structure ST_1 and the second stack structure ST_2 are combined is performed (S50). For example, heat and pressure are applied to the structure in which the first stack structure ST_1 and the second stack structure ST_2 are combined so that the second stack structure ST_1 is attached onto the first stack structure ST_1. Perform the laminating process.

Further, in the exemplary embodiment, the first insulating layer IL1 is formed on the second stack structure ST_2. The first insulating layer IL1 is formed from, for example, an oxide layer, a nitride layer, a polymer layer, or a combination layer thereof.

Next, one or more solder balls SB are joined to the first stack structure ST_1 (S60). For example, the solder ball SB is joined to a part of the lower surface of one or more first TPV TPV1 exposed to the outside. The solder ball SB also serves as, for example, an electrical connection passage between the first stack structure ST_1 and the second stack structure ST_1 and an external chip or device.

FIG. 23 illustrates a semiconductor package according to an exemplary embodiment of the invention. In the configuration disclosed in FIG. 23, a duplicate description is avoided as compared with FIG.

Referring to FIG. 23, the semiconductor package 400 has a third rewiring layer RDL3, a third rewiring layer laminated in the first direction (X) on the solder balls SB1 and SB2, the fifth panel PNL5, and the fifth panel PNL5. Further includes a fifth semiconductor chip 450 electrically connected via the wiring layer RDL3 and the fifth pad 451 and a molding layer MD covering the fifth semiconductor chip. Further, the semiconductor package 400 penetrates the molding layer MD and penetrates the solder ball SB1 and the fifth TPV TPV5 and the fifth panel PNL5 which are electrically connected to the solder ball SB1 and the third rewiring layer RDL3, and penetrates the third rewiring layer RDL3 and the third rewiring layer RDL3. It further comprises a sixth TPV TPV6 that is electrically coupled to the solder ball SB2.

The molding layer MD molds the fifth semiconductor chip 450. Fifth TPV5 At least a part of TPV5 is exposed to the outside from the molding layer MD. The molding layer MD may include a polymer layer such as a resin. The molding layer MD may include, for example, EMC (epoxy molding compound).

The fifth semiconductor chip 450 is a memory chip or a logic chip. For example, when the first semiconductor chip 410 to the fourth semiconductor chip 440 are memory chips, the fifth semiconductor chip 450 may include a memory controller that controls the first semiconductor chip 410 to the fourth semiconductor chip 440. The semiconductor package 400 constitutes, for example, a SoC (system on chip) or a SIP (system in package).

The semiconductor package 400 may further include a first insulating layer IL1, a second insulating layer IL2, and an additional layer AD formed between the first insulating layer IL1 and the second insulating layer IL2. In an exemplary embodiment, the additional layer AD includes an element such as a capacitor or an inductor. Alternatively, the additional layer AD may further include additional semiconductor chips by comprising the same or similar configuration as the first layer L1 to the fourth layer L4.

FIG. 24 is a block diagram schematically illustrating an electronic system including a semiconductor package according to an exemplary embodiment of the present invention.
Specifically, the electronic system 1000 includes a control unit 1010, an input unit 1020, an output unit 1030, and a storage unit 1040, and may further include a communication unit 1050 and / or other operation unit 1060.

The control unit 1010 collectively controls the electronic system 1000 and each part. The control unit 1010 is also understood as a central processing unit or a central control unit. The input unit 1020 outputs an electrical instruction signal to the control unit 1010. The input unit 1020 is an image recognition device such as a keyboard, a keypad, a mouse, a touch pad, a scanner, or various input sensors. The output unit 1030 receives an electrical instruction signal from the control unit 1010 and outputs the result processed by the electronic system 1000. The output unit 1030 is a monitor, a printer, a beam irradiator, or various mechanical devices.

The storage unit 1040 is a component for temporarily or permanently storing the electric signal processed by the control unit 1010 or the processed electric signal. The storage unit 1040 is physically and electrically connected or coupled with the control unit 1010. The communication unit 1050 receives an electric command signal from the control unit 1010, and transmits / receives an electric signal to / from another electronic system. The other operation unit 1060 performs a physical or mechanical operation according to the command of the control unit 1010.

In an exemplary embodiment, at least one of the control unit 1010, the input unit 1020, the output unit 1030, the storage unit 1040, the communication unit 1050 and the other operating unit 1060 may include the semiconductor package disclosed by FIGS. 1 to 23. good. Thereby, the volume of the electronic system 1000 is reduced.

The above description of the examples is merely an example with reference to the drawings for a more thorough understanding of the invention and should not be construed as limiting the invention. .. Further, it will be obvious to those skilled in the art to which the present invention belongs that various changes and changes can be made without departing from the basic principles of the present invention.

The semiconductor package and the method for manufacturing the same of the present invention can be effectively applied to, for example, technical fields related to electronic devices.

100, 200, 300, 400 Semiconductor package 110, 210, 310, 410 1st semiconductor chip 111, 311 1st pad 120, 220, 320, 420 2nd semiconductor chip 121, 211, 321 2nd pad 330, 430 3rd Semiconductor chip 331 3rd pad 340, 440 4th semiconductor chip 341 4th pad 450 5th semiconductor chip 451 5th pad 1000 Electronic system 1010 Control unit 1020 Input unit 1030 Output unit 1040 Storage unit 1050 Communication unit 1060 Other operation unit

Claims (20)

A first layer containing one or more first semiconductor chips having a first surface to which one or more first pads are exposed.
A second layer comprising one or more second semiconductor chips arranged vertically above the first layer and having a second surface exposed to one or more second pads.
A first rewiring layer disposed between the first layer and the second layer and electrically connected to the one or more first pads.
The first layer comprises one or more first TPV (throwh panel via) that penetrate the first layer in the vertical direction and are electrically connected to the first rewiring layer .
In the one or more first semiconductor chips and the one or more second semiconductor chips, the first surface and the second surface face each other with the first rewiring layer interposed therebetween. Placed in
The one or more second pads are electrically connected to the first rewiring layer.
A semiconductor package characterized in that the first semiconductor chip and the second semiconductor chip are arranged so as to face each other while forming symmetry with respect to the first rewiring layer and share the first rewiring layer . The first layer includes a first panel comprising one or more first accommodating portions in which the one or more first semiconductor chips are accommodated.
The semiconductor package according to claim 1, wherein the second layer includes a second panel including one or more second accommodating portions in which the one or more second semiconductor chips are accommodated. One or more bumps are arranged between the one or more second pads and the first rewiring layer.
The semiconductor package according to claim 1 , wherein the one or more second pads and the first rewiring layer are electrically connected via the one or more bumps. The one or more second pads include one or more protrusions that project toward the first rewiring layer.
The semiconductor package according to claim 1 , wherein the first rewiring layer includes one or more grooves coupled to the one or more protrusions. The first aspect of the present invention is characterized in that the upper surface of the first rewiring layer electrically connected to the one or more second pads is provided on the same plane as the lower surface of the one or more second pads. The described semiconductor package. The first layer is characterized by containing one or more TSVs (through silicon vias) extending vertically from the one or more first pads and penetrating the one or more first semiconductor chips. The semiconductor package according to claim 1. The semiconductor package according to claim 6 , wherein the height of the one or more first semiconductor chips in the vertical direction is the same as the height of the first layer in the vertical direction. The first aspect of claim 1, wherein the second layer includes one or more second TPVs that penetrate the second layer in the vertical direction and are electrically connected to the first rewiring layer. Semiconductor package. A second rewiring layer laminated in the vertical direction on the second layer is further included.
The semiconductor package according to claim 8 , wherein the one or more second pads and the one or more second TPV are electrically connected to the second rewiring layer. One or more bumps are arranged between the one or more second TPV and the first rewiring layer.
The semiconductor package according to claim 8 , wherein the one or more second TPVs and the first rewiring layer are electrically connected via the one or more bumps. The one or more second TPVs include one or more protrusions that project towards the first rewiring layer.
The semiconductor package according to claim 8 , wherein the first rewiring layer includes one or more grooves coupled to the one or more protrusions. The eighth aspect of the present invention, wherein the upper surface of the first rewiring layer electrically connected to the one or more second TPVs is provided on the same plane as the lower surface of the one or more second TPVs. Semiconductor package. A first semiconductor chip having a first surface to which one or more first pads are exposed, a first panel provided with a first accommodating portion for accommodating the first semiconductor chip, and the first panel vertically penetrating. A first layer containing one or more first TPVs
A first rewiring layer laminated on the first layer in the vertical direction and electrically connected to the one or more first pads and the one or more first TPV.
A second semiconductor chip that is vertically laminated on the first rewiring layer and has a second surface on which one or more second pads are exposed, and a second accommodating portion that accommodates the second semiconductor chip. Includes a second layer, including a provided second panel ,
The first accommodating portion and the second accommodating portion are arranged symmetrically with respect to the first rewiring layer.
The one or more second pads are electrically connected to the first rewiring layer.
A semiconductor package characterized in that the first semiconductor chip and the second semiconductor chip are arranged so as to face each other while forming symmetry with respect to the first rewiring layer and share the first rewiring layer . The first layer and the second layer are one that extends in the vertical direction from the one or more first pads and the second pads, respectively, and penetrates the first semiconductor chip and the second semiconductor chip. The semiconductor package according to claim 13 , wherein each of the two or more TSVs (through silicon vias) is contained. The semiconductor package according to claim 14 , wherein the first accommodating portion has the same height as the first panel in the vertical direction. The second layer comprises one or more second TPVs (throwpanel via) that penetrate the second panel in the vertical direction.
13. The semiconductor package according to claim 13 , further comprising a second rewiring layer that is vertically laminated on the second layer and electrically connected to the one or more second TPVs. On the first panel, one or more first semiconductor chips having a first surface on which one or more first pads are exposed, and one or more first TPV (throwh panel via) penetrating the first panel. By arranging, the stage of forming the first layer and
A stage of forming a second layer by arranging one or more second semiconductor chips having a second surface on which one or more second pads are exposed on the second panel.
A step of forming the one or more first pads on the first layer and a first rewiring layer electrically connected to the first TPV.
A step of forming a first stack structure by vertically laminating the second layer on the first rewiring layer is included.
The stage of forming the first stack structure is
The step including laminating the second layer so that the first surface and the second surface face each other so as to sandwich the first rewiring layer is included.
A semiconductor package characterized in that the first semiconductor chip and the second semiconductor chip are arranged so as to face each other while forming symmetry with respect to the first rewiring layer and share the first rewiring layer . Production method. The stage of forming the second layer is
The method for manufacturing a semiconductor package according to claim 17 , wherein the second panel includes a step of arranging one or more second TPVs penetrating the second panel. By arranging on the third panel one or more third semiconductor chips having a third surface on which one or more third pads are exposed, and one or more third TPVs penetrating the third panel. The stage of forming the third layer and
By arranging on the fourth panel one or more fourth semiconductor chips having a fourth surface on which one or more fourth pads are exposed, and one or more fourth TPVs penetrating the fourth panel. The stage of forming the fourth layer and
A step of forming a second rewiring layer electrically connected to the one or more third pads and the third TPV on the third layer.
A step of forming a second stack structure by laminating the fourth layer on the second rewiring layer in the vertical direction.
The method for manufacturing a semiconductor package according to claim 18 , further comprising a step of laminating the second stack structure on the first stack structure in the vertical direction. A first semiconductor chip having a first surface to which one or more first pads are exposed, a first panel provided with a first accommodating portion for accommodating the first semiconductor chip, and the first panel vertically penetrating. A first layer containing one or more first TPV (throw semiconductor via)
A first rewiring layer arranged vertically on the first layer and electrically connected to the one or more first pads and the one or more first TPV.
A second semiconductor chip having a second surface that is vertically laminated on the first rewiring layer and is exposed to one or more second pads that are electrically connected to the first rewiring layer. A second panel provided with a second accommodating portion for accommodating the second semiconductor chip, and a second layer including a second TPV that vertically penetrates the second panel and is electrically connected to the first rewiring layer. And, including
A semiconductor package characterized in that the first semiconductor chip and the second semiconductor chip are arranged so as to face each other while forming symmetry with respect to the first rewiring layer and share the first rewiring layer .

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