JP6764375B2 - Field effect transistor - Google Patents

Description

The present invention relates to the structure of a field effect transistor that can realize high frequency operation by shortening the gate and suppress the short channel effect associated with electric field concentration.

For terahertz waves, which are in the electromagnetic wave frequency band of 0.3 to 3.0 THz, high-speed wireless communication exceeding several tens of Gb / s, non-destructive internal inspection by three-dimensional imaging, and component analysis using electromagnetic wave absorption have been conducted so far. There is a potential to create new applications.

In order to realize an application using terahertz waves, good high-frequency characteristics are required for the electronic devices that compose the application. Generally, as an electronic device having good high-frequency characteristics, a field-effect transistor made of a compound semiconductor having a particularly high electron mobility in terms of physical properties is used. For the further development of terahertz wave technology in the future, field-effect transistors with better high-frequency characteristics are required.

The field-effect transistor is composed of a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a gate electrode formed on the semiconductor layer, and a source electrode and a drain electrode formed on both sides of the gate electrode. To. In particular, a high electron mobility transistor (HEMT) having excellent frequency characteristics is composed of a buffer layer, a conduction channel layer, a carrier supply layer, a barrier layer, an ohmic cap layer, and the like in the stacking direction with respect to the semiconductor substrate.

In a field-effect transistor, when a potential is applied to the gate electrode, the concentration of two-dimensional electron gas formed by supplying carriers from the carrier supply layer to the conduction channel layer is modulated according to the intensity of the potential, and the source is Electrons move through a conduction channel layer formed between the electrodes and the drain electrode. At this time, the conduction channel layer on which the carrier travels and the electron supply layer are spatially separated to suppress scattering due to impurities, so that the electron mobility can be improved. As a result, the field effect transistor can realize high frequency operation.

In order to realize a field effect transistor having excellent high frequency characteristics, it is necessary to improve the modulation rate in this conduction channel layer. In order to improve this modulation rate, it is necessary to shorten the gate length and shorten the carrier travel time in the conduction channel layer.

However, if the gate length is shortened, the conduction channel length is also shortened at the same time. When a drain voltage is applied in this state, an electric field from the drain electrode acts on the conduction channel layer directly under the gate electrode, causing a bias in the distribution of carriers traveling in the conduction channel layer. This adverse effect is called the short channel effect, and causes a phenomenon called DIBL (Drain induced barrier lowering) or impact ionization. For field-effect transistors, DIBL mainly causes a decrease in threshold voltage, deterioration of pinch-off characteristics, deterioration of subthreshold characteristics, etc., and impact ionization mainly causes deterioration of device reliability and generation of kink. ..

As a result, the effect of characteristic deterioration due to the short channel effect is greater than the effect of shortening the gate length and shortening the carrier travel time, and the high frequency characteristics are significantly deteriorated. Therefore, it is necessary to realize a field effect transistor having improved high frequency characteristics while suppressing the short channel effect due to the electric field concentration generated by shortening the gate.

There is a field plate structure as a typical conventional technique for relaxing the electric field strength between the gate electrode and the drain electrode, including the conduction channel layer near the drain electrode side directly under the gate electrode (see, for example, Patent Documents 1 and 2).

FIG. 1 shows the configuration of the field effect transistor described in Patent Document 1. In FIG. 1, the semiconductor substrate 11, the conduction channel layer 12 formed on the semiconductor substrate 11, the source electrode 13, the drain electrode 14, the gate electrode 15, and the gate electrode 15 are in contact with each other on the channel layer 12. While covering the first dielectric layer 16 formed, the second dielectric layer 17 formed on the conduction channel layer 12 between at least the source electrode 13 and the gate electrode 15, and the gate electrode 15 from above. A field effect type transistor having a field plate structure is described, which comprises a source wall 18 having a tip portion 19 hanging on the upper surface of the first dielectric layer 16. In the field-effect transistor shown in FIG. 1, the first dielectric layer 16 has a higher dielectric constant than the second dielectric layer 17.

According to the configuration described in Patent Document 1 shown in FIG. 1, the electric power line between the drain electrode 14 and the gate electrode 15 has a higher dielectric constant than the second dielectric layer 17, the first dielectric layer 16. Since it is attracted toward the tip 19 of the source wall 18 via the gate electrode 15, the electric field concentration between the drain electrode 14 and the gate electrode 15 is relaxed, including the conduction channel layer 12 near the drain electrode side directly under the gate electrode 15. Can be made to.

FIG. 2 shows the configuration of the field effect transistor described in Patent Document 2. In FIG. 2, between the semiconductor substrate 21, the nitride semiconductor layer 22 formed on the semiconductor substrate 21, the source electrode 23, the drain electrode 24, the gate electrode 25, and the drain electrode 24 and the gate electrode 25. In the region between the drain electrode 24 and the gate electrode 25, the first field plate 26 formed in the region of the above, the second field plate 27 formed above the first field plate 26 and insulated from the first field plate 26. A second insulation provided on the first insulating film 28 in the region between the first insulating film 28 covering the surface of the nitride semiconductor layer 22 and the first field plate 26 and the drain electrode 24. An electric field effect type transistor having a dual field plate structure with a film 29 is shown.

The second field plate 27 includes a shielding portion 30 in the region between the first field plate 26 and the drain electrode 24 that shields the first field plate 26 from the drain electrode 24. The upper end of the shielding portion 30 is located above the upper end of the first field plate 26, and the second field plate 27 is above the structure formed from the gate electrode 25 and the first field plate 26. It overlaps.

According to the field effect transistor shown in FIG. 2, due to the dual field plate structure, the electric field concentration between the drain electrode 24 and the gate electrode 25 including the nitride semiconductor layer 22 near the drain electrode side directly under the gate electrode 25. Can be efficiently relaxed.

Japanese Patent No. 4768996 Japanese Patent No. 4968067

However, all of the above-mentioned conventional techniques are used for improving withstand voltage characteristics in field effect transistors for high output applications. That is, in order to relax the electric field concentration and suppress dielectric breakdown from the lower end of the gate electrode to the entire region of the drain electrode when a voltage of about 10 V to several 100 V or more is applied to the gate electrode and the drain electrode. It is not a structure for improving high frequency characteristics.

When the field plate structure is actually adopted, the parasitic capacitance is effectively increased by the amount that the area of the gate electrode and the source electrode is expanded. Increasing the parasitic capacitance increases the transmission delay of the signal propagating through the field effect transistor and hinders the speedup. This hinders the realization of high-frequency operation of the field-effect transistor.

Summarizing the above, it is a big issue to realize a structure of a field effect transistor that can realize high frequency operation by accurately controlling the short channel effect due to gate shortening and not increasing the parasitic capacitance.

In order to solve the above problems, the electric field effect transistor according to one aspect of the present invention has a buffer layer, a conduction channel layer, a spacer layer, a carrier supply layer, and a barrier layer on the circuit forming surface side of the semiconductor substrate. , And two ohmic cap layers formed on the barrier layer apart from each other, a source electrode and a drain electrode formed on the two ohmic cap layers, respectively, and the above-mentioned on the barrier layer. An electric field effect transistor including a gate electrode formed between a source electrode and a drain electrode, which is a back surface side of the semiconductor substrate opposite to the circuit forming surface side and is a gate electrode. An electric field relaxation electrode formed by being embedded in the semiconductor substrate so as not to come into contact with the conduction channel layer is further provided at a position between the drain electrode and the electric field relaxation electrode so that a potential can be applied. It is characterized by being done.

According to the field effect transistor according to the present invention, since the structure is such that the electric field concentration of the conduction channel layer near the drain electrode side directly under the gate electrode is relaxed without forming the field plate structure, the parasitic capacitance is reduced and the high frequency is generated. It is possible to suppress the short-channel effect while trying to improve the quality.

It is a figure which shows the structure of the field effect transistor described in Patent Document 1. It is a figure which shows the structure of the field effect transistor described in Patent Document 2. It is a schematic cross-sectional enlarged view which shows the structure of the field effect transistor which concerns on Example 1 of this invention. It is a top view which shows the structure of the field effect transistor which concerns on Example 1 of this invention. It is a figure which shows the state which the source electrode was grounded and the positive bias potential was applied to the drain electrode 109 before the formation of the electric field relaxation electrode. It is a figure which shows the state which the source electrode was grounded, and the positive bias potential was applied to the drain electrode 109 after the formation of the electric field relaxation electrode. It is a schematic cross-sectional enlarged view which shows the structure of the field effect transistor which concerns on Example 2 of this invention. It is a top view which shows the structure of the field effect transistor which concerns on Example 3 of this invention. FIG. 8 is an enlarged cross-sectional view of IX-IX'in FIG. It is a schematic cross-sectional enlarged view which shows the structure of the field effect transistor which concerns on Example 4 of this invention. It is a schematic cross-sectional enlarged view which shows the structure of the field effect transistor which concerns on Example 5 of this invention.

The present invention is premised on maintaining high frequency performance. For example, in the case of a field-effect transistor that can be expected to operate in the terahertz band with an InP gate length of 100 nm or less, it is assumed that a voltage of about several V at the maximum is applied to the gate electrode and drain electrode for operation. There is. In this case, the electric field concentration from the drain electrode at the lower end of the gate electrode is weaker than the case where the field plate structure as described in Patent Documents 1 and 2 is applied with high output to the extent that it affects the conduction carrier such as electrons. is there. That is, in order to suppress the short-channel effect of the field-effect transistor operating at high speed, it is sufficient to alleviate this slight electric field concentration.

The present invention accurately alleviates the electric field concentration in the conduction channel layer near the drain electrode side directly under the gate electrode and suppresses the increase in parasitic capacitance in the field effect transistor in which the gate length is shortened to realize high frequency operation. By doing so, high frequency operation is realized.

(Example 1)
FIG. 3 is a schematic cross-sectional enlarged view (III-III'cross-sectional view of FIG. 4 described later) showing the configuration of the field-effect transistor according to the first embodiment of the present invention. In FIG. 3, the semiconductor substrate 101, the buffer layer 102 formed on the semiconductor substrate 101, the conduction channel layer 103 formed on the buffer layer 102, and the spacer layer 104 formed on the conduction channel layer 103 are shown. , The carrier supply layer 105 formed on the spacer layer 104, the barrier layer 106 formed on the carrier supply layer 105, and the two ohmic cap layers 107 formed apart from each other on the barrier layer 106. A source electrode 108 and a drain electrode 109 formed on the ohmic cap layer 107, a gate electrode 110 formed between the source electrode 108 and the drain electrode 109 on the barrier layer 106, and a gate of the source electrode 108 and the drain electrode 109. A field effect transistor including a gate mask insulating film 111 formed on each side of the electrode 110 side and an electric field relaxation electrode 112 formed on the back surface side of the semiconductor substrate 101 is shown. Here, in FIG. 1, the surface on which the buffer layer 102 or the like is formed on the semiconductor substrate 101 is used as the circuit forming surface, and the surface on the opposite side thereof is used as the back surface.

As shown in FIG. 3, recess regions 113 are present on both sides of the gate electrode 110 in the direction toward the source electrode 108 and the drain electrode 109. Further, the ohmic region 114 is formed by the spacer layer 104, the carrier supply layer 105, the barrier layer 106, and the ohmic cap layer 107 formed directly under each of the source electrode 108 and the drain electrode 109.

The electric field relaxation electrode 112 is formed by being embedded in the semiconductor substrate 101 at a position on the back surface of the semiconductor substrate 101 between the drain electrode 109 and the gate electrode 110 so as not to be in contact with the conduction channel layer 103. The electric field relaxation electrode 112 is configured to apply a compensation potential so as to alleviate the electric field concentration in the conduction channel layer 103 near the drain electrode 109 side immediately below the gate electrode 110.

FIG. 4 is a top view of the field effect transistor according to the first embodiment of the present invention. As shown in FIG. 4, the electric field relaxation electrode 112 is formed in parallel with the source electrode 108, the drain electrode 109, and the gate electrode 110, and penetrates between the back surface of the semiconductor substrate 101 and the circuit forming surface. It is connected to the penetrating via 115. Further, on the circuit forming surface of the semiconductor substrate 101, an electric field relaxation electrode pad 116 is formed at an end portion, and a gate electrode pad 117 is formed at an opposite end portion. The electric field relaxation electrode 112 is connected to the electric field relaxation electrode pad 116 via the substrate penetration via 115, and the gate electrode 110 is connected to the gate electrode pad 117.

In the following examples, InP-HEMT using InP will be described as an example. The conduction channel has a large number of electrons as carriers. However, the present invention is not limited to InP-based materials, and can be applied to field-effect transistors using other semiconductor materials as long as the principle of the present invention is not deviated.

First, on the semiconductor substrate 101 made of InP, a buffer layer 102 having a thickness of 100 to 300 nm made of InAlAs, a conduction channel layer 103 having a thickness of 5 to 20 nm made of InGaAs, and a spacer layer 104 having a thickness of 2 to 5 nm made of InAlAs. Carrier supply layer 105 made of InAlAs doped with Si as impurities 1 × 10 ¹⁹ to 2 × 10 ¹⁹ cm ^-3 , barrier layer 106 made of InAlAs with a thickness of 5 to 20 nm, and Si 1 × 10 ¹⁹ to 2 × 10 ¹⁹ cm ^{-3 The} ohmic cap layer 107 made of doped InGaAs is sequentially laminated by crystal-growing by an organic metal vapor phase growth method, a molecular beam epitaxy method, or the like.

A source electrode 108 and a drain electrode 109 made of, for example, Ti / Pt / Ni or a combination of a plurality of kinds of metals containing at least these metals are formed in the portion of the ohmic region 114 of the ohmic cap layer 107. The source electrode 108 and the drain electrode 109 are ohmic-bonded to the semiconductor substrate 101 by the presence of the ohmic cap layer 107 in the ohmic region 114 directly below the source electrode 108 and the drain electrode 109.

An insulating film 111 for a gate mask is formed on the ohmic cap layer 107, the source electrode 108, and the drain electrode 109. The insulating film 111 for a gate mask can be made of, for example, silicon oxide or silicon nitride, and has a typical thickness of, for example, 20 to 200 nm. By forming the gate mask insulating film 111 with this thickness, it is possible to realize a field effect transistor having a short gate length and a high yield.

Next, the barrier layer 106 is formed in the opening so as to be partially exposed by partially removing the gate mask insulating film 111 and the ohmic cap layer 107 between the source electrode 108 and the drain electrode 109. Then, by selectively removing the ohmic cap layer 107 on the side wall portion of the opening, the recess region 113 in which the ohmic cap layer 107 is removed in the lateral direction from the opening is formed.

Next, a gate electrode 110 whose lower end reaches the barrier layer 106 is formed in the opening. A low resistance metal such as Au, Ag, or Cu is used as the main material of the gate electrode 110, and for example, an electric field plating, an electroless plating method, a sputtering method, and a vacuum vapor deposition method are used as the forming method.

The size and shape of the gate electrode 110 are designed so that parasitic capacitance does not occur with respect to the source electrode 108 and the drain electrode 109, respectively, and the resistance of the entire gate electrode 110 is sufficiently low. The length of the gate electrode 110 in a direction parallel to the gate length (channel) (hereinafter, this direction is referred to as a gate length direction) is typically designed to be, for example, 0.01 to 5 μm. Further, the length of the gate electrode 110 in the gate length direction is, for example, T-shaped, and the length of the end of the gate electrode 110 on the circuit forming surface side is the length of the end of the gate electrode 110 on the back surface side. It may be designed to be larger than the length of the portion in the gate length direction.

The distance between the gate electrode 110 and the source electrode 108 and the distance between the gate electrode 110 and the drain electrode 109 can be, for example, approximately 200 to 3000 nm. In particular, in order to improve the output characteristics of the transistor, the distance between the gate electrode 110 and the drain electrode 109 is set to be larger than the distance between the gate electrode 110 and the source electrode 108. You may.

By forming the gate electrode 110 using the above method, it is possible to sufficiently reduce the resistance of the gate electrode 110 and realize a field effect transistor having good high frequency characteristics.

Further, recess regions 113 are present on both sides of the gate electrode 110. The size of the recess region 113 is designed based on the balance between the effect of increasing parasitic resistance and the effect of reducing parasitic capacitance and drain conductance. For example, typically, the length of the recess region 113 on the source electrode 108 side in the gate length direction can be 20 to 200 nm, and the length of the recess region 113 on the drain electrode 109 side in the gate length direction can be 50 to 300 nm. ..

The electric field relaxation electrode 112 is embedded in the semiconductor substrate 101 at a position between the drain electrode 109 and the gate electrode 110 on the back surface of the semiconductor substrate 101 so as not to be in contact with the conduction channel layer 103. The electric field relaxation electrode 112 forms a deep-drilled structure by supporting the circuit forming surface side of the semiconductor substrate 101 with another supporting substrate or the like and performing various etchings, and then fills a conductive material or forms a side wall of the deep-drilled structure. It is formed by coating. For the etching, a wet etching method using citric acid, hydrochloric acid, or phosphoric acid-based etchant, a dry etching method using gas plasma such as HI, HBr, or Cl ₂ , or a combination thereof is used.

The deep moat structure has a distance of 0.01 to 1 μm from the end of the electric field relaxation electrode 112 on the circuit formation surface side to the bottom surface of the conduction channel layer 103 so as not to penetrate to the circuit formation surface of the semiconductor substrate 101. It can be formed to a degree. Thereby, the electric field concentration can be efficiently relaxed and the effect of suppressing the short channel effect can be maximized. However, the electric field relaxation electrode 112 may be formed at a position other than the above in consideration of the degree of the effect of relaxation of the electric field concentration.

An etching stop layer may be formed on the semiconductor substrate 101 in order to realize a deep-drilled structure of the electric field relaxation electrode 112 with high accuracy without penetrating to the circuit forming surface of the semiconductor substrate 101. This etching stop layer is formed on the back surface side of the buffer layer 102, and has a property that the speed of dry etching or wet etching is selectively slow. Due to this property, the accuracy of the deep digging structure can be improved.

At this time, the semiconductor substrate 101 may be thinly processed to a desired thickness. By thinning the semiconductor substrate 101 to a desired thickness, the machining accuracy of the electric field relaxation electrode 112 in the depth direction is sufficiently improved, and the conduction channel layer 103 near the drain electrode side directly below the gate electrode 110 by the electric field relaxation electrode 112. The electric field controllability in the above can be improved. The thickness of the semiconductor substrate 101 after typical processing is 20 to 300 μm, but it may be thinner than this depending on the formation size of the electric field relaxation electrode 112.

The electric field relaxation electrode 112 may be formed at a position that internally divides the distance between the gate electrode 110 and the drain electrode 109 from the gate electrode 110 to 0 to 30% with respect to the distance between the gate electrode 110 and the drain electrode 109. In order to suppress the short channel effect, the conduction channel layer 103 can be controlled most effectively. However, the electric field relaxation electrode 112 may be formed at a position other than the above in consideration of the degree of the effect of relaxation of the electric field concentration.

The length of the electric field relaxation electrode 112 in the gate length direction is formed on a scale equal to or less than the length of the gate electrode 110 in the gate length direction. By setting such a length, the electric field relaxation effect can be maximized while maintaining the performance. However, in consideration of the effect of relaxing the electric field concentration, the length of the electric field relaxing electrode 112 in the gate length direction may be set to the above or less. Further, although the lower limit of the length of the electric field relaxation electrode 112 in the gate length direction is limited by the manufacturing technique for forming the electrode 112, it is a design matter in consideration of the desired degree of the effect of the present invention. It is determined.

The electric field relaxation electrode 112 may be configured such that a metal material is filled therein. Similar to the gate electrode 110, a low resistance metal such as Au, Ag, or Cu can be used as the main material of the metal material, and the forming method thereof includes, for example, electric field plating, electroless plating, sputtering, vacuum deposition, etc. Is used.

Further, the electric field relaxation electrode 112 may have a structure in which a metal film is formed only on the side wall thereof, and the inside of the metal film may be filled with an appropriate filling material in order to secure the strength. Examples of the filling material include organic resins such as benzocyclobutene, polyimide resins, and epoxy resins UV, and metals such as Au, Ag, and Cu. The filling method may be an electric field plating method or an electroless plating method, or a material having an appropriate viscosity may be filled by a dispensing method, a squeegee method, or an inkjet method. However, if sufficient strength can be obtained without filling the electric field relaxation electrode 112, it is not always necessary to fill with the filling material.

The structure according to the present invention adopts a structure similar to the field plate structure as described above, but its action and effect are different from that. The field plate structure is an electrode installed so that the gate electric field formed in the channel portion by the gate applied voltage becomes a sufficiently strong electric field for the purpose of modulating the potential of the entire channel by, for example, controlling the threshold value. It is a structure that adjusts the position and size of. In the case of the field plate structure, high-speed operation cannot be expected because the capacitance between the gate and the channel is effectively increased significantly.

On the other hand, in the present invention, since the electric field relaxation electrode 112 formed on the back surface of the semiconductor substrate 101 has a small physical size, a remarkable increase in capacitance does not occur. Further, the position and size of the electric field relaxation electrode 112 are set for the purpose of relaxing the electric field in the conduction channel layer 103 near the drain electrode side directly below the gate electrode 110, not aiming at the potential modulation of the entire channel in the first place. It has been adjusted and installed. Therefore, it is clear that the structure according to the present invention is completely different from the so-called electric field relaxation structure in terms of physical structure, purpose of installation, and action and effect.

The effect of suppressing the short-channel effect of the field-effect transistor according to the first embodiment of the present invention will be described with reference to FIGS. 5 and 6. 5 and 6, respectively, show that the source electrode 108 is grounded and positive with respect to the drain electrode 109 in order to allow electrons to drift from the source electrode 108 to the drain electrode 109 before and after the formation of the electric field relaxation electrode 112. The state in which the bias potential of is applied is shown. In FIGS. 5 and 6, it is assumed that a positive bias potential is input to the gate electrode 110 in order to supply electrons to the conduction channel layer 103. In reality, a high frequency signal is applied to the gate electrode 110.

First, a state in which the electric field relaxation electrode 112 shown in FIG. 5 is not formed will be described. In the field-effect transistor with a shortened gate length, the positive bias potential applied to the drain electrode 109 concentrates the electric field in the conduction channel layer 103 near the drain electrode side directly below the gate electrode 110. As a result, the electrons in the conduction channel layer 103 are attracted to the drain electrode 109 side, and the electron distribution in the conduction channel layer 103 is biased toward the drain electrode 109 side.

Ideally, the electric field strength in the conduction channel layer 103 near the drain electrode side directly under the gate electrode 110 is affected only by the gate potential, and a potential gradient is generated parallel to the traveling direction of the electrons. When the length or the channel length is shortened, the influence of the voltage applied to the drain electrode 109 extends to the extent that it cannot be ignored in the conduction channel layer 103 near the drain electrode side immediately below the gate electrode 110 and its surroundings. As a result, the threshold voltage is lowered, the pinch-off characteristic is deteriorated, and the subthreshold characteristic is significantly deteriorated.

Next, as shown in FIG. 6, a state in which the electric field relaxation electrode 112 is formed and a negative bias potential is applied to the electric field relaxation electrode 112 will be described. In this case, the electric field concentration due to the positive bias applied to the drain electrode 109 can be caused to act on the conduction channel layer 103 so that the negative potential from the electric field relaxation electrode 112 is relaxed. As a result, it is possible to suppress a decrease in the threshold voltage and deterioration of the subthreshold characteristic due to DIBL.

The amount of negative bias applied to the electric field relaxation electrode 112 required to control the electrons in the conduction channel layer 103 is estimated using the following equation as a guide, considering the structure according to the present invention as a parallel plate structure. be able to.

Here, V _b is the amount of the required bias applied from the electric field relaxation electrode 112, and D _{ch and back} are the distances between the bottom surface of the conduction channel layer 103 and the end of the electric field relaxation electrode 112 on the circuit forming surface side. , D _ch is the thickness of the conduction channel layer 103, and V _g is the maximum potential of the high frequency signal applied to the gate electrode 110. For example, in the case of D _{ch, back} = 0.1 μm, D _ch = 0.2 μm, and V _g = 0.5 V, V _b may be about −0.25 V as a guide.

In this embodiment, it is assumed that a negative bias is applied to the electric field relaxation electrode 112 mainly in order to suppress DIBL. On the other hand, if it is desired to suppress impact ionization due to channel shortening, a positive bias may be applied to the electric field relaxation electrode 112. By applying a positive bias to the electric field relaxation electrode 112, hot carriers generated by impact ionization in the drain electrode 109 can be neutralized, and reliability deterioration and kink can be suppressed. Of course, in consideration of the above-mentioned DIBL suppression, a bias that efficiently reduces both may be applied to the electric field relaxation electrode 112, and the bias applied to the electric field relaxation electrode 112 is positive or negative and its application amount. It may be adjusted appropriately according to the purpose including.

As described above, according to the present invention, by forming the electric field relaxation electrode 112 as described above, the compensation potential can be effectively suppressed with respect to the conduction channel layer 103 without increasing the parasitic capacitance. Can be applied.

(Example 2)
FIG. 7 is a schematic enlarged cross-sectional view showing the configuration of the field effect transistor according to the second embodiment of the present invention. The field effect transistor according to the second embodiment is provided with an electric field relaxation electrode 212 having a tapered shape so that the length in the gate length direction gradually decreases from the end on the back surface side to the end on the circuit forming surface side. This is different from the field effect transistor according to the first embodiment.

Since the electric field relaxation electrode 212 has the tapered shape, the electric field can be concentrated on the circuit forming surface. Therefore, by applying a smaller potential to the electric field relaxation electrode 212, the conduction channel layer 103 It is possible to control the potential bias of the short channel effect.

Examples of the method for forming the electric field relaxation electrode 112 include the following two methods. As the first method, there is a method of forming the electric field relaxation electrode 212 from the back surface side by using the wet etching method and utilizing the etching anisotropy in which the etching rate differs with respect to the crystal orientation. As the second method, there is a method of forming a reverse taper shape by using a dry etching method and utilizing the small amount of side etching from the back surface to the stacking direction. Of course, the electric field relaxation electrode 212 having a reverse taper shape may be formed by combining these two methods.

In the second embodiment, the length of the electric field relaxation electrode 212 in the gate length direction may be set so that, for example, when the end on the back surface side is 5 μm, the end on the circuit forming surface side is about 1 μm. preferable.

(Example 3)
FIG. 8 is a top view showing the configuration of the field effect transistor according to the third embodiment of the present invention, and FIG. 9 is an enlarged cross-sectional view of IX-IX'of FIG. As shown in FIGS. 8 and 9, in the third embodiment, a plurality of electric field relaxation electrodes 312 are formed in a linear shape parallel to the formation direction of the gate electrode 110 and in a circular or rectangular shape at regular intervals. There is. These plurality of electric field relaxation electrodes 312 are electrically connected by back surface wiring 301 formed on the back surface of the semiconductor substrate 101.

In the above-mentioned Examples 1 and 2, since the electric field relaxation electrode 112 is formed by etching the semiconductor substrate 101 linearly in parallel with the forming direction of the gate electrode 110, the mechanical strength is significantly deteriorated. I was afraid. On the other hand, in the structure according to the third embodiment, a plurality of electric field relaxation electrodes 312 are formed by etching in a linear shape at regular intervals in a circular or rectangular shape parallel to the formation direction of the gate electrode 110. There is. As a result, the field-effect transistor according to the third embodiment can maintain high mechanical strength.

The back surface wiring 301 may be formed in the same manner as the material and forming method of the electric field relaxation electrode 312, and may be formed at the same time as the electric field relaxation electrode 312.

The electric field relaxation electrode 312 is formed so that the distance from the end of the electric field relaxation electrode 312 on the circuit forming surface side to the bottom surface of the conduction channel layer 103 is about 0.01 to 1 μm, as in the first embodiment. be able to. Further, the length of the electric field relaxation electrode 312 in the gate length direction is the same as that of the first embodiment.

The length of the back surface wiring 301 in the gate length direction is formed to be about the same as or slightly wider than the electric field relaxation electrode 312. As a result, even if a plurality of electric field relaxation electrodes 312 are formed in a circular or rectangular shape at regular intervals as in the third embodiment, the potential from the electric field relaxation electrodes 312 is uniformly applied to the conduction channel layer 103. It can act and suppress the short channel effect.

(Example 4)
FIG. 10 is a schematic cross-sectional enlarged view showing the configuration of the field effect transistor according to the fourth embodiment of the present invention. As shown in FIG. 10, in the fourth embodiment, the surface of the electric field relaxation electrode 112 on the semiconductor substrate 101 side is coated with a non-conductive and low dielectric constant dielectric 401.

As the dielectric 401, a material having a relative permittivity lower than that of the semiconductor substrate 101, ideally, a material having a relative permittivity of 4 or less can be used. Similar to the first embodiment, the electric field relaxation electrode 112 is formed so that the distance from the end of the electric field relaxation electrode 112 on the circuit forming surface side to the bottom surface of the conduction channel layer 103 is about 0.01 to 1 μm. be able to. Further, the length of the electric field relaxation electrode 112 in the gate length direction is the same as that of the first embodiment.

By coating the electric field relaxation electrode 112 with a non-conductive, low dielectric constant dielectric 401, the electric field from the electric field relaxation electrode 112 is applied to the conduction channel layer 103 more efficiently and selectively, and the gate is formed. It is possible to more effectively relax the electric field concentration from the drain electrode 109 when the length is shortened.

(Example 5)
FIG. 11 is a schematic cross-sectional enlarged view showing the configuration of the field effect transistor according to the fifth embodiment of the present invention. As shown in FIG. 11, in the fifth embodiment, the control circuit 501 capable of controlling the potential applied to the electric field relaxation electrode 112, which is optimal for suppressing the short channel effect, is integrated on the circuit forming surface of the semiconductor substrate 101. are doing.

The control circuit 501 includes a mechanism for monitoring at least the drain voltage value among the drain voltage value and the drain current value, and the application of the optimum electric field relaxation electrode 112 for compensating for the short channel effect based on the monitor value. It has a function to calculate the potential. For example, when assuming a high-frequency amplifier, the control circuit 501 can calculate and control the applied potential of the electric field relaxation electrode 112 so as to maximize the output gain.

According to the fifth embodiment, even in the case where various sizes of field effect transistors are mixed or in the case of a circuit to which various drain voltages are applied, the optimum value to be applied to the electric field relaxation electrode 112 in each case is obtained. The potential can be set.

Claims (6)

A buffer layer, a conduction channel layer, a spacer layer, a carrier supply layer, and a barrier layer are sequentially laminated on the circuit forming surface side of the semiconductor substrate, and two ohmics formed separately on the barrier layer. A field effect type including a cap layer, a source electrode and a drain electrode formed on the two ohmic cap layers, respectively, and a gate electrode formed between the source electrode and the drain electrode on the barrier layer. It ’s a transistor,
It is embedded in the semiconductor substrate at a position between the gate electrode and the drain electrode on the back surface side of the semiconductor substrate opposite to the circuit forming surface side so as not to contact the conduction channel layer. Further equipped with a formed electrode for electric field relaxation,
The field effect relaxation electrode is a field effect transistor characterized in that it is configured to be able to apply an electric potential. A substrate-penetrating via that penetrates the semiconductor substrate and
An electric field relaxation electrode pad formed on the circuit forming surface side of the semiconductor substrate is further provided.
The field effect transistor according to claim 1, wherein the electric field relaxation electrode is connected to the electric field relaxation electrode pad via the substrate penetrating via. Claim 1 or 2 is characterized in that the electric field relaxation electrode has a tapered shape such that the length in the gate length direction gradually decreases from the end portion on the back surface side to the end portion on the circuit forming surface side. The electric field effect transistor described in. The field-effect transistor according to any one of claims 1 to 3, wherein the field-mitigating electrode is formed in a linear shape at regular intervals in a circular or rectangular shape. The field effect transistor according to any one of claims 1 to 4, further comprising a non-conductive dielectric material that covers the electric field relaxation electrode. A control circuit for controlling the potential applied to the electric field relaxation electrode is further provided.
The control circuit includes a mechanism for monitoring at least the drain voltage value among the drain voltage value and the drain current value, and controls the potential applied to the field relaxation electrode based on the monitor value. The field effect transistor according to any one of claims 1 to 5.

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