JP6662015B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

  2. Description of the Related Art A semiconductor device in which two semiconductor substrates are stacked is known (see Patent Document 1). In a stacked semiconductor device, there is a known problem that an electrical connection between circuits on two semiconductor substrates becomes long.

JP 2010-245506 A

The semiconductor device includes a first semiconductor substrate having a first wiring, a second semiconductor substrate laminated with the first semiconductor substrate, provided with a second wiring and a third wiring, and the second semiconductor substrate. A third semiconductor substrate stacked with the substrate and provided with a fourth wiring and a fifth wiring, and a sixth wiring and a seventh wiring provided on the opposite surface of the stacked structure; the second semiconductor substrate and the third semiconductor; A first connection provided in a hole penetrating through the substrate, penetrating the second wiring and the fourth wiring, and connecting the first wiring, the second wiring, the fourth wiring, and the sixth wiring; And a hole penetrating the third semiconductor substrate and having a depth different from a hole provided with the first connection portion , penetrating the fifth wiring, and forming the third wiring, the fifth wiring, and And a second connection portion for connecting to the seventh wiring.
The method of manufacturing a semiconductor device includes a first semiconductor substrate having a first wiring, a second semiconductor substrate having a second wiring and a third wiring, and a third semiconductor having a fourth wiring and a fifth wiring. And laminating the first and second semiconductor substrates, the second semiconductor substrate, and the third semiconductor substrate, and penetrating the second wiring and the fourth wiring, and Forming a first connection portion for connecting one wiring, the second wiring and the fourth wiring, and a second connection for penetrating the fifth wiring and connecting the third wiring and the fifth wiring; Forming a portion, a sixth wiring connected to the first connection portion on a surface of the first semiconductor substrate opposite to a surface laminated with the second semiconductor substrate, and the second connection portion. have a, a step of forming a seventh wiring connected to, the step of forming the second connecting portion, the third Providing a hole from the semiconductor substrate side through the fifth wiring to the third wiring of the second semiconductor substrate, providing a conductor in the hole and connecting the third wiring and the fifth wiring; Including .

FIG. 2 is a diagram illustrating a schematic configuration of a semiconductor device. FIG. 2A is a diagram illustrating a first semiconductor wafer before bonding. FIG. 2B is a diagram illustrating a second semiconductor wafer before bonding. Hereinafter, since the present invention is characterized by the wiring method, the present invention is mainly shown in a cross-sectional view in which only the wiring portion of the chip is enlarged. It is an expanded sectional view of a chip when the surface of the 2nd semiconductor wafer is stuck on the surface of the 1st semiconductor wafer. FIG. 4 (a) is a diagram illustrating thinning of the second semiconductor wafer. FIG. 4B is a diagram illustrating a third semiconductor wafer before bonding. FIG. 5A is a diagram in which the front surface of the third semiconductor wafer is bonded to the back surface of the second semiconductor wafer. FIG. 5B is a diagram illustrating a thinned third semiconductor wafer. FIG. 6A is a view for explaining the first to third semiconductor wafers whose total thickness has been adjusted. FIG. 6B is a diagram illustrating a step of forming a photoresist pattern. FIG. 7A is a diagram illustrating the formation of a through hole. FIG. 7B is a diagram illustrating the formation of a through-silicon via (TSV). FIG. 3 is a diagram illustrating a completed semiconductor device. 6 is a flowchart illustrating a procedure for manufacturing a semiconductor device.

FIG. 1 is a diagram illustrating a schematic configuration of a semiconductor device according to the present embodiment. In FIG. 1, a semiconductor device 1 is configured by laminating a first semiconductor wafer (semiconductor substrate) 10, a second semiconductor wafer (semiconductor substrate) 20, and a third semiconductor wafer (semiconductor substrate) 30. You.
In the present embodiment, a three-layer stack is exemplified. However, the present invention is not limited to a three-layer structure. For example, two or four layers or more layers may be used.

  The semiconductor device 1 is used for electrically connecting these three semiconductor wafers 10 to 30 after laminating the first semiconductor wafer 10, the second semiconductor wafer 20, and the third semiconductor wafer 30. This is completed by providing the TSV.

  Each of the first semiconductor wafer 10, the second semiconductor wafer 20, and the third semiconductor wafer 30 is a semiconductor substrate manufactured by a known manufacturing technique. On each semiconductor substrate, for example, devices such as an optical sensor, a memory, a transistor, and an LSI, and wires for connecting these devices are formed as necessary.

<First semiconductor wafer>
On the first semiconductor wafer 10, for example, a sensor region 11 in which photoelectric conversion elements are two-dimensionally arranged and a control circuit 12 for the sensor region 11 are formed, and constitute a semi-finished image sensor. . The sensor region 11 includes, for example, a photodiode (PD) forming a pixel and a pixel transistor arranged for each photodiode.

  The control circuit 12 includes, for example, a metal oxide silicon (MOS) transistor. The wiring in the first semiconductor wafer 10 is made of, for example, copper, aluminum, titanium, or a compound thereof.

<Second semiconductor wafer>
On the second semiconductor wafer 20, for example, a memory area 21 in which memory elements are two-dimensionally arranged and a control circuit 22 for the memory area 21 are formed, and constitute a semi-finished product memory circuit. The memory region 21 has, for example, a drain electrode formed on a silicon substrate, a source electrode, and a floating gate sandwiched between tunnel oxide insulating films. The control circuit 22 is configured by, for example, a MOS transistor or the like. The wiring in the second semiconductor wafer 20 is made of, for example, copper, aluminum, titanium, or a compound thereof.

<Third semiconductor wafer>
On the third semiconductor wafer 30, for example, a signal processing circuit 31 in a semi-finished product state is formed. The signal processing circuit 31 is configured by, for example, a CMOS transistor or the like. The wiring in the third semiconductor wafer 30 is made of, for example, copper, aluminum, titanium, or a compound thereof.

  Hereinafter, a manufacturing process for laminating the first semiconductor wafer 10, the second semiconductor wafer 20, and the third semiconductor wafer 30 and electrically connecting the three semiconductor wafers 10 to 30 will be described with reference to the drawings. .

<Lamination>
FIG. 2A is a diagram illustrating the first semiconductor wafer 10a before bonding. FIG. 2A illustrates only the metal wiring 15 among the above-described sensor region 11, control circuit 12, wiring, and the like. The wiring 15 is a wiring that functions as an etching stopper layer later, and is made of, for example, a metal with a low etching rate such as titanium or a metal whose surface is covered with a barrier metal with a low etching rate. The wiring 15 is provided at a position where the TSV is to be provided.
The wiring other than the wiring connected by the TSV is made of a metal such as aluminum having a high etching rate or a nonmetal such as polysilicon.

  FIG. 2B illustrates the second semiconductor wafer 20a before bonding. FIG. 2B shows only the metal wirings 25 and 26 among the memory area 21, the control circuit 22, and the wirings described above. The wiring 25 is a wiring that functions as an etching stopper layer later, as in the case of the wiring 15, and is made of, for example, titanium. The wiring 25 is provided at a position where the TSV is to be provided.

  The wiring 26 provided at the expected position of the TSV and penetrated by etching is made of a metal such as aluminum having a high etching rate or a nonmetal such as polysilicon. In addition, wirings other than the wirings connected by the TSV are also made of a metal such as aluminum or a nonmetal such as polysilicon.

  The surface 10f of the first semiconductor wafer 10a and the surface 20f of the second semiconductor wafer 20a are bonded by plasma bonding or adhesive bonding.

  FIG. 3 is a diagram in which the surface 10f of the first semiconductor wafer 10a and the surface 20f of the second semiconductor wafer 20a are bonded.

  Next, the back surface 20b of the second semiconductor wafer 20a is ground and polished, and is thinned to, for example, a thickness of about 10 μm or less. FIG. 4A is a diagram illustrating a state where the second semiconductor wafer 20 is thinned. Here, the thickness of the first semiconductor wafer 10a and the thickness of the second semiconductor wafer 20a before thinning are both usually 775 μm for a 12-inch wafer.

  FIG. 4B is a diagram illustrating the third semiconductor wafer 30a before bonding. FIG. 4B shows only the metal wirings 35 and 36 among the signal processing circuit 31 and the wirings and the like described above. The wiring 35 and the wiring 36 are provided at the expected positions of the TSV, respectively.

  Since the wiring 35 and the wiring 36 are wirings penetrated by etching, the wiring 35 and the wiring 36 are formed of a metal such as aluminum having a high etching rate or a nonmetal such as polysilicon. The wiring other than the wiring connected by the TSV is made of a metal wiring of an arbitrary material.

  The front surface 30f of the third semiconductor wafer 30a in FIG. 4B is bonded to the back surface 20b of the second semiconductor wafer 20 by plasma bonding or adhesive bonding.

  FIG. 5A is a diagram illustrating a state where the front surface 30f of the third semiconductor wafer 30a is bonded to the back surface 20b of the second semiconductor wafer 20.

  Next, the back surface 30b of the third semiconductor wafer 30a is ground and polished, and is thinned, for example, to a thickness of about 10 μm or less. FIG. 5B is a diagram illustrating a state where the third semiconductor wafer 30 is thinned. Here, the thickness of the third semiconductor wafer 30a before flattening and thinning is usually 775 μm for a 12-inch wafer.

  Next, the back surface 10b of the first semiconductor wafer 10a is polished so that, for example, the total thickness is 700 μm. FIG. 6A is a diagram illustrating a state in which the first semiconductor wafer 10 to the third semiconductor wafer 30 have been bonded after the total thickness has been adjusted.

<TSV formation>
FIG. 6B is a diagram illustrating a step of forming a pattern using the photoresist 40. Specifically, a positive photoresist 40 is applied to the entire back surface 30b of the third semiconductor wafer 30 in FIG. Next, only the position corresponding to the TSV scheduled position is exposed, and then developed to remove the photoresist 40 at the TSV scheduled position. Thus, a pattern using the photoresist 40 is formed. Note that, instead of the positive photoresist 40, a negative photoresist may be used. When a negative photoresist is used, a position other than the position corresponding to the expected TSV position is exposed.

  FIG. 7A is a diagram illustrating the formation of the through holes 51 and 52 at the expected TSV position. After forming a pattern by the photoresist 40, the through holes 51 and 52 are formed by performing anisotropic etching. As described above, the wiring 15 on the first semiconductor wafer 10 and the wiring 25 on the second semiconductor wafer 20 are both formed of a metal having a low etching rate (for example, a metal covered with a titanium barrier metal). ing. Therefore, these wirings both function as an etching stopper layer.

  By providing the wirings 15 and 25 functioning as etching stopper layers, through holes 51 and 52 having different depths can be obtained in a single etching step. Specifically, the etching time is determined based on the depth of the through hole 51. That is, the time required for the hole formed by the etching to penetrate the wiring 36 of the third semiconductor wafer 30 and the wiring 26 of the second semiconductor wafer 20 and reach the wiring 15 of the first semiconductor wafer 10. Is the etching time.

  Since the through-hole 52 is shallower than the through-hole 51, the time required for the hole eroded by etching to reach the wiring 25 of the second semiconductor wafer 20 depends on the amount of the eroded hole on the side of the through-hole 51. It is shorter than the time required to reach the ten wirings 15. However, since the wiring 25 of the second semiconductor wafer 20 is formed of a metal having a low etching rate, the etching rate of the wiring 25 is low. Therefore, the through hole 51 reaches the wiring 15 before the wiring 25 penetrates. In other words, the through holes 51 and 52 having different depths can be obtained with the same etching time.

  FIG. 7B is a diagram illustrating the formation of a TSV. After removing the photoresist 40 remaining after the etching shown in FIG. 7A, a titanium film is formed on the inner wall surfaces 51a and 52a of the through holes 51 and 52, respectively. Then, a TSV is formed by filling copper inside the through holes 51 and 52 in which the titanium film is formed. As the filling material, tungsten or polysilicon may be used in addition to copper. After the TSV is formed, metal wirings 45 and 46 are formed on the through holes 51 and 52, respectively. The metal used here is arbitrary as long as it is suitable for wiring.

FIG. 8 is a diagram illustrating the completed semiconductor device 1. In the semiconductor device 1 shown in FIG. 8, an upper cover 47 made of a dielectric material such as SiO ₂ is formed so as to cover the aluminums 45 and 46. Further, the bonding PAD 48 is formed of, for example, copper. The bonding PAD 48 is connected to a wiring (not shown) in the third semiconductor wafer 30. That is, the bonding PAD 48 plays a role of an electrode taken out from the semiconductor device 1, that is, a so-called electrode pad. When the bonding PAD 48 is used, the bonding PAD 48 and an external wiring (not shown) can be connected by wire bonding.

  Although the example using the bonding PAD 48 has been described, an electrode bump (not shown) is provided on the back surface 10b of the first semiconductor wafer 10, and the electrode bump and an external wiring (not shown) are connected by face-down bonding. The configuration may be such that:

<Explanation of flowchart>
The manufacturing procedure of the semiconductor device 1 will be described with reference to FIG. For example, an operator (or a robot) prepares a first semiconductor wafer 10a before bonding, a second semiconductor wafer 20a before bonding, and a third semiconductor wafer 30a before bonding, and manufactures the semiconductor wafer shown in FIG. Start the procedure.

  In step S10, the operator polishes and planarizes the surface 10f of the first semiconductor wafer 10a and the surface 20f of the second semiconductor wafer 20a to bond them to each other (FIGS. 2A and 2A). (b)), and proceed to step S20.

  In step S20, the operator joins the surface 20f of the second semiconductor wafer 20a to the surface 10f of the first semiconductor wafer 20a before joining (FIG. 3). The alignment between the two is performed, for example, using a measuring device (not shown) using an infrared interference method.

  In step S30, the operator thins the second semiconductor wafer 20a by grinding and polishing the back surface 20b of the second semiconductor wafer 20a (FIG. 4A), and proceeds to step S40. In step S40, the operator polishes and flattens the front surface 30f of the third semiconductor wafer 30a to join the back surface 20 of the second semiconductor wafer 20 (FIG. 4B), and proceeds to step S50.

  In step S50, the operator joins the front surface 30f of the third semiconductor wafer 30a to the back surface 20b of the second semiconductor wafer 20 before joining (FIG. 5A). The alignment between the two is performed using a measuring device using an infrared interference method, as in the case of step S20.

  In step S60, the operator thins the third semiconductor wafer 30a by grinding and polishing the back surface 30b of the third semiconductor wafer 30a (FIG. 5B), and proceeds to step S70. In step S70, the worker adjusts the total thickness by polishing the back surface 10b of the first semiconductor wafer 10a (FIG. 6A), and proceeds to step S80.

  In steps S80 to S100, the operator forms a TSV. In step S80, the operator forms a photoresist pattern as follows. That is, the worker applies a photoresist to the back surface 30b of the third semiconductor wafer 30, and exposes only a position corresponding to the TSV scheduled position. Thereafter, the photoresist 40 at the TSV expected position is removed by development. Thus, a pattern of the photoresist 40 is formed (FIG. 6B).

  In step S90, after forming the photoresist pattern, the operator performs anisotropic etching using an ion beam etching device (not shown) to form through holes 51 and 52 (FIG. 7A). ), And proceed to step S100. In step S100, the operator removes the photoresist 40 remaining after the etching, and then forms a titanium film on the inner wall surfaces 51a and 52a of the through holes 51 and 52, respectively. The worker further fills the insides of the through holes 51 and 52 with the titanium film formed therein with copper using a plating apparatus (not shown), thereby forming a TSV (FIG. 7B).

In step S110, the worker covers the through holes 51 and 52 with aluminum 45 and 46, respectively, and forms an upper cover 47 made of a dielectric material such as SiO ₂ so as to cover the aluminum 45 and 46 (FIG. 8). The process illustrated in FIG. 9 ends.

  According to the semiconductor device 1 and the method of manufacturing the same according to the present embodiment, the following operational effects can be obtained.

(1) The semiconductor device 1 is provided after bonding the second semiconductor wafer 20 having the wiring 25, the third semiconductor wafer 30 having the wiring 35, and the second semiconductor wafer 20 and the third semiconductor wafer 30. And a TSV 52t for connecting the wiring 25 and the wiring 35. As a result, the two semiconductor wafers can be short-connected.

(2) The second semiconductor wafer 20 and the third semiconductor wafer 30 have the wiring 25 and the wiring 35 at positions where the TSVs 52t are to be provided, respectively. For a semiconductor wafer that does not need to be connected via the TSV 52t, the wiring at the predetermined position can be omitted.

(3) Since the TSV 52t penetrates the wiring 35 of the wiring 35 and the wiring 25, the depth of the TSV 52t can be suppressed as compared with the case where both the wirings penetrate.

(4) Since the etching rates of the wiring 25 and the wiring 35 are different, the TSV 52t that penetrates one wiring 35 and reaches the other wiring 25 can be easily formed.

(5) Since the wiring 25 is made of titanium and the wiring 35 is made of aluminum, the TSV 52t that penetrates the aluminum wiring 35 and reaches the titanium wiring 25 can be easily formed.

(6) Even when the wiring 25 is made of metal (titanium) and the wiring 35 is made of a non-metallic conductor (polysilicon), the TSV 52t that passes through the polysilicon wiring 35 and reaches the titanium wiring 25 can be easily formed. Can be formed.

(7) The method for manufacturing the semiconductor device 1 includes a step of joining the second semiconductor wafer 20 having the wiring 25 and the third semiconductor wafer 30 having the wiring 35 (S50); Forming a TSV 52t for connecting the wiring 25 and the wiring 35 after the bonding with the third semiconductor wafer 3 (S80 to S100). Thereby, the semiconductor device 1 in which two semiconductor wafers are connected by a short path can be obtained.

(8) After the joining step (S50) and before the step of forming the TSV 52t (S100), a step (S60) of thinning the third semiconductor wafer 30 is provided. That is, the second semiconductor wafer 20 is used as a support substrate when the third semiconductor wafer 30 is thinned. This can save members and simplify the manufacturing process.

(9) The step of forming the TSV 52t includes the step of providing a hole 52 from the third semiconductor wafer 30 side to the wiring 25 of the second semiconductor wafer 20 through the wiring 35 (S90), and the inner wall surface 52a of the hole 52. Connecting the wiring 25 and the wiring 35 by providing titanium (S100). Thus, the TSV 52t can be easily formed using the holes 52 provided.

(10) The step of providing the holes 52 is an etching step, and the etching rate of the wiring 25 is lower than the etching rate of the wiring 35. Thus, the hole 52 for forming the TSV 52t that penetrates the one wiring 35 and reaches the other wiring 25 can be easily formed.

(11) Since the semiconductor device 1 is configured to be separated into the first semiconductor wafer 10, the second semiconductor wafer 20, and the third semiconductor wafer 30, for example, each of the sensor unit, the memory unit, and the signal processing unit The most suitable process formation technique can be used. Thereby, the performance of each of the sensor unit, the memory unit, and the signal processing unit can be sufficiently exhibited, and the high-performance semiconductor device 1 can be provided.

(12) After bonding the first semiconductor wafer 10a and the second semiconductor wafer 20a in a semi-finished state, the second semiconductor wafer 20 is thinned. That is, the first semiconductor wafer 10a is used as a support substrate when the second semiconductor wafer 20 is thinned. This can save members and simplify the manufacturing process.

(13) Further, after bonding the third semiconductor wafer 30a to the first semiconductor wafer 10a and the second semiconductor wafer 20 in a semi-finished state, the third semiconductor wafer 30 is thinned. That is, the first semiconductor wafer 10a and the second semiconductor wafer 20 are used as support substrates when the third semiconductor wafer 30 is thinned. This can save members and simplify the manufacturing process.

(14) Since the through holes 51 and 52 are formed after the total thickness is adjusted, the aspect ratio of the holes is reduced, and the through holes 51 and 52 can be formed with high accuracy. In addition, as the conductor material to be filled in the through holes 51 and 52 having a low aspect ratio, not only a metal material such as tungsten (W) having a good covering property but also a metal such as copper (Cu) having a poor covering property as compared with tungsten is used. Materials can be used. That is, the semiconductor device 1 suitable for mass productivity can be manufactured by suppressing the manufacturing cost by not being restricted by the conductor material.

The following modifications are also within the scope of the present invention, and one or more of the modifications can be combined with the above-described embodiment.
(Modification 1)
A semiconductor wafer may be further stacked from above the upper cover 47. For example, a semiconductor wafer similar to the second semiconductor wafer 20a and the third semiconductor wafer 30a is joined from the top of the semiconductor device 1 of FIG. 8 (however, the bonding PAD 48 is not provided) after being planarized.

  That is, a predetermined number (for example, two layers) of semiconductor wafers are joined to the semiconductor device 1 to which a predetermined number (three layers in the above embodiment) of the semiconductor wafers 10 to 30 are joined, and then the uppermost layer is formed. A TSV is provided for connecting the semiconductor wafer from the semiconductor wafer to the uppermost semiconductor wafer of the semiconductor device 1 (third semiconductor wafer 30).

  According to the first modification, after all the semiconductor wafers (five layers) are joined, instead of providing TSVs for connecting four layers from the uppermost semiconductor wafer to the lowermost semiconductor wafer, they are joined later. By providing a TSV for connecting a predetermined number (two layers) of semiconductor wafers, the aspect ratio of the through-hole formed for the TSV is reduced, and the through-hole can be formed with high precision. Further, the degree of freedom in the manufacturing process of the semiconductor device can be increased.

(Modification 2)
In the above-described embodiment, the TSV connecting the three layers from the third semiconductor wafer 30 to the first semiconductor wafer 10 in the semiconductor device 1 and the two layers of the third semiconductor wafer 30 and the second semiconductor wafer 20 The example with the connected TSV has been described. In addition, a TSV that connects the two layers of the third semiconductor wafer 30 and the first semiconductor wafer 10 may be provided.

  As described above, the semiconductor wafer connected by the TSV may be appropriately selected when designing the semiconductor device.

  Although various embodiments and modified examples have been described above, the present invention is not limited to these contents. Other embodiments that can be considered within the scope of the technical concept of the present invention are also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10, 10a ... First semiconductor wafer 10b, 20b, 30b ... Back surface 10f, 20f, 30f ... Front surface 15, 25 ... Wiring (titanium etc.)
20, 20a ... second semiconductor wafers 26, 35, 36 ... wiring (aluminum etc.)
30, 30a: third semiconductor wafer 40: photoresist 51, 52: through holes 51a, 52a: inner wall surfaces 51t, 52t: TSV

Claims (10)

A first semiconductor substrate having a first wiring;
A second semiconductor substrate laminated with the first semiconductor substrate and provided with a second wiring and a third wiring;
A third semiconductor substrate stacked with the second semiconductor substrate, provided with a fourth wiring and a fifth wiring, and provided with a sixth wiring and a seventh wiring on the opposite surface of the stacked wiring;
The first wiring, the second wiring, and the fourth wiring are provided in a hole that penetrates the second semiconductor substrate and the third semiconductor substrate, and penetrate the second wiring and the fourth wiring. A first connecting portion for connecting the second wiring and the sixth wiring;
A hole penetrating the third semiconductor substrate and having a depth different from a hole provided with the first connection portion , penetrating the fifth wiring, and forming the third wiring, the fifth wiring, and the seventh wiring. A second connection unit for connecting
A semiconductor device comprising: The semiconductor device according to claim 1,
The first semiconductor substrate and the second semiconductor substrate are silicon;
The semiconductor device, wherein the first connection portion and the second connection portion are TSV (through-silicon via). The semiconductor device according to claim 1 or 2,
A semiconductor device in which a material of the first wiring and the third wiring and a material of the second wiring, the fourth wiring and the fifth wiring have different etching rates. The semiconductor device according to any one of claims 1 to 3,
The material of the first wiring and the third wiring is titanium,
A semiconductor device wherein the material of the second wiring, the fourth wiring, and the fifth wiring is aluminum. The semiconductor device according to any one of claims 1 to 3,
The material of the first wiring and the third wiring is metal,
A semiconductor device in which a material of the second wiring, the fourth wiring, and the fifth wiring is a nonmetallic conductor. A step of laminating a first semiconductor substrate having a first wiring, a second semiconductor substrate having a second wiring and a third wiring, and a third semiconductor substrate having a fourth wiring and a fifth wiring; When,
After laminating the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate, the second wiring and the fourth wiring are penetrated, and the first wiring, the second wiring, and Forming a first connection portion for connecting to the fourth wiring;
Forming a second connection portion penetrating the fifth wiring and connecting the third wiring and the fifth wiring;
A sixth wiring connected to the first connection portion and a seventh wiring connected to the second connection portion are provided on a surface of the first semiconductor substrate opposite to a surface laminated with the second semiconductor substrate. Forming a;
Have a,
The step of forming the second connection portion includes:
Providing a hole from the third semiconductor substrate side through the fifth wiring to a third wiring of the second semiconductor substrate;
Providing a conductor in the hole and connecting the third wiring and the fifth wiring.
A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 6 ,
A method of manufacturing a semiconductor device, comprising a step of thinning the third semiconductor substrate after the step of stacking and before the step of forming the first connection portion and the second connection portion. The method for manufacturing a semiconductor device according to claim 6 , wherein
The step of forming the first connection portion includes:
Providing a hole from the third semiconductor substrate side through the fourth wiring and the second wiring to the first wiring of the first semiconductor substrate;
Providing a conductor in the hole to connect the first wiring, the second wiring, and the fourth wiring. The method for manufacturing a semiconductor device according to claim 6 , wherein
The step of providing the hole is an etching step,
A method of manufacturing a semiconductor device, wherein an etching rate of a material of the third wiring is lower than an etching rate of a material of the fifth wiring. The method of manufacturing a semiconductor device according to claim 8 ,
The step of providing the hole is an etching step,
A method of manufacturing a semiconductor device, wherein an etching rate of a material of the first wiring is lower than an etching rate of a material of the second wiring and a material of the fourth wiring.

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