JP6640940B2 - Memory system control method - Google Patents

Description

  The present embodiment relates to a method for controlling a memory system.

  Conventionally, a memory system using a NAND flash memory as a storage medium is known. The memory system manages translation information that records a correspondence between logical position information (logical address) specified from the outside and position information (physical address) physically indicating a position in a storage medium. .

  In addition, when a transfer error of the data requested to be written occurs, the memory system may be required to return to a state immediately before starting to write the data requested to be written. Such a write mode is referred to as an atomic write.

US Patent Application Publication No. 2015/0074336

  An object of one embodiment is to provide a memory system that can execute atomic writes efficiently.

  According to one embodiment, a method for controlling a memory system includes a first step, a second step, a third step, and a fourth step. The first step is a first translation information indicating a correspondence between logical position information designated by a host and physical position information indicating a physical position in a nonvolatile first memory. In the volatile second memory. The second step is a step of managing second translation information that is the first translation information cached in the second memory. In the third step, when the first data included in the data group received from the host is stored in the first memory in a first write mode which is a mode for specifying an atomic write, the second translation information is copied. And updating the third translation information stored in the second memory. The fourth step is a step of reflecting the third translation information on the second translation information when the first write mode ends.

FIG. 1 is a diagram illustrating an example of a configuration of the memory system according to the first embodiment. FIG. 2 is a diagram illustrating an example in which a write command in the atomic write mode is transmitted and received. FIG. 3 is a diagram schematically illustrating a data processing unit and a position management unit in the NAND memory according to the first embodiment. FIG. 4 is a diagram illustrating a region. FIG. 5 is a diagram illustrating the first table cache, the second table, and the second table cache. FIG. 6 is a diagram illustrating a data configuration example of the second table. FIG. 7 is a diagram illustrating a data configuration example of log information. FIG. 8 is a flowchart illustrating an example of the rewinding process. FIG. 9 is a diagram illustrating an example of a configuration of a memory system according to the second embodiment. FIG. 10 is a diagram illustrating a cache of the second table according to the second embodiment. FIG. 11 is a flowchart illustrating the operation of the data processing unit according to the second embodiment. FIG. 12 is a flowchart illustrating the operation of the management unit according to the second embodiment. FIG. 13 is a diagram illustrating a mounting example of the memory system.

  Hereinafter, a memory system according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited by these embodiments.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a configuration of the memory system according to the first embodiment. The memory system 1 is, for example, an SSD (Solid State Drive). Hereinafter, a case where a NAND flash memory (hereinafter, referred to as a NAND memory) is used as the nonvolatile memory will be described as an example.

  The memory system 1 is configured to be connectable to the host 2. For example, a CPU (Central Processing Unit), a personal computer, a portable information device, a server, and the like correspond to the host 2. As an interface standard for communication between the memory system 1 and the host 2, any interface standard can be adopted. Two or more hosts 2 may be connected to the memory system 1 at the same time. The host 2 and the memory system 1 may be connected via a network.

  The memory system 1 transmits and receives data to and from the host 2 in response to an access request from the host 2. The access request includes a write command and a read command. The access request includes address information logically indicating an access position. As the address information, for example, LBA (Logical Block Address) can be adopted. When NVMe is adopted as an interface standard for communication between the memory system 1 and the host 2, for example, the address information may include namespace identification information and LBA. The name space is a logical address space specified by the identification information of the namespace. That is, when NVMe is employed, the memory system 1 can manage a plurality of logical address spaces.

  The memory system 1 can receive a write command in the atomic write mode from the host 2. Atomic write is one of the write modes. According to the atomic write mode, when the reception of the user data requested to be written in the mode is interrupted, it is required to return to the state immediately before the writing of the data requested to be written in the mode is started. . Regarding one or more user data requested to be written between the start of the atomic write mode and the end thereof, from the viewpoint of the host 2, all the user data is written, or one user data is written. Is also not written.

  FIG. 2 is a diagram illustrating an example in which a write command in the atomic write mode is transmitted and received. An atomic write mode is referred to as an atomic write mode. The host 2 transmits an atomic write start command before transmitting an atomic write mode write command (S101). The atomic write start command is provided with an atomic write ID (AW ID). The memory system 1 can execute an atomic write of a plurality of threads. AW ID is identification information for distinguishing threads. A thread is a combination of a plurality of write commands in the atomic write mode that are issued in chronological order from the start of the atomic write to the end of the atomic write. In the memory system 1, when a plurality of threads are input in parallel, each thread is individually terminated. One of the plurality of threads is requested to be terminated by an end command for terminating the one thread.

  Note that the memory system 1 may be configured such that a thread is identified by information different from the AW ID. For example, the target space of the atomic write may be specified by a logical address for each thread. For example, if it is constrained that two or more threads cannot execute in one namespace, the threads can be identified by the namespace identification information.

  In S101, the host 2 starts a thread with AW ID = 0, for example. After transmitting the start command, the host 2 can transmit a write command in the atomic write mode belonging to the thread started by the start command (S102). The write command in the atomic write mode includes the AW ID. The memory system 1 can identify the thread to which the write command belongs based on the AW ID included in the write command in the atomic write mode. The host 2 can transmit a normal write command, that is, a write command that is not in the atomic write mode, during the write command in the atomic write mode (S103). Write commands that are not in atomic write mode do not include the AW ID. Alternatively, a write command that is not in the atomic write mode may include an invalid value (for example, “NULL”) as the AW ID. Before terminating one thread, the host 2 can transmit a start command to start another thread (S104) or transmit a write command of the other thread (S105). The write command of another thread means a write command belonging to another thread. In the process of S105, the thread with AW ID = 1 is started before the thread with AW ID = 0. Before terminating the thread with AW ID = "0", the host 2 can transmit an end command for terminating the thread with AW ID = "1" (S106). By including the AW ID in the end command, the memory system 1 can recognize the thread to be terminated. Note that the host 2 can also transmit an end command for terminating the thread with AW ID = "0" before terminating the thread with AW ID = "1". In the example of FIG. 2, the host 2 transmits the write command of the thread with AW ID = 0 again (S107), and thereafter transmits the end command to terminate the thread with AW ID = 0. (S108).

  The memory system 1 includes a host interface unit 11, a NAND memory 12, a NAND controller 13, a RAM (Random Access Memory) 14, and a control unit 15.

  The control unit 15 is configured by an arithmetic device such as a CPU (Central Processing Unit). The control unit 15 functions as the data processing unit 151 and the management unit 152 by executing a program stored in a predetermined position in the memory system 1 in advance. The storage location of the program is arbitrarily designed. For example, the program is stored in the NAND memory 12 in advance and loaded into the RAM 14 at the time of startup. The control unit 15 executes the program loaded in the RAM 14. Some or all of the functions of the data processing unit 151 may be realized by hardware. Some or all of the functions of the management unit 152 may be realized by hardware.

  The data processing unit 151 executes data transfer between the host 2 and the NAND memory 12. When writing user data to the NAND memory 12, the data processing unit 151 writes a write log 1223 (described later) corresponding to the user data to the NAND memory 12.

  The management unit 152 performs management of management information. The management information includes translation information, statistical information, block information, and the like. The translation information is information in which a correspondence between a logical address and address information (physical address) indicating a physical position in the NAND memory 12 is recorded. The statistical information is information that records the usage status of the memory system 1, the power-on time, the number of power-offs, and the like. The block information is information that records, for example, the number of rewrites, the number of valid data, and the like for each physical block (described later). The management unit 152 performs translation between a logical address and a physical address.

  When the thread is interrupted, the management unit 152 executes a process of returning the translation information to a state before the thread was started (hereinafter, a rewind process). The suspension of a thread refers to an event in which all user data requested to be written by a series of write commands constituting the thread cannot be written to the NAND memory 12. For example, when the power of the memory system 1 is cut off during the reception of a thread, the thread is suspended.

  The host interface unit 11 is an interface device for communicating with the host 2. For example, the host interface unit 11 executes transfer of user data between the host 2 and the RAM 14 under the control of the data processing unit 151.

  The NAND controller 13 is an interface device for accessing the NAND memory 12. The NAND controller 13 transfers user data or management information between the RAM 14 and the NAND memory 12 under the control of the control unit 15. Although not described in detail, the NAND controller 13 can perform an error correction process.

  The NAND memory 12 is a nonvolatile storage medium that functions as a storage. The NAND memory 12 includes one or more chips.

  FIG. 3 is a diagram schematically illustrating a data processing unit and a position management unit in the NAND memory 12 according to the first embodiment. In a chip constituting the NAND memory 12, a data storage area is constituted by a plurality of physical blocks. Each physical block is composed of a plurality of physical pages. A physical page is a unit that can be accessed for writing and reading. In the physical block, the minimum unit in which data can be collectively erased is a physical block.

  In the data storage area, a physical address is assigned to a unit smaller than one physical page. Here, a unit to which a physical address is assigned is referred to as a cluster. Translation information is managed in cluster units. The size of one cluster may be equal to or different from the minimum access unit from the host 2. In the example of FIG. 3, one physical page is configured by ten clusters. In the example of FIG. 3, one physical block is configured by n (n is a natural number) physical pages.

  The RAM 14 is a storage medium for temporarily storing data. As the RAM 14, for example, a storage medium of a type faster than the NAND memory 12 can be adopted. As the RAM 14, for example, a volatile or non-volatile storage medium can be adopted. As the RAM 14, for example, DRAM (Dynamic RAM), SRAM (Static RAM), FeRAM (Ferroelectric RAM), MRAM (Magnetoresistive RAM), PRAM (Phase change RAM) and the like can be adopted.

  In the NAND memory 12, a management information area 121 and a user data area 122 are secured. Each of the areas 121 and 122 is composed of, for example, a plurality of physical blocks. The user data area 122 stores one or more data (user data 1221) requested to be written by the host 2 and log information 1222. Here, a description will be given assuming that the size of each user data 1221 is the size of a cluster.

  The management information area 121 stores a first table 1211. In the management information area 121, an LUT area 1212 in which one or more second tables 1213 are stored is secured. The LUT area 1212 includes, for example, a plurality of physical blocks. The first table 1211 and one or more second tables 1213 constitute translation information.

  In the RAM 14, a write buffer 141, a read buffer 142, and an LUT cache area 144 are secured. The RAM 14 stores a first table cache 143.

  The write buffer 141 and the read buffer 142 are buffers for data transfer between the host 2 and the NAND memory 12. Data is input / output to / from the write buffer 141 and the read buffer 142 in accordance with the rules of the FIFO. The write buffer 141 stores the user data received by the host interface unit 11 from the host 2. The user data stored in the write buffer 141 is written to the user data area 122 by the NAND controller 13. The read buffer 142 stores the user data 1221 read from the user data area 122 by the NAND controller 13. The user data 1221 stored in the read buffer 142 is transferred to the host 2 by the host interface unit 11.

  The first table 1211 and one or more second tables 1213 are cached in the RAM 14 and updated on the RAM 14. The LUT cache area 144 is an area where the second table 1213 is cached. The second table 1213 cached in the LUT cache area 144 is referred to as a second table cache 145. The first table cache 143 is the first table 1211 cached in the RAM 14.

  The translation information will be described with reference to FIG. 4, FIG. 5, and FIG. The management unit 152 hierarchizes the translation information into two or more hierarchies. Here, as an example, the management unit 152 manages the translation information as a two-layer table group. The first table 1211 and the first table cache 143 correspond to the first layer table. One or more second tables 1213 and one or more second table caches 145 correspond to the second layer table.

  The management unit 152 divides the logical address space into a plurality of subspaces. The subspace is described as a region. FIG. 4 is a diagram illustrating a region. Each region includes a plurality of clusters having consecutive logical addresses. Here, each region includes m (m is a natural number) clusters. Each region is identified by a region number (Region No.). The region number is obtained, for example, by shifting the logical address to the right. The region #i ranges from the logical address i * m to the logical address ((i + 1) * m-1). An address in a region is represented by an offset from the start of the region. Digits higher than the predetermined digit of the logical address correspond to the region number, and digits lower than the predetermined digit of the logical address correspond to addresses in the region.

  FIG. 5 is a diagram illustrating the first table cache 143, the second table 1213, and the second table cache 145. In the first table cache 143, a table address is recorded for each region. The table address is address information that physically indicates the storage location of the second table 1213 or the second table cache 145. Here, both the table address in the RAM 14 indicating the storage position of the second table cache 145 and the table address in the NAND memory 12 indicating the storage position of the second table 1213 are stored in the first table cache 143. It is recorded every time. When the second table cache 145 is not cached for a certain region, an invalid value (for example, “NULL”) is recorded as the table address of the storage position of the second table cache 145 corresponding to the region. The management unit 152 can determine whether or not the second table cache 145 is cached for the certain region based on whether or not “NULL” is recorded as a table address in the RAM 14. The management of whether or not the second table cache 145 is cached for each region is not limited to the above method.

  FIG. 6 is a diagram illustrating a data configuration example of the second table 1213. The second table 1213 and the second table cache 145 have, for example, the same data configuration. In the second table 1213, an address (data address) physically indicating the storage location of the user data 1221 is recorded for each address in the region. If each region is composed of m clusters, the second table 145 includes at least m entries. An invalid value (for example, “NULL”) is recorded in the second table 145 for a logical address not associated with a physical address.

  The management unit 152 reads translation information from the NAND memory 12 to the RAM 14 and uses the translation information read into the RAM 14. Use includes updating and referencing. The management unit 152 reads, for example, all entries of the first table 1211 into the RAM 14 as the first table cache 143. The management unit 152 reads, for example, the second table 1213 including at least an entry to be used from the one or more second tables 1213 stored in the LUT area 1212 into the LUT cache area 144.

  When the management unit 152 updates the translation information read into the RAM 14, the translation information stored in the RAM 14 becomes different from the translation information stored in the NAND memory 12. The state of the translation information stored in the RAM 14 that is different from the translation information stored in the NAND memory 12 is referred to as dirty. The management unit 152 writes a dirty part of the translation information into the NAND memory 12 at a predetermined timing. The dirty part of the translation information is changed to a non-dirty state by being written into the NAND memory 12. The unit of management, dirty or non-dirty, is arbitrarily designed. The management unit 152 manages, for example, whether the first table cache 143 is dirty or non-dirty for each entry. The management unit 152 manages, for example, whether the second table cache 145 is dirty or non-dirty.

  For example, when writing user data from the write buffer 141 to the NAND memory 12, the data processing unit 151 requests an update request for updating the correspondence between the logical address and the physical address with respect to the logical address indicating the position of the user data. Is transmitted to the management unit 152. The management unit 152 updates the second table cache 145 including the logical address specified by the update request based on the update request. The management unit 152 manages the updated second table cache 145 as dirty. In addition, the management unit 152 manages a record indicating the dirty second table cache 145 among the records of the first table cache 143 as dirty. After writing the dirty second table cache 145 in the LUT area 1212, the management unit 152 manages the second table cache 145 as non-dirty. The management unit 152 updates a dirty record among the records of the first table cache 143 in accordance with the writing to the LUT area 1212 of the second table cache 145, and then writes the updated record to the management information area 121. After writing the updated record in the management information area 121, the management unit 152 manages the record as non-dirty.

  The timing of writing the dirty part of the translation information into the NAND memory 12 is arbitrarily designed. For example, the timing is determined based on the total size of dirty portions of the translation information. For example, at the timing when the total size of dirty portions of the translation information exceeds a predetermined threshold, some or all of the dirty portions are written to the NAND memory 12. When the power is turned off, at least a dirty part of the translation information is written to the NAND memory 12. When the memory system 1 includes a battery, when the power is turned off, the management unit 152 may be driven by the energy stored in the battery. When the power is turned off, at least a dirty part of the translation information is written to the management information area 121. When the NAND memory 12 has an area for urgently evacuating the management information (emergency evacuation area) in addition to the management information area 121 and the user data area 122, at least the dirty part of the translation information is urgently evacuated. Can be written to the area. As described above, the management unit 152 manages the translation information in the RAM 14 so that the dirty part of the translation information is not lost as much as possible.

  The first table 1211 may have the same data configuration as the first table cache 143, or may have a data configuration in which the recording of the table address in the LUT cache area 144 is omitted. .

  FIG. 7 is a diagram illustrating a data configuration example of the log information 1222. The log information 1222 includes one or more write logs 1223. Each write log 1223 is information indicating a correspondence relationship between a logical address and a physical address when the user data 1221 is written to the NAND memory 12 in cluster units. For example, one log information 1222 includes the write logs 1223 of all clusters included in one corresponding physical page. The log information 1222 corresponds to any of the user data 1221. For example, the log information 1222 is written in a cluster at a predetermined position (for example, the last cluster) in each physical block. In this embodiment, when a thread in the atomic write mode is interrupted, information for returning translation information to a state before writing user data requested to be written by the first write command of the thread to the NAND memory 12 is written. It is added to the log 1223.

  The write log 1223 includes a logical address 200, an old physical address 201, a new physical address 202, an AW ID 203, and a Start End Flag 204. The old physical address 201 is a physical address associated with the logical address 200 before the writing of the user data 1221. The new physical address 202 is a physical address newly associated with the logical address 200 by writing the corresponding user data 1221. In other words, the new physical address 202 is a physical address indicating the position where the corresponding user data 1221 has been written. The AW ID 203 is added to the write log 1223 of the user data 1221 requested to be written in the atomic write mode. The AW ID 203 is equal to the AW ID included in the write command in the atomic write mode. The Start End Flag 204 is a combination of a start flag indicating whether or not the user data 1221 has been written at the beginning of the thread and an end flag indicating whether or not the user data 1221 has been written at the end of the thread. is there. That is, the Start End Flag 204 has a size of at least 2 bits. The Start End Flag 204 is operated based on a start command and an end command.

  A case where user data requested to be written by a write command other than the atomic write mode is written from the write buffer 141 to the NAND memory 12 will be described below. The data processing unit 151 writes the logical address 200, the old physical address 201, and the new physical address 202 in the write log 1223. The data processing unit 151 does not use the AW ID 203 and the Start End Flag 204. For example, the data processing unit 151 records an invalid value (such as “NULL”) in the AW ID 203. The data processing unit 151 sets neither the start flag nor the end flag in the Start End Flag 204.

  A case in which user data requested to be written by an atomic write mode write command is written from the write buffer 141 to the NAND memory 12 will be described below. The data processing unit 151 records the AW ID 203 in the write log 1223 in addition to the logical address 200, the old physical address 201, and the new physical address 202. The data processing unit 151 sets a start flag in the Start End Flag 204 of the write log 1223 for the user data requested to be written by the first write command of each thread. The data processing unit 151 sets an end flag in the Start End Flag 204 of the write log 1223 for the user data requested to be written by the last write command of each thread. The data processing unit 151 performs, for write data belonging to each thread, a user command that has been requested to write by a write command that does not correspond to any of the first write command of each thread and the last write command of each thread. , Start End Flag 204, neither a start flag nor an end flag is set.

  For example, the end command is stored in the write buffer 141 by the data processing unit 151. When writing the user data requested to be written by the write command in the atomic write mode to the NAND memory 12, the data processing unit 151 uses the write command of the same thread as the user data to be written after the user data to be written. It is determined by referring to the write buffer 141 whether or not the end command has been received without intervention of the user data requested to be written. If the end command is received without intervention of the user data requested to be written by the write command of the same thread as the user data to be written, the data processing unit 151 determines that the user data to be written is a thread. Is determined to be user data requested to be written by the last write command.

  If the thread is interrupted, a write request is issued by the write command of the interrupted thread, and if there is already-written user data in the NAND memory 12, the physical address indicating the storage location of the user data is rewinded. As a result of the processing, a transition is made from the state associated with the logical address to the state not associated with the logical address. User data that is not associated with a logical address cannot be accessed from the host 2. Therefore, from the viewpoint of the host 2, the user data transmitted to the memory system 1 until the thread is interrupted is seen as not being written to the NAND memory 12. That is, when the thread is interrupted, from the viewpoint of the host 2, the memory system 1 appears to have returned to the state before the thread was started, so that the atomic write operation is realized.

  FIG. 8 is a flowchart illustrating an example of the rewinding process. First, the management unit 152 restores the first table cache 143 to the RAM 14 at the time when the interruption of the thread occurs.

  Subsequently, the management unit 152 reads a predetermined number of write logs 1223 from the write log 1223 that was last written when the interruption occurred, in the reverse order of the write order (S201). The management unit 152 identifies a thread to be canceled based on the read predetermined number of write logs 1223 (S202).

  Specifically, for example, the management unit 152 extracts all AW IDs from a predetermined number of read write logs 1223. For example, a predetermined number of read write logs 1223 include a write log 1223 in which AW ID = "0" is recorded, a write log 1223 in which AW ID = "1" is recorded, and an AW ID = "2". When including the write log 1223, the management unit 152 extracts AW ID = "0", AW ID = "1", and AW ID = "2". Then, the management unit 152 searches the predetermined number of read write logs 1223 for a write log 1223 having an end flag. When the write log 1223 having the end flag is obtained, the management unit 152 obtains the AW ID recorded in the write log 1223 having the end flag. Get the AW ID indicating the suspended thread by excluding the recorded AW ID. The management unit 152 identifies the suspended thread as a thread to be canceled.

  After the processing in S202, the management unit 152 selects the write log 1223 written last when the interruption occurred (S203). Then, the management unit 152 determines whether the selected write log 1223 is the write log 1223 related to the thread to be canceled (S204). Whether or not the selected write log 1223 is the write log 1223 related to the interrupted thread is included in any of the AW IDs indicating the thread in which the AW ID 203 recorded in the selected write log 1223 is interrupted. It can be determined based on whether or not it is performed.

  When the selected write log 1223 is the write log 1223 for the thread to be canceled (S204, Yes), the management unit 152 acquires the logical address 200 and the old physical address 201. Then, the management unit 152 changes the physical address associated with the acquired logical address 200 in the translation information to the acquired old physical address 201 (S205).

  For example, the management unit 152 acquires the storage position of the second table 1213 that records the correspondence relationship of the acquired logical address 200 by referring to the restored first table cache 143. Then, the management unit 152 reads the second table 1213 from the acquired storage position, and stores the read second table 1213 in the LUT cache area 144 as the second table cache 145. The management unit 152 updates the first table cache 143 in accordance with storing the second table cache 145 in the LUT cache area 144. Then, the management unit 152 executes the change by the processing of S205 on the second table cache 145. The management unit 152 manages the second table cache 145 changed by the processing in S205 as dirty. The management unit 152 manages the record indicating the second table cache 145 changed by the processing in S205 among the records in the first table cache 143 as dirty.

  Subsequent to the processing of S205, the management unit 152 determines whether a start flag is set in the selected write log 1223 (S206). When the start flag is set in the selected write log 1223 (S206, Yes), the management unit 152 deletes the thread indicated by the AW ID 203 recorded in the selected write log 1223 from the threads to be canceled (S206). S207). When the start flag is not set in the selected write log 1223 (S206, No), or after the processing of S207, the management unit 152 determines whether or not there is still a thread to be canceled (S208).

  When the selected write log 1223 is not the write log 1223 concerning the thread to be canceled (S204, No), or when the thread to be canceled still exists (S208, Yes), the management unit 152 writes the currently selected write log. A new write log 1223 written immediately before the log 1223 is newly selected (S209), and the process of S204 is executed for the newly selected write log 1223. If there is no thread to be canceled (S208, No), the management unit 152 ends the rewind process.

  As described above, according to the first embodiment, the data processing unit 151 records the write log 1223 every time user data is written to the NAND memory 12. Further, the data processing unit 151 records the start of the atomic write and the end of the atomic write in the write log 1223. When the thread is interrupted, the management unit 152 returns the translation information to the state before the thread was interrupted by reading the write log 1223 in the reverse order of the writing order. Thereby, the operation of the atomic write is realized.

  According to the above description, the data processing unit 151 writes the user data regardless of whether the write command requesting the writing of the user data is an atomic write mode write command or a non-atomic write mode write command. An update request is issued when writing to the NAND memory 12. If the write command requesting the write of the user data is an atomic write mode write command, the data processing unit 151 queues the update request internally, and receives the internally queued update request as an end command. May be transmitted to the management unit 152 after confirmation. As a result, the translation information is updated after the thread ends, so that the atomic write operation is realized without performing the rewinding process.

  Further, according to the above description, the management unit 152 manages the translation information in the RAM 14 so that a dirty part of the translation information is not lost as much as possible. When the dirty part of the translation information is lost, the management unit 152 reconstructs the translation information by referring to the write log 1223 in the reverse order of the write order, for example. When reconstructing the translation information, the management unit 152 specifies the thread to be canceled and reads the write log 1223 in the reverse order of the write order. The management unit 152 reads the write log 1223 that is not the write log 1223 for the thread to be canceled, and the logical address 200 of the write log 1223 is not associated with any physical address in the translation information. , The correspondence between the logical address 200 recorded in the write log 1223 and the new physical address 202 recorded in the write log 1223 is recorded in the translation information in an overwriting format. When the write log 1223 concerning the thread to be canceled is read, the management unit 152 reads the next write log 1223. The management unit 152 reconstructs the translation information by performing the above-described processing on the sequentially read write log 1223.

(Second embodiment)
FIG. 9 is a diagram illustrating an example of a configuration of a memory system according to the second embodiment. Note that components having the same functions as those of the first embodiment are given the same names and symbols as those of the first embodiment. A description of components having the same functions as those of the first embodiment will be omitted.

  The memory system 1a is connectable to the host 2. The memory system 1a may be configured to be connectable to a plurality of hosts 2. The memory system 1a can receive a write command in the atomic write mode from the host 2, similarly to the memory system 1 of the first embodiment. The memory system 1a includes a host interface unit 11, a NAND memory 12, a NAND controller 13, a RAM 14, and a control unit 15. The control unit 15 functions as a data processing unit 151a and a management unit 152a by executing a program stored in a predetermined position in the memory system 1a in advance.

  The data processing unit 151a executes data transfer between the host 2 and the NAND memory 12. The management unit 152a executes management of management information. The management information includes translation information, statistical information, block information, and the like. The management unit 152a executes translation between a logical address and a physical address. The management unit 152a manages the translation information in the RAM 14 so that a dirty part of the translation information is not lost as much as possible.

  In the NAND memory 12, a management information area 121 and a user data area 122 are secured. The user data area 122 stores one or more user data 1221 and log information 1222. In the second embodiment, the log information 1222 may not be recorded. The management information area 121 stores a first table 1211. In the management information area 121, an LUT area 1212 in which one or more second tables 1213 are stored is secured. In the RAM 14, a write buffer 141, a read buffer 142, and an LUT cache area 144 are secured. The RAM 14 stores a first table cache 143. The second table 1213 is stored in the LUT cache area 144.

  FIG. 10 is a diagram illustrating the cache of the second table 1213 according to the second embodiment. In the second embodiment, the second table 1213 of each region can be cached as one second table cache 145a. In addition, the second table 1213 of each region can be cached as one second table cache 145a and at the same time as one or more second table caches 145b. Each second table cache 145b is generated by duplicating the second table cache 145a of the corresponding region. The number of second table caches 145b for a region is equal to the number of threads that need to use the second table 1213 for that region. That is, the second table cache 145b is cached for each thread.

  The pointer 210 and the AW ID 211 are recorded in the second table cache 145a and the second table cache 145b. The AW ID 211 of the second table cache 145b indicates a thread that needs to use the second table cache 145b.

  The storage position of the second table cache 145a is indicated by the first table cache 143. The storage location of the second table cache 145b is not indicated by the first table cache 143. The pointer 210 forms a list structure for referring to the storage positions of one or more second table caches 145b having the second table cache 145a as a replication source from the second table cache 145a. That is, when there is one or more second table caches 145b whose replication source is the second table cache 145a, the pointer 210 of the second table cache 145a is one of the one or more second table caches 145b. The storage position of the second table cache 145b is shown. If there is no other second table cache 145b, a value indicating the end of the list structure (for example, “NULL”) is recorded in the pointer 210 of the one second table cache 145b. If there is another one or more second table caches 145b, the pointer 210 of the one second table cache 145b indicates one of the other one or more second table caches 145b. Indicates the storage location of If there is no second table cache 145b that has the second table cache 145a as a replication source, a value indicating, for example, the end of the list structure is recorded in the pointer 210 of the second table cache 145a.

  A method of managing the correspondence between the second table cache 145a and one or more second table caches 145b having the second table cache 145a as a copy source is a management method using the list structure of the pointer 210. It is not limited to only. The correspondence between the second table cache 145a and one or more second table caches 145b having the second table cache 145a as a copy source may be managed using a separately provided table. In addition, a dedicated entry is provided in the first table cache 143, and the correspondence between the second table cache 145a and one or more second table caches 145b having the second table cache 145a as a copy source is provided by the dedicated entry. Relationships may be managed. The pointer 210 may be a bidirectional pointer.

  When writing the user data requested to be written by the write command in the atomic write mode to the NAND memory 12, the management unit 152a uses the second table cache 145b of the corresponding thread. When writing user data requested to be written by a write command that is not in the atomic write mode to the NAND memory 12 and when reading user data from the NAND memory 12, the management unit 152a stores the second table cache 145a in the use.

  FIG. 11 is a flowchart illustrating the operation of the data processing unit 151a according to the second embodiment. The data processing unit 151a determines whether a write command has been received (S301). When a write command is received (S301, Yes), the data processing unit 151a stores the user data requested to be written by the write command in the write buffer 141 (S302). If no write command has been received (S301, No), the data processing unit 151a skips the processing of S302.

  Subsequently, the data processing unit 151a determines whether the write timing has come (S303). Any timing can be set as the write timing. For example, the write timing is determined based on the total size of the user data stored in the write buffer 141. For example, the write timing is a timing when the total size of the user data stored in the write buffer 141 exceeds a predetermined threshold. For example, the write timing is a timing at which a Flush command is received from the host 2. The Flush command is a command for writing all the user data stored in the write buffer 141 and not written in the NAND memory 12 to the NAND memory 12.

  When the write timing has come (S303, Yes), the data processing unit 151a selects one user data from the write buffer 141 (S304). The data processing unit 151a writes the selected user data to the NAND memory 12 (S305). The data processing unit 151a determines whether the written user data is the user data requested to be written by the write command in the atomic write mode (S306). If the written user data is not the user data requested to be written by the write command in the atomic write mode (S306, No), the data processing unit 151a transmits a first update request to the management unit 152a (S307). When the written user data is the user data requested to be written by the write command in the atomic write mode (S306, Yes), the data processing unit 151a transmits a second update request to the management unit 152a (S308).

  The first update request and the second update request are requests for updating the translation information. The first update request includes at least a logical address, an old physical address, and a new physical address. The logical address included in the first update request is a logical address specified by a write command requesting writing of user data. The old physical address is a physical address associated with the logical address included in the first update request before writing the user data. The new physical address is a physical address newly associated with a logical address by writing user data.

  The second update request includes at least the AW ID in addition to the logical address, the old physical address, and the new physical address. The AW ID included in the second update request indicates the thread to which the write command that requested the written user data belongs.

  If the write timing has not come (S303, No), or after the processing of S307 or S308, the data processing unit 151a determines whether or not an end command has been received (S309). If an end command has been received (S309, Yes), the data processing unit 151a sends an update confirmation request to the management unit 152a (S310).

  The update confirmation request is a request for reflecting the second table cache 145b corresponding to the thread terminated by the end command in the second table cache 145a of the copy source. The update confirmation request includes at least the AW ID indicating the thread terminated by the end command. The data processing unit 151a transmits a second update request for all write data requested to be written by the write command of the thread specified by the AW ID included in the end command, and then transmits an update confirmation request.

  When the end command has not been received (S309, No), or after the process of S310, the data processing unit 151a determines whether a read command has been received (S311). If a read command has been received (S311, Yes), the data processing unit 151a transmits a translation request to the management unit 152a (S312). The translation request includes at least the logical address specified by the read command. The management unit 152a translates the logical address included in the translation request, and returns the physical address obtained by the translation to the data processing unit 151a. The data processing unit 151a reads the user data from the position indicated by the returned physical address to the write buffer 141 (S313). The data processing unit 151a transmits the user data read to the write buffer 141 to the host 2 (S314). After the processing of S314, the data processing unit 151a executes the processing of S301 again.

  FIG. 12 is a flowchart illustrating an operation of the management unit 152a according to the second embodiment. The management unit 152a determines whether a first update request has been received (S401). When the first update request is received (S401, Yes), the management unit 152a determines whether or not the second table 1213 relating to the logical address included in the first update request is cached in the LUT cache area 144. (S402). When the corresponding second table 1213 is not cached in the LUT cache area 144 (S402, No), the management unit 152a reads the corresponding second table 1213 into the LUT cache area 144 as the second table cache 145a (S403). ). The management unit 152a records “NULL” in the pointer 210 and the AW ID 211 of the second table cache 145a.

  When the corresponding second table 1213 is cached in the LUT cache area 144 (S402, Yes), or after the processing of S403, the management unit 152a updates the second table cache 145a (S404). Specifically, the management unit 152a associates a logical address included in the first update request with a new physical address included in the first update request. After the processing in S404, the management unit 152a sets the updated entry in the second table cache 145a as dirty (S405). Further, the entry indicating the storage location of the updated second table cache 145a in the first table cache 143 is set as dirty (S406).

  When the first update request has not been received (S401, No), or after the processing of S406, the management unit 152a determines whether the second update request has been received (S407). When the second update request is received (S407, Yes), the management unit 152a determines whether the second table 1213 for translating the logical address included in the second update request is cached in the LUT cache area 144. Is determined (S408). When the relevant second table 1213 is not cached in the LUT cache area 144 (S408, No), the management unit 152a reads the relevant second table 1213 into the LUT cache area 144 as the second table cache 145a (S409). ). The management unit 152a records “NULL” in the pointer 210 and the AW ID 211 of the second table cache 145a.

  When the corresponding second table 1213 is cached in the LUT cache area 144 (S408, Yes), or after the processing of S409, the management unit 152a determines the second table related to the thread indicated by the AW ID included in the second update request. It is determined whether the two-table cache 145b (hereinafter, the target second table cache 145b) is cached in the LUT cache area 144 (S410). In the process of S410, the management unit 152a follows the pointer 210 in order from the second table cache 145a to update the second table cache 145b in which the same AW ID 211 as the AW ID included in the second update request is recorded. Search for.

  If the target second table cache 145b is not cached in the LUT cache area 144 (S410, No), the management unit 152a copies the target second table cache 145a to a free area of the LUT cache area 144, and The two-table cache 145b is generated (S411). NULL is recorded in the pointer 210 of the target second table cache 145b. The AW ID included in the second update request is recorded in the AW ID 211 of the target second table cache 145b.

  After the process of S411, the management unit 152a updates each pointer 210 forming the list structure (S412). Specifically, for example, the management unit 152a overwrites the pointer 210 at the end of the list structure with an address indicating the storage location of the target second table cache 145b. When the target second table cache 145b is cached in the LUT cache area 144 (S410, Yes), or after the processing of S412, the management unit 152a updates the target second table cache 145b (S413). Specifically, the management unit 152a associates the logical address included in the second update request with the new physical address included in the second update request.

  When the second update request has not been received (S407, No), or after the processing of S413, the management unit 152a determines whether or not the update confirmation request has been received (S414). When the update confirmation request is received (S414, Yes), the management unit 152a replaces all the second table caches 145b including the AW ID included in the update confirmation request as the AW ID 211 with the corresponding second table cache 145a. (S415).

  A specific example of the processing of S415 will be described below. The management unit 152a focuses on one second table cache 145b including the AW ID included in the update confirmation request as the AW ID 211. The management unit 152a classifies the entry of the noted second table cache 145b into an entry that has been updated since the noted second table cache 145b was generated and an entry that has not been updated. The management unit 152a writes the value recorded in the second table cache 145a of the copy source into the entry that has not been updated in an overwrite format. The management unit 152a records NULL in the AW ID 211 of the noted second table cache 145b, and updates the first table cache 143 to indicate the noted second table cache 145b. As a result, the focused second table cache 145b is subsequently treated as the second table cache 145a. The original second table cache 145a is deleted, for example. The management unit 152a updates each pointer 210 forming the list structure. The management unit 152a focuses on each of the second table caches 145b including the AW ID included in the update confirmation request as the AW ID 211, and executes the above-described series of processes on each of the focused second table caches 145b. .

  After the processing of S415, the management unit 152a sets all the second table caches 145a targeted for the processing of S415 as dirty (S416). Further, all the entries in the first table cache 143 indicating the storage positions of the second table cache 145a targeted for the processing of S415 are set as dirty (S417).

  When the update confirmation request has not been received (S414, No), or after the processing of S417, the management unit 152a determines whether a translation request has been received (S418). When the translation request is received (S418, Yes), the management unit 152a determines whether the second table 1213 relating to the logical address included in the translation request is cached in the LUT cache area 144 (S419). . When the relevant second table 1213 is not cached in the LUT cache area 144 (S419, No), the management unit 152a reads the relevant second table 1213 into the LUT cache area 144 as the second table cache 145a (S420). ). The management unit 152a records “NULL” in the pointer 210 and the AW ID 211 of the second table cache 145a. If the corresponding second table 1213 is cached in the LUT cache area 144 (S419, Yes), or after the processing of S420, the management unit 152a determines the logical address included in the translation request based on the second table cache 145a. Is translated into a physical address (S421). The management unit 152a returns the physical address obtained by the translation to the data processing unit 151a. When a translation request has not been received (S418, No), or after the process of S421, the management unit 152a executes the process of S401 again.

  As described above, in the second embodiment, the management unit 152a generates the second table cache 145b by duplicating the second table cache 145a. The management unit 152a uses the second table cache 145b when the user data requested to be written by the write command in the atomic write mode is written to the NAND memory 12. Upon termination of the atomic write mode, the management unit 152a reflects the second table cache 145b on the second table cache 145a. Since the second table cache 145a is not updated by the processing of the write command in the atomic write mode until the thread ends, if the thread is interrupted, a write request is issued by the write command of the interrupted thread, and the NAND memory When there is written user data in 12, the physical address indicating the storage location of the user data is not associated with the logical address by the second table cache 145a. Therefore, even if the second table cache 145a at the time when the thread is suspended is restored, the state of the restored second table cache 145a is a state where the thread has not been started, so that the atomic write operation is realized. .

  When the data processing unit 151 queues the update request until the end of the thread and the management unit 152 executes all the queued update requests at the end of the thread, the management unit 152 performs Need access to translation information. On the other hand, according to the second embodiment, when the thread ends, the management unit 152a executes the reflection of the translation information on a region-by-region basis. Can be.

  The management unit 152a uses the second table cache 145a when reading the user data 1221 requested to be read by the read command from the NAND memory 12. This allows the user data 1221 to be read from the NAND memory 12 based on the translation information in a state where the thread is not started, even during the execution of the thread.

  The management unit 152a uses the second table cache 145a when writing user data requested to be written by a write command that is not in the atomic write mode to the NAND memory 12. Thereby, even during the execution of the thread, it is possible to execute the writing of the user data to the NAND memory 12 based on the translation information in a state where the thread is not started.

  The management unit 152a reflects the second table cache 145b on the second table cache 145a in response to receiving the end command. Since the second table cache 145b is reflected in the second table cache 145a after the end of the thread, the memory system 1 does not write any user data requested to be written by the write command of the thread before the end of the thread. After the end of the thread, the state shifts to a state where all the user data requested to be written by the write command of the thread is written. That is, the operation of the atomic write is realized.

  The management unit 152a updates the second table cache 145b in response to the writing of the last user data requested to be written among the one or more user data requested to be written by the thread write command to the NAND memory 12, Then, the second table cache 145b is reflected in the second table cache 145a.

  The data processing unit 151a can receive write commands of a plurality of threads in parallel. The management unit 152a generates a second table cache 145b for each thread. As a result, the memory system 1a can realize an atomic write operation of a plurality of threads.

  The end command includes identification information for specifying a corresponding thread. Thereby, the memory system 1 can specify the thread to be terminated based on the identification information included in the end command.

  The size of the logical address space provided externally by the memory system 1 is called a notation capacity. The indicated capacity of the memory system 1 is smaller than the capacity of an area where the user data 1221 can be written (that is, the user data area 122). The user data area 122 stores user data 1221 whose storage location is associated with a logical address by translation information and user data 1221 whose storage location is not associated with a logical address by translation information. It is. The capacity obtained by subtracting the indicated capacity from the capacity of the user data area 122 is called a surplus capacity. The user data area 122 can store the user data 1221 whose storage position is not associated with the logical address by the translation information up to the maximum capacity. In the first embodiment, the total amount of user data that can be received from the host 2 by all the threads being processed cannot exceed the surplus capacity. That is, the total size of the user data receivable by the data processing unit 151a up to the last first data of the thread from the first user data of the thread is equal to or less than the spare capacity of the memory system 1a.

(Third embodiment)
FIG. 13 is a diagram illustrating an implementation example of the memory system 1. The memory system 1 is implemented in, for example, the server system 1000. The server system 1000 includes a disk array 2000 and a rack mount server 3000 connected by a communication interface 4000. Any standard can be adopted as the standard of the communication interface 4000. The rack mount server 3000 is configured by mounting one or more hosts 2 on a server rack. The plurality of hosts 2 can access the disk array 2000 via the communication interface 4000.

  The disk array 2000 is configured by mounting one or more memory systems 1 on a server rack. In the disk array 2000, one or more hard disk units may be mounted in addition to the memory system 1. Each memory system 1 can execute a command from each host 2. Each memory system 1 has a configuration in which the first or second embodiment is adopted. Thereby, each memory system 1 can easily execute the atomic write.

  In the disk array 2000, for example, each memory system 1 may be used as a cache of one or more hard disk units. In the disk array 2000, a storage controller unit that constructs a RAID using one or more memory systems 1 may be mounted.

  Although several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

  1, 1a memory system, 2 hosts, 12 NAND memories, 15 control units, 121 management information area, 122 user data area, 141 write buffer, 143 first table cache, 144 LUT cache area, 145, 145a, 145b second table Cache, 151, 151a data processing unit, 152, 152a management unit, 1000 server system, 1211 first table, 1212 LUT area, 1213 second table, 1221 user data, 1222 log information, 1223 write log, 2000 disk array, 3000 Rack mount server, 4000 communication interface.

Claims (13)

The first translation information indicating the correspondence between the logical position information specified by the host and the physical position information indicating the physical position in the nonvolatile first memory is converted to the volatile second information. A first step of caching in memory;
A second step of managing second translation information that is the first translation information cached in the second memory;
In a case where first data included in a data group received from the host is stored in the first memory in a first write mode which is a mode for specifying an atomic write, the first memory is a copy of the second translation information and is a copy of the second memory. A third step of updating the third translation information stored in
A fourth step of reflecting the third translation information on the second translation information when the first write mode ends;
A method for controlling a memory system comprising: A step of acquiring physical location information of a data transfer source in the first memory by referring to the second translation information when performing data transfer from the first memory to the host;
The control method of a memory system according to claim 1, further comprising: Updating the second translation information when storing second data, which is data received from the host, in the first memory in a second write mode different from the first write mode;
The method according to claim 2, further comprising: A fifth step of receiving an end command from the host,
The fourth step is a step of reflecting the third translation information in the second translation information in response to receiving the end command.
A method for controlling a memory system according to claim 1. In the fourth step, after the reception of the end command and after updating the third translation information according to the last first data in the data group, the third translation information is converted to the second translation information. Steps to reflect on information,
A method for controlling a memory system according to claim 4. A sixth step of receiving the plurality of data groups in parallel,
A seventh step of generating the third translation information for each data group;
The control method of a memory system according to claim 1, further comprising: A fifth step of receiving an end command for each data group;
The fourth step is a step of reflecting third translation information on a data group corresponding to the received end command in the second translation information.
A method for controlling a memory system according to claim 6. In the fourth step, the third translation information on the data group corresponding to the received end command is updated according to the last first data in the data group corresponding to the received end command. Reflecting the third translation information on the data group corresponding to the received end command in the second translation information.
A method for controlling a memory system according to claim 7. The end command includes identification information for identifying a corresponding data group,
A method for controlling a memory system according to claim 8. Storing the updated portion of the second translation information in the first memory at a predetermined timing;
A method for controlling a memory system according to claim 1. The predetermined timing includes a power-off timing,
A method for controlling a memory system according to claim 10. Restoring the second translation information based on the stored updated portion after power recovery, further comprising:
A method for controlling a memory system according to claim 11. Generating the third translation information by duplicating the second translation information when data included in the data group received from the host in the first write mode is first stored in the first memory. Further prepare,
A method for controlling a memory system according to claim 1.

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