JP6570045B2 - Compound semiconductor wafer processing method - Google Patents
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Description
本発明は、ＳｉＣ（シリコンカーバイト）やＧａＮ（ガリウムナイトライド）等の化合物半導体からなる化合物半導体ウエハの加工方法に関する。 The present invention relates to a method for processing a compound semiconductor wafer made of a compound semiconductor such as SiC (silicon carbide) or GaN (gallium nitride).
パワー半導体デバイスの材料として、Ｓｉ（シリコン）よりも電気を通しやすく、電力損失が発生しにくいＳｉＣやＧａＮといった化合物半導体が用いられるが、これらの化合物半導体は、ウエハ製造がＳｉに比べて難しいという問題がある。特に、ＳｉＣウエハは非常に硬く、通常機械研磨で３５０μｍ程度に加工された後、ＣＭＰ（化学機械研磨）を用いて表面の鏡面仕上げを行っている（例えば特許文献１参照。）。 As a material for power semiconductor devices, compound semiconductors such as SiC and GaN, which are easier to conduct electricity than Si (silicon) and are less likely to cause power loss, are used, but these compound semiconductors are difficult to manufacture as compared to Si. There's a problem. In particular, the SiC wafer is very hard, and after being processed to about 350 μm by normal mechanical polishing, the surface is mirror-finished using CMP (Chemical Mechanical Polishing) (see, for example, Patent Document 1).
しかしながら、近年、パワー半導体の薄板化が望まれており、ウエハを通常機械研磨によってさらに薄く研磨していくと、厚みが薄くなるにつれてウエハが徐々に反ってくるため、ウエハの中心部と端部とで厚みが変わってしまうことになる。このようにウエハの厚みが場所によって変わると、抵抗が変わり、場所によって特定が異なるウエハとなってしまう。 However, in recent years, thinning of power semiconductors has been desired, and when the wafer is further thinned by normal mechanical polishing, the wafer gradually warps as the thickness decreases. The thickness will change. Thus, when the thickness of the wafer changes depending on the location, the resistance changes, resulting in a wafer with different specifications depending on the location.
また、上記のように通常機械研磨後にＣＭＰを行った場合、化合物半導体の表面には通常機械研磨による加工層が含まれた状態である。すなわち、通常機械研磨では２０〜３０μｍの加工歪みが発生するが、この加工歪みはＣＭＰによって除去することができず、ＣＭＰ後の化合物半導体の表面にそのまま発生することになる。 Further, when CMP is performed after normal mechanical polishing as described above, the surface of the compound semiconductor is in a state where a processed layer by normal mechanical polishing is included. In other words, processing strain of 20 to 30 μm is usually generated by mechanical polishing, but this processing strain cannot be removed by CMP, and is generated as it is on the surface of the compound semiconductor after CMP.
そこで、本発明においては、加工歪みを発生させることなく薄板化することが可能な化合物半導体ウエハの加工方法を提供することを目的とする。 Accordingly, an object of the present invention is to provide a method for processing a compound semiconductor wafer that can be thinned without causing processing distortion.
本発明の化合物半導体ウエハの加工方法は、半導体元素である第１原子およびこの第１原子と異なる元素である第２原子がイオン結合した化合物半導体からなるウエハを加工する化合物半導体ウエハの加工方法であって、第１原子と反応するエッチングガスから生成した高密度プラズマによりウエハの表面をエッチングすること、このエッチング後のウエハの表面の第２原子を含む残存粒子層を機械研磨により除去することを含むことを特徴とする。 The compound semiconductor wafer processing method of the present invention is a compound semiconductor wafer processing method for processing a wafer made of a compound semiconductor in which a first atom which is a semiconductor element and a second atom which is an element different from the first atom are ion-bonded. Etching the surface of the wafer with a high-density plasma generated from an etching gas that reacts with the first atoms, and removing the residual particle layer containing the second atoms on the surface of the wafer after the etching by mechanical polishing. It is characterized by including.
本発明の加工方法によれば、高密度プラズマによって発生するイオンとウエハの化合物半導体結晶中の第１原子（半導体元素）とが反応し、ウエハ表面の第１原子が排除されていく。この第１原子の排除によってウエハ表面には第２原子を含む残存粒子層が形成されるが、この残存粒子層は化合物半導体と比較して非常に脆いため、徐々に崩壊しながらウエハ表面のエッチングが進行していく。このエッチング後、ウエハ表面には残った第２原子を含む残存粒子層を機械研磨により除去することで、表面に化合物半導体面が復元された化合物半導体ウエハが得られる。 According to the processing method of the present invention, ions generated by high-density plasma react with the first atoms (semiconductor elements) in the compound semiconductor crystal of the wafer, and the first atoms on the wafer surface are eliminated. Due to the elimination of the first atoms, a residual particle layer containing the second atoms is formed on the wafer surface. Since this residual particle layer is very brittle compared to the compound semiconductor, the wafer surface is etched while gradually declining. Will progress. After this etching, the residual particle layer containing the second atoms remaining on the wafer surface is removed by mechanical polishing, thereby obtaining a compound semiconductor wafer having the compound semiconductor surface restored on the surface.
本発明の化合物半導体ウエハの加工方法は、高密度プラズマのエッチングによる表面反応であるため、従来の通常機械研磨による加工歪みを発生させることなく、化合物半導体の表面の平面度を保ったまま均一に削っていくことで薄板化が可能であり、最終的にウエハ表面に残った脆い残存処理層を機械研磨により除去するため、薄板化による変形がほとんどなく、表面に化合物半導体面が復元された化合物半導体ウエハが得られる。 Since the compound semiconductor wafer processing method of the present invention is a surface reaction by high-density plasma etching, it does not generate processing distortion due to conventional normal mechanical polishing, and the surface of the compound semiconductor is kept flat while maintaining its flatness. It is possible to reduce the thickness by shaving, and finally remove the brittle residual processing layer remaining on the wafer surface by mechanical polishing, so there is almost no deformation due to thinning and the compound semiconductor surface is restored on the surface. A semiconductor wafer is obtained.
本発明の実施形態における加工対象は、半導体元素である第１原子およびこの第１原子と異なる元素である第２元素がイオン結合した化合物半導体からなる化合物半導体ウエハである。以下では、第１原子としてのＳｉ（シリコン）原子および第２原子としてのＣ（カーボン）原子がイオン結合した化合物半導体であるＳｉＣ（シリコンカーバイト）からなるＳｉＣウエハの加工方法について説明する。 An object to be processed in the embodiment of the present invention is a compound semiconductor wafer made of a compound semiconductor in which a first element that is a semiconductor element and a second element that is different from the first atom are ion-bonded. Hereinafter, a method for processing a SiC wafer made of SiC (silicon carbide), which is a compound semiconductor in which Si (silicon) atoms as first atoms and C (carbon) atoms as second atoms are ion-bonded, will be described.
本発明の実施形態におけるＳｉＣウエハの加工方法は、Ｓｉと反応するエッチングガスから生成した高密度プラズマによりウエハの表面をエッチングする第１工程（エッチング工程）と、このエッチング後のウエハの表面のＣを含む残存粒子層を機械研磨により除去する第２工程（機械研磨工程）とを含む。 An SiC wafer processing method according to an embodiment of the present invention includes a first step (etching step) of etching a wafer surface with high-density plasma generated from an etching gas that reacts with Si, and C on the wafer surface after the etching. And a second step (mechanical polishing step) of removing the residual particle layer containing the above by mechanical polishing.
以下、第１工程および第２工程について詳細に説明する。 Hereinafter, the first step and the second step will be described in detail.
＜第１工程（エッチング工程）＞
図１は本発明の実施の形態における化合物半導体ウエハのエッチング工程に用いる加工装置を示す説明図、図２はウエハに対する磁場、電場および電子流の方向とエッチング状態を示す説明図である。
<First step (etching step)>
FIG. 1 is an explanatory view showing a processing apparatus used in an etching process of a compound semiconductor wafer according to an embodiment of the present invention, and FIG. 2 is an explanatory view showing directions of magnetic field, electric field and electron flow with respect to the wafer and an etching state.
図１に示すように、本発明の実施の形態における化合物半導体ウエハの加工装置１は、真空容器２と、ウエハ１１（図２参照。）を搭載する陰極板３と、真空容器２外側に配置され、磁場を発生させるコイル４と、コイル印加直流電源４ａと、磁場方向反転切換スイッチ４ｂと、電場生成のための電源である電源部５と、エッチングガスのＣＦ4のボンベ６と、添加ガスＡｒ、Ｏ2のボンベ７と、パージガスＮ2のボンベ８と、ターボ分子ポンプ９と、ロータリーポンプ１０とを有する。 As shown in FIG. 1, a compound semiconductor wafer processing apparatus 1 according to an embodiment of the present invention is disposed outside a vacuum vessel 2, a cathode plate 3 on which a wafer 11 (see FIG. 2) is mounted, and the vacuum vessel 2. The magnetic field generating coil 4, the coil applied DC power source 4a, the magnetic field direction reversal changeover switch 4b, the power source unit 5 serving as the power source for generating the electric field, the CF 4 cylinder 6 of the etching gas, and the additive gas. Ar, O 2 cylinder 7, purge gas N 2 cylinder 8, turbo molecular pump 9, and rotary pump 10 are provided.
ウエハ１１は直径２インチ〜４インチ〜６インチ以上、厚さ２００μｍ〜２５０μｍ〜３００μｍ〜３５０μｍ〜４００μｍ以上のものが対象である。陰極板３は、このウエハ１１を搭載可能な大きさの例えばＳＵＳ３１６製の板である。真空容器２は、このウエハ１１が搭載された陰極板３が収容される大きさの角型容器である。電源部５は、最大出力１０００Ｗの１３．５６ＭＨｚの交番電圧の高周波電源（ＲＦ電源）５ａを有する。ターボ分子ポンプ９は３５０リットル／秒、ロータリーポンプ１０は１０００リットル／分である。 The wafer 11 has a diameter of 2 inches to 4 inches to 6 inches or more and a thickness of 200 μm to 250 μm to 300 μm to 350 μm to 400 μm or more. The cathode plate 3 is a plate made of, for example, SUS316 having a size capable of mounting the wafer 11. The vacuum container 2 is a rectangular container having a size that accommodates the cathode plate 3 on which the wafer 11 is mounted. The power supply unit 5 includes a high frequency power supply (RF power supply) 5a having an alternating voltage of 13.56 MHz with a maximum output of 1000 W. The turbo molecular pump 9 is 350 liters / second, and the rotary pump 10 is 1000 liters / minute.
真空容器２内の陰極板３上にウエハ１１を載せ、真空容器２内を高真空に排気後、真空容器２内にボンベ６よりエッチングガスを封入する。エッチングガスの濃度は、１０-2〜１０-3Ｔｏｒｒ程度の希薄ガス状態とする。エッチングガスとしては第１原子であるＳｉと反応するフッ化炭素ＣＦ4を用いているが、Ｃ2Ｆ8等の他のフッ化炭素を用いることも可能である。また、エッチングガスとしては、フッ化炭素のみの場合と、他のガスを混合する場合があり、ボンベ７からアルゴンガスＡｒ、酸素ガスＯ2を添加してもよい。 The wafer 11 is placed on the cathode plate 3 in the vacuum vessel 2, the inside of the vacuum vessel 2 is evacuated to a high vacuum, and then an etching gas is sealed in the vacuum vessel 2 from the cylinder 6. The concentration of the etching gas is a lean gas state of about 10 −2 to 10 −3 Torr. As the etching gas, fluorocarbon CF 4 that reacts with Si, which is the first atom, is used, but other fluorocarbons such as C 2 F 8 can also be used. In addition, as the etching gas, there may be a case where only fluorocarbon or another gas is mixed, and argon gas Ar and oxygen gas O 2 may be added from the cylinder 7.
この希薄エッチングガスを封入した真空容器２内で、図２に示すように磁場Ｂと電場Ｅを直交方向に与えて電子流を生起し、エッチングガスをその電子流の電子で電離させて高密度プラズマを生成する。より詳しくは、電源部５により陰極板３と真空容器２（陽極）との間に交番電圧を印加して電場Ｅを形成するとともに、コイル４により同電場Ｅの方向に直交するように磁場Ｂを与えて、これらと直交方向にウエハ１１のまわりを回転するベクトル積Ｅ×Ｂの電子流を形成し、同電子流の電子でエッチングガスを分離させて高密度プラズマを生成する。 In the vacuum vessel 2 in which the dilute etching gas is sealed, as shown in FIG. 2, a magnetic field B and an electric field E are applied in the orthogonal directions to generate an electron flow, and the etching gas is ionized by the electrons of the electron flow to increase the density. Generate plasma. More specifically, an alternating voltage is applied between the cathode plate 3 and the vacuum vessel 2 (anode) by the power supply unit 5 to form the electric field E, and the magnetic field B is orthogonal to the direction of the electric field E by the coil 4. To form an electron current having a vector product E × B rotating around the wafer 11 in a direction orthogonal to these, and separating the etching gas with the electrons of the electron current to generate a high-density plasma.
この高密度プラズマで真空容器２内に配置したウエハ１１の表面をエッチングする。このとき、高密度プラズマによって発生するフッ化物イオンＦ-とウエハ１１のＳｉＣ結晶中のＳｉ原子とが反応し、ウエハ１１表面のＳｉ原子が排除されていく。図３は代表的な４Ｈ構造のＳｉＣにおいて、プラズマエッチングによりＳｉＣ結晶中のＳｉ原子が排除される様子を示す説明図である。図３に示すように、密度プラズマによって発生するフッ化物イオンＦ-とＳｉ原子とが反応し、ＳｉＦｘの反応生成物として真空排除され、ウエハ１１表面にはＣ原子が残ることになる。 The surface of the wafer 11 placed in the vacuum vessel 2 is etched with this high-density plasma. At this time, fluoride ions F − generated by the high-density plasma react with Si atoms in the SiC crystal of the wafer 11 to eliminate Si atoms on the surface of the wafer 11. FIG. 3 is an explanatory view showing a state in which Si atoms in the SiC crystal are eliminated by plasma etching in a typical 4H-structured SiC. As shown in FIG. 3, fluoride ions F − and Si atoms generated by the density plasma react to be evacuated as a reaction product of SiFx, and C atoms remain on the surface of the wafer 11.
このＳｉ原子の排除によってウエハ１１表面にはＣ原子を含む残存粒子層１２（図２参照。）が形成される。この残存粒子層１２はＳｉＣと比較して非常に脆いため、徐々に崩壊しながらウエハ１１表面のエッチングが進行していく。このエッチング後、ウエハ１１表面にはＣ原子を含む残存粒子層１２が２０〜３０μｍの厚みで残る。 By eliminating this Si atom, a residual particle layer 12 (see FIG. 2) containing C atoms is formed on the surface of the wafer 11. Since this residual particle layer 12 is very brittle compared to SiC, the etching of the surface of the wafer 11 proceeds while gradually breaking down. After this etching, a residual particle layer 12 containing C atoms remains on the surface of the wafer 11 with a thickness of 20 to 30 μm.
なお、このエッチング工程は、上記のように高密度プラズマのエッチングによる表面反応であるため、従来の通常機械研磨による加工歪みを発生させることなく、平面度を保ったまま化合物半導体の表面を均一に削っていくことが可能である。 Since this etching process is a surface reaction by etching with high-density plasma as described above, the surface of the compound semiconductor is made uniform while maintaining flatness without generating processing distortion due to conventional normal mechanical polishing. It is possible to sharpen.
＜第２工程（機械研磨工程）＞
次に、上記エッチング後のウエハ１１表面のＣ原子を含む残存粒子層１２を機械研磨により除去する。Ｃ原子の残存粒子層１２はＳｉＣと比較して非常に脆いため、通常機械研磨により容易に除去することが可能である。図４は機械研磨によるウエハ表面状態の変遷を拡大写真により示した図である。図４に示すように、プラズマエッチング直後はウエハ表面がＣ原子の残存粒子層により覆われているが、この残存粒子層を通常機械研磨することで、ＳｉＣ面が鏡面となって現れる。最終的には、ＣＭＰ加工することによってさらに加工歪みの少ないＳｉＣ面を実現することが可能である。
<Second step (mechanical polishing step)>
Next, the residual particle layer 12 containing C atoms on the surface of the wafer 11 after the etching is removed by mechanical polishing. Since the C atom residual particle layer 12 is very brittle compared to SiC, it can usually be easily removed by mechanical polishing. FIG. 4 is an enlarged photograph showing the transition of the wafer surface state due to mechanical polishing. As shown in FIG. 4, the wafer surface is covered with a residual particle layer of C atoms immediately after plasma etching, but the SiC surface appears as a mirror surface by normal mechanical polishing of the residual particle layer. Ultimately, it is possible to realize a SiC surface with less processing distortion by CMP.
このように、本実施形態における化合物半導体ウエハの加工方法では、高密度プラズマのエッチングによる表面反応であるため、従来の通常機械研磨による加工歪みを発生させることなく、ＳｉＣの表面を均一に削っていくことで薄板化が可能であり、最終的にウエハ１１表面に残った脆い残存粒子層１２を機械研磨により除去するため、薄板化による変形がほとんどなく、表面に化合物半導体面が復元された化合物半導体ウエハが得られる。本実施形態における化合物半導体ウエハの加工方法では、加工前の厚さ３５０μｍ程度から加工後１５０μｍ〜１００μｍ程度まで平面度を保ったまま薄板化が可能である。 As described above, in the compound semiconductor wafer processing method according to the present embodiment, since the surface reaction is performed by etching with high-density plasma, the surface of SiC is uniformly shaved without generating processing distortion due to conventional normal mechanical polishing. It is possible to reduce the thickness of the wafer 11 and finally remove the fragile residual particle layer 12 remaining on the surface of the wafer 11 by mechanical polishing. Therefore, there is almost no deformation due to the reduction of the thickness, and the compound semiconductor surface is restored on the surface. A semiconductor wafer is obtained. In the compound semiconductor wafer processing method according to the present embodiment, it is possible to reduce the thickness of the compound semiconductor wafer while maintaining its flatness from about 350 μm before processing to about 150 μm to 100 μm after processing.
なお、上記実施形態においては、第１元素としてＳｉ原子および第２原子としてＣ原子がイオン結合した化合物半導体であるＳｉＣからなるＳｉＣウエハの加工について説明したが、同様に、第１原子としてＧａ原子および第２原子としてＮ原子がイオン結合した化合物半導体であるＧａＮからなるＧａＮウエハにも適用可能である。 In the above embodiment, the processing of the SiC wafer made of SiC, which is a compound semiconductor in which Si atoms as the first elements and C atoms as the second atoms are ion-bonded, has been described. Similarly, Ga atoms as the first atoms The present invention is also applicable to a GaN wafer made of GaN, which is a compound semiconductor in which N atoms are ion-bonded as the second atoms.
本発明の化合物半導体ウエハの加工方法は、パワー半導体デバイスの材料であるＳｉＣやＧａＮ等の化合物半導体からなる化合物半導体ウエハを薄板化する方法として有用である。 The compound semiconductor wafer processing method of the present invention is useful as a method for thinning a compound semiconductor wafer made of a compound semiconductor such as SiC or GaN, which is a material of a power semiconductor device.
１ 加工装置
２ 真空容器
３ 陰極板
４ コイル
４ａ コイル印加直流電源
４ｂ 磁場方向反転切換スイッチ
５ 電源部
５ａ 高周波電源
６ ＣＦ4のボンベ
７ Ａｒ、Ｏ2のボンベ
８ Ｎ2のボンベ
９ ターボ分子ポンプ
１０ ロータリーポンプ
１１ ウエハ
１２ 残存粒子層
1 machining apparatus 2 vacuum chamber 3 cathode plate 4 coils 4a coil applied DC power supply 4b field direction reversal cylinder 7 Ar, cylinder 9 turbomolecular pump 10 of the cylinder 8 N 2 for O 2 transfer switch 5 Power unit 5a frequency power source 6 CF 4 Rotary pump 11 Wafer 12 Residual particle layer
Claims (3)
真空容器内の陰極板上にウエハを搭載し、前記陰極板と前記真空容器との間に交番電圧を印加して電場Ｅを形成するとともに、前記真空容器外側に配置されるコイルにより前記電場Ｅの方向に直交するように磁場Ｂを与えて、前記電場Ｅおよび前記磁場Ｂと直交方向に前記ウエハのまわりを回転するベクトル積Ｅ×Ｂの電子流を形成し、前記電子流の電子で前記第１原子と反応するエッチングガスを分離させて生成した高密度プラズマのエッチングによる表面反応により前記ウエハの表面の前記第１原子を排除し、平面度を保ったまま前記ウエハの表面を均一に削っていくこと、
このエッチング後のウエハの表面に残った前記第２原子の残存粒子層を機械研磨により除去すること
を含む化合物半導体ウエハの加工方法。 A compound semiconductor wafer processing method for processing a wafer made of a compound semiconductor in which a first atom which is a semiconductor element and a second atom which is an element different from the first atom are ion-bonded,
A wafer is mounted on a cathode plate in a vacuum vessel, an alternating voltage is applied between the cathode plate and the vacuum vessel to form an electric field E, and the electric field E is generated by a coil disposed outside the vacuum vessel. A magnetic field B is applied so as to be orthogonal to the direction of the electric field E, and an electron current having a vector product E × B rotating around the wafer in a direction orthogonal to the electric field E and the magnetic field B is formed. the first atom of the surface of the wafer is eliminated by by that surface reaction for etching a high-density plasma generated by separating the etching gas that reacts with the first atom, uniform surface of the wafer while maintaining the flatness To sharpen ,
A method of processing a compound semiconductor wafer, comprising removing the residual particle layer of the second atoms remaining on the surface of the wafer after the etching by mechanical polishing.
前記第２原子はＣである
請求項１または２に記載の化合物半導体ウエハの加工方法。 The first atom is Si;
The method for processing a compound semiconductor wafer according to claim 1, wherein the second atom is C.
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| JPS57124438A (en) * | 1981-01-26 | 1982-08-03 | Rikagaku Kenkyusho | Ion beam etching for silicon carbide |
| JPS6037129A (en) * | 1983-08-10 | 1985-02-26 | Hitachi Ltd | Equipment for manufacturing semiconductor |
| JPS62216335A (en) * | 1986-03-18 | 1987-09-22 | Fujitsu Ltd | Dry etching method |
| JP3052266B2 (en) * | 1997-11-28 | 2000-06-12 | 株式会社日立製作所 | Plasma processing method |
| JP2006032655A (en) * | 2004-07-16 | 2006-02-02 | Kyoto Univ | Method for manufacturing silicon carbide substrate |
| JP5103025B2 (en) * | 2006-02-10 | 2012-12-19 | 九州電通株式会社 | Method for removing surface layer of silicon wafer |
| JP5614677B2 (en) * | 2010-02-25 | 2014-10-29 | 国立大学法人大阪大学 | Precision processing method and apparatus for difficult-to-process materials |
| JP5869280B2 (en) * | 2011-09-29 | 2016-02-24 | 住友電工デバイス・イノベーション株式会社 | Manufacturing method of semiconductor device |
| KR101723780B1 (en) * | 2013-12-20 | 2017-04-05 | 엔지케이 인슐레이터 엘티디 | Substrate including gallium nitride layer and process for manufacturing same |
| JP6547100B2 (en) * | 2014-02-25 | 2019-07-24 | 国立大学法人九州大学 | Combined processing apparatus and workpiece processed by the apparatus |
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