JP6386231B2 - Memory device with magnetic tunnel junction element - Google Patents

Description

  The present invention relates to a storage device including a magnetic tunnel junction element.

  A magnetic tunnel junction (MTJ) element having non-volatility, high-speed response, rewrite endurance, high integration, etc. has attracted attention, and various research and development have been made.

  The MTJ element is used in various storage circuits such as a flip-flop, a large capacity storage circuit, and a cache circuit in a logic circuit (see Patent Documents 1 and 2). Since writing to the MTJ element enables low current spin injection magnetization reversal writing (current writing), magnetic field writing is hardly used.

JP 2013-229721 A JP 2013-191873 A

  The MTJ element is a non-volatile storage element, and data stored in the MTJ element is not lost even when power supply is stopped. Therefore, in order to erase all data stored in a storage device having a plurality of MTJ elements, it is necessary to write data for initialization in all MTJ elements. When the writing method of the MTJ element is current writing, as a method for erasing all the data stored in the storage device, a process of selecting one MTJ element one by one and flowing a predetermined current through the selected MTJ element is performed. Although there are methods that are performed sequentially, this method has a problem that initialization processing takes time and effort.

  Some flip-flops have an input terminal for inputting a reset signal or a preset signal generated by a signal generating circuit and initializing (reset or preset) stored data. This input terminal is connected to the signal generation circuit, and the number of wirings connecting the flip-flop and the signal generation circuit increases as the number of flip-flops increases. Furthermore, in order to perform initialization simultaneously with the entire apparatus including a plurality of flip-flops, it is necessary to arrange a fan-out buffer, a delay buffer, and the like, which further complicates the circuit configuration.

  Even when initializing a mass storage circuit using an MTJ element, it is usually necessary to sequentially select and designate memory cells and sequentially write predetermined data, so that the initialization process takes time.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a storage device that can easily initialize an MTJ element when a writing method is current writing with a simple circuit configuration. .

The storage device according to the present invention includes:
A plurality of storage elements each comprising a pair of magnetic tunnel junction elements;
Writing means for individually writing data to the plurality of storage elements;
Magnetic field writing means for writing common data by applying a magnetic field to the plurality of storage elements,
The magnetic tunnel junction element includes a first layer in which the magnetization direction is fixed and a second layer in which the magnetization direction is not fixed, and the magnetization direction of the first layer and the second layer When the magnetization directions are parallel to each other, the resistance is low, and when the magnetization directions are antiparallel, the resistance is high.
The pair of magnetic tunnel junction elements constituting each storage element has either one of the magnetic tunnel junction elements in which the magnetization direction of the first layer and the magnetization direction of the second layer are parallel to each other. The direction of magnetization of the first layer and the direction of magnetization of the second layer of the other magnetic tunnel junction element are set to be complementary to each other,
The magnetic field writing means includes a current line through which a current flows.
Of the pair of magnetic tunnel junction elements constituting each storage element, the first magnetic tunnel junction element and the second magnetic tunnel junction element have the first magnetic tunnel junction element generated by one magnetic field generated by one current flowing through the current line. The direction of magnetization of the first layer of one magnetic tunnel junction element is parallel to the direction of magnetization of the second layer, and the direction of magnetization of the first layer of the second magnetic tunnel junction element is The magnetization directions of the second layer are arranged at positions where they are antiparallel to each other.

For example, the magnetization directions of the first layers of each of the pair of magnetic tunnel junction elements are set in the same direction, and each of the pair of magnetic tunnel junction elements is caused by a magnetic field generated by a current flowing through the current line. The second layers are arranged at positions where the magnetization directions are opposite to each other.

For example, the magnetization directions of the first layers of each pair of magnetic tunnel junction elements are set in opposite directions, and each pair of magnetic tunnel junction elements is caused by a magnetic field generated by a current flowing through the current line. The magnetization directions of the second layers are arranged at the same direction.

The storage device is, for example,
A plurality of storage elements comprising a pair of magnetic tunnel junction elements;
Writing means for individually writing data to the plurality of storage elements by causing a current corresponding to the data to be written to flow through a magnetic tunnel junction element constituting the storage element to be written;
A magnetic line writing unit that includes a current line for flowing a current that generates a magnetic field, and stores common data by applying a magnetic field to the plurality of storage elements;
Each of the magnetic tunnel junction elements includes a first layer whose magnetization direction is fixed and a second layer whose magnetization direction is not fixed, and the magnetization direction of the first layer and the second layer Low resistance when the magnetization directions of the layers are parallel to each other, high resistance when the layers are antiparallel,
The pair of magnetic tunnel junction elements constituting each of the memory elements is configured such that the direction of magnetization of the first layer and the direction of magnetization of the second layer of any one of the magnetic tunnel junction elements are parallel to each other. The direction of magnetization of the first layer and the direction of magnetization of the second layer of the other magnetic tunnel junction element are set to be complementary to each other,
In the pair of magnetic tunnel junction elements constituting the memory element, the magnetization directions of the first layer and the second layer of one of the magnetic tunnel junction elements are parallel to each other due to the magnetic field generated by the magnetic field writing unit. And the magnetization directions of the first layer and the second layer of the other magnetic tunnel junction element are arranged to be antiparallel to each other.

The current line includes, for example, a word line, a bit line, a bit line bar, a power supply line, or a ground line.

The storage device is, for example,
A plurality of storage elements each comprising a magnetic tunnel junction element;
Writing means for individually storing data in the storage element;
A line including at least one of a power supply line and a ground line and arranged to surround a plurality of the storage elements ;
The power supply voltage or a ground voltage is applied to at least one power supply line and a ground line, or by supplying a current to the line, applies a magnetic field in the same direction in a plurality of said storage elements enclosed taken by the line A power supply control device for storing common data ;
Is provided.

For example, each of the storage elements includes a pair of magnetic tunnel junction elements,
The magnetic tunnel junction element includes a first layer whose magnetization direction is fixed and a second layer whose magnetization direction is not fixed,
When the magnetization direction of the first layer and the magnetization direction of the second layer are parallel to each other, the resistance is low, and when the magnetization direction is antiparallel, the resistance is high.
The magnetization directions of the first layers of the pair of magnetic tunnel junction elements constituting the memory element are set to be antiparallel to each other.
Further, for example, the storage device includes both a power line and a ground line,
Each of the power supply line and the ground line is disposed so as to surround the plurality of storage elements,
The power supply control device passes a current through at least one of a power supply line and a ground line.

According to the present invention, it is possible to easily initialize a plurality of storage elements including a magnetic tunnel junction element with a simple circuit configuration.

It is the figure which showed the structure of the memory | storage device which concerns on Embodiment 1 of this invention. It is the figure which showed the structure of the circuit module shown in FIG. FIG. 3 is a diagram illustrating a configuration of the flip-flop illustrated in FIG. 2. (A) is a diagram showing an MTJ element in a low resistance state, and (b) is a diagram showing an MTJ element in a high resistance state. (A) is a figure which shows the structure for generating the magnetic field for initialization based on Embodiment 1, (b) It is the figure which showed an example of the initialization electric current (pulse). It is the figure which showed the 1st example of arrangement | positioning of an MTJ element. It is the figure which showed the 2nd example of arrangement | positioning of an MTJ element. (A) is a diagram showing an MTJ element in a low resistance state, (b) is a diagram showing an MTJ element in a high resistance state, (c) is a diagram showing how one MTJ element is initialized, and (d) is a diagram showing how the MTJ element is initialized. It is a figure which shows a mode that a pair of MTJ element is initialized. It is the figure which showed the structure of the memory | storage device which concerns on Embodiment 2 of this invention. (A) is a cross-sectional view showing the structure of the memory cell shown in FIG. 9, and (b) is a diagram showing a state in which a magnetic field for initialization is applied to the memory cell. It is a figure which shows the structure for generating the magnetic field for initialization which concerns on Embodiment 2 of this invention. FIG. 6 is a circuit diagram showing a configuration of a memory cell according to Embodiment 3 of the present invention. (A) is the figure which showed the example of arrangement | positioning of a pair of MTJ element, (b) is the figure which showed the state which applied the magnetic field for initialization to a pair of MTJ element. (A) is a figure explaining arrangement | positioning of two MTJ elements based on Embodiment 4 of this invention, (b) and (c) are the magnetization directions of a free layer by applying the magnetic field of a different direction and magnitude | size sequentially. FIG. 5 is a diagram showing a procedure for initializing a memory cell by changing. It is a figure which shows the structure of the memory | storage device which concerns on Embodiment 5 of this invention. It is the figure which showed the structure of the memory | storage device which concerns on Embodiment 6 of this invention. It is the figure which showed the structure of the memory | storage device which concerns on Embodiment 7 of this invention. It is a figure for demonstrating the function which initializes neighboring MTJ with the initialization electric current. It is a figure for demonstrating the function which initializes a pair of nearby MTJ with the initialization electric current. It is a figure for demonstrating the function which initializes a pair of nearby MTJ with the initialization electric current.

(Embodiment 1)
Hereinafter, the memory device according to Embodiment 1 of the present invention will be described with reference to the drawings, taking an LSI (Large Scale Integration) chip 100 including a flip-flop including an MTJ (Magnetic Tunneling Junction) element as a memory element as an example. I will explain.

  As shown in FIG. 1, the LSI chip 100 includes a plurality of circuit modules 10A, 10B, 10C..., A power supply control circuit 31, a clock generation circuit 40, a power supply line 33, a ground line 35, a constant current. Sources 39a, 39b,...

  In the following description, the circuit modules 10A, 10B, 10C,.

  As shown in FIG. 2, the circuit module 10 has a circuit configuration in which various logic gates 15 and a flip-flop FF as a storage circuit are connected, and is connected to a power supply line 33 and a ground line 35 as shown in FIG. Then, it operates with power supplied from the power supply control circuit 31, and performs processing such as logical operation and storage. The circuit configuration itself of each circuit module 10 is arbitrary.

  The flip-flop FF included in the circuit module 10 is constituted by, for example, a D-type flip-flop shown in FIG. 3, and includes a data input terminal D, a data output terminal Q, a clock terminal CLK, and an MTJ element 12. With internal circuitry. Note that the flip-flop FF is not provided with a reset terminal (clear terminal) or a preset terminal for initializing data. Therefore, wiring for connecting the signal generation circuit for generating the reset signal and the preset signal and the flip-flop FF is unnecessary. The LSI chip 100 has a function of initializing data stored in a flip-flop FF arranged in the circuit module 10. In the following description, “initializing data” means resetting or presetting data. To reset the data means to set the data to “0”, and to preset the data means to set the data to “1”.

  Data “0” (in this embodiment, a low level signal) or “1” (in this embodiment, a high level signal) is input to the data input terminal D of the flip-flop FF. The clock signal generated by the clock generation circuit 40 is supplied to the clock terminal CLK. The flip-flop FF responds to the rising edge of the clock signal input to the clock terminal CLK (the timing at which the clock signal changes from low level to high level) and transfers the data input to the data input terminal D to the MTJ that is a storage element. The data is stored in the element 12 and the stored data is read out and output from the data output terminal Q. Note that the clock signal generated by the clock generation circuit 40 is directly input to the clock terminal CLK of the flip-flop FF shown in FIG. A clock gating circuit made up of, for example, AND gates may be arranged between the two.

  The MTJ element 12 is non-volatile, and the flip-flop FF does not lose its stored data even when the supply of power is stopped.

  As shown in FIGS. 4A and 4B, the MTJ element 12 includes three layers of a pin (fixed) layer 12a, an insulating layer 12b, and a free (movable) layer 12c. The MTJ element 12 has a bottom pin structure in which the magnetization directions of the pinned layer 12a and the free layer 12c are perpendicular to the stacking direction, and the pinned layer 12a is disposed in the lowest layer. The MTJ element 12 may have a magnetization direction of the pinned layer 12a and the free layer 12c that is parallel to the stacking direction, or may have a top pin structure in which the pinned layer 12a is arranged as the uppermost layer.

  The pinned layer 12a and the free layer 12c are made of a ferromagnetic material such as iron (Fe), a cobalt-iron alloy (Co), or a ferromagnetic Heusler alloy (eg, Co2FeAl, Co2MnSi, CoFeB).

  The pinned layer 12a has a fixed magnetization direction, and has the property that the magnetization direction does not change even when a current flows in the layer or the magnetic field MF is applied. On the other hand, the direction of magnetization of the free layer 12c is not fixed, and the direction of magnetization changes according to the direction and magnitude of the current flowing in the layer or the direction and magnitude of the magnetic field MF.

  The insulating layer 12b is a thin film provided between the pinned layer 12a and the free layer 12c, and is formed of a material such as magnesia (MgO), alumina (Al2O3), spinel single crystal (MgAl2O4), for example.

  The resistance value of the MTJ element 12 changes as the magnetization directions of the pinned layer 12a and the free layer 12c change relatively. As shown in FIG. 4A, the resistance value of the MTJ element 12 is small (hereinafter referred to as a low resistance state) when the magnetization directions indicated by the arrows of the pinned layer 12a and the free layer 12c are aligned. As shown in FIG. 4B, when the magnetization directions indicated by the arrows of the pinned layer 12a and the free layer 12c are in the antiparallel state, the MTJ element 12 has a large resistance value (hereinafter referred to as a high resistance state). Called).

  When a current equal to or greater than the threshold value flows from the pinned layer 12a to the free layer 12c, or a magnetic field MF in the same direction as the magnetization of the pinned layer 12a is applied to the MTJ element 12 in the low resistance state shown in FIG. Then, as shown in FIG. 4B, the magnetization direction of the free layer 12c changes in the opposite direction (left direction) to the magnetization of the pinned layer 12a, and the MTJ element 12 enters a high resistance state. On the other hand, when a current equal to or greater than the threshold value is passed from the free layer 12c to the pinned layer 12a to the MTJ element 12 in the high resistance state shown in FIG. Then, as shown in FIG. 4A, the magnetization direction of the free layer 12c changes in the same direction (right direction) as the magnetization of the pinned layer 12a, and the MTJ element 12 enters a low resistance state.

The internal circuit of the flip-flop FF switches between the high resistance state and the low resistance state of the MTJ element 12 depending on whether the data supplied to the data terminal D is “1” or “0” when the clock signal rises. Data stored in the MTJ element 12 is read from the circuit (writing means), that is, data “1” or “0” corresponding to the output terminal Q is output according to the high resistance state and low resistance state of the MTJ element 12 Circuit (reading means).
Any known circuit configuration of the flip-flop FF can be used.

  The power supply control circuit 31 is composed of, for example, a PMU (Power Management Unit). The power supply control circuit 31 normally applies the power supply voltage VDD to the power supply line 33 and applies the ground voltage Vss to the ground line 35. Thereby, power for operation is supplied to each circuit in the LSI chip 100. In addition, the power supply control circuit 31 supplies an operation control signal and operating power to the constant current source 39 at a timing of collectively initializing (resetting or presetting) the flip-flops FF arranged in the circuit module 10. The operation control signal includes a reset control signal for resetting data stored in the internal circuit of the flip-flop FF (set to “0”: setting the MTJ element 12 to a low resistance state), and an internal control circuit of the flip-flop FF. There is a preset control signal for presetting stored data (set to “1”: set MTJ element 12 to a high resistance state).

  The power supply line 33 is a line that is made of a conductor and supplies the power supply voltage VDD output from the power supply control circuit 31 to the circuits in the LSI chip 100. In the present embodiment, the power supply line 33 is disposed in an upper layer of the circuit component via an insulating layer. Of the power supply line 33, portions 33a, 33b,... (Hereinafter referred to as loop-shaped portions) disposed on the circuit module 10 are formed in a loop shape.

  The ground line 35 supplies the ground voltage VSS to all internal circuits.

  The constant current sources 39a, 39b,... Constitute a constant current circuit together with the loop portions 33a, 33b,. The constant current sources 39a, 39b,... Operate according to the control signal using the operating power supplied from the power supply control circuit 31 via the dedicated line, and the flip-flops FF are provided in the loop-like portions 33a, 33b, respectively. A constant current (reset current or preset current: hereinafter, collectively referred to as initialization current IR) for initializing all at once is applied. In the following description, the constant current sources 39a, 39b,.

  When the constant current sources 39a, 39b,... Operate, the power supply control circuit 31 does not apply the power supply voltage VDD to the power supply line 33, but separately to the constant current sources 39a, 39b,. Supply power.

  As shown in FIGS. 5 and 6, the flip-flop FF in the circuit module 10 has a magnetization direction of the pinned layer 12a in the power supply line 33 immediately below the conductors constituting the loop-shaped portions 33a, 33b. It arrange | positions in the vicinity of this conductor so that it may orthogonally cross with the direction of the electric current which flows.

  When the constant current source 39 receives a control signal from the power supply control circuit 31, the constant current source 39 supplies an initialization current IR to the loop-shaped portions 33a and 33b in the constant current circuit. The constant current source 39 sets the direction of current flowing through the loop-shaped portions 33a and 33b according to the control signal. An initialization current IR (reset current and preset current) in the reverse direction flows in the loop-shaped portions 33a and 33b depending on whether data is reset (“0”) or preset (“1”). When the initialization current IR flows through the loop portions 33a and 33b, a magnetic field is generated in the vicinity thereof. For example, as shown in FIG. 5A, when the initialization current IRa flows through the loop-shaped portion 33a, a magnetic field MFa is generated around the conductor, and when the initialization current IRb flows through the loop-shaped portion 33b, A magnetic field MFb is generated around the conductor. A magnetic field in the opposite direction is generated around the power supply line 33 (loop-like portions 33a and 33b) depending on whether the data is reset (“0”) or preset (“1”). Note that the initialization current IR is a pulse current having a predetermined writing time as shown in FIG. 5B, and the magnitude (amplitude) is equal to or greater than the milliampere.

  The strength of the magnetic field generated around the power supply line 33 (loop-like portions 33a and 33b) is inversely proportional to the distance from the power supply line 33 (distance in the direction perpendicular to the power supply line 33), and the MTJ element 12 is close to the power supply line 33. It receives a large magnetic field. Therefore, the MTJ element 12 to be initialized is disposed at a position close to the power line 33 so that the magnetic field MF generated around the power line 33 is applied. Specifically, as shown in FIG. 6, the MTJ element 12 to be initialized is arranged at a position immediately below the power supply line 33 and close to the power supply line 33. As a result, the magnetic field MF generated around the power supply line 33 is applied to the MTJ element 12, and the magnetization of the free layer 12c of the MTJ element 12 changes in the direction opposite to the direction of the magnetic field.

  The magnetization of the pinned layer 12a of the MTJ element 12 is set to be parallel to the magnetization direction of the free layer 12c at the time of resetting and to be antiparallel to the magnetization direction of the free layer 12c at the time of presetting. As a result, the MTJ element 12 enters a low resistance state when an initialization current IR (reset current) for resetting flows through the power supply line 33, and the initialization current IR (preset current) for presetting is set to the power supply line 33. When it flows into the high resistance state.

  Further, when the initialization current IR in the same direction flows through the plurality of power supply lines 33 (loop-like portions 33a and 33b) arranged in parallel as shown in FIGS. In the meantime, magnetic fields in opposite directions are generated (the magnetic fields are canceled). The MTJ element 12 to be initialized is arranged at intervals from the other power supply lines 33 so that the magnetization direction of the free layer 12c is changed only by the magnetic field generated around any one of the power supply lines 33. The crosses in FIG. 6 indicate that the direction of the initialization current IR flowing through the power supply line 33 is the direction from the front surface to the back surface.

  Next, the operation of the LSI chip 100 having the above configuration will be described.

(Normal time)
In the normal state, the power supply control circuit 31 applies the power supply voltage VDD to the power supply line 33 and applies the ground voltage Vss to the ground line 35. Thereby, power for operation is supplied to various circuits such as the circuit module 10, the power supply control circuit 31, and the clock generation circuit 40 in the LSI chip 100.

  The data input terminal D of the flip-flop FF in the circuit module 10 receives data “0” (low level signal) or “1” (high level signal) from the logic gate 15 and other flip-flops FF in the previous stage. Entered. The flip-flop FF writes input data to the MTJ element 12 by flowing a current corresponding to the data input to the input terminal D to the MTJ element 12 in response to the rising edge of the clock signal supplied to the clock terminal CLK. The data (memory data) corresponding to the resistance state of the MTJ element 12 is read out and output from the data output terminal Q.

  Here, the MTJ element 12 is a non-volatile storage element, and even if the supply of power from the power supply control circuit 31 to the circuit module 10 is stopped, the storage data of the MTJ element 12 is retained. When the supply of the power supply voltage VDD is resumed, the internal circuit of the flip-flop FF reads out data corresponding to the resistance state of the MTJ element 12 and re-outputs it from the data output terminal Q.

(Initialization operation)
Next, an operation (reset process) for collectively erasing data stored in the flip-flops FF provided in each circuit module 10 will be described.
It is assumed that a reset instruction signal is supplied from the outside and the power supply control circuit 31 is instructed to reset the circuit module 10. Then, the power supply control circuit 31 stops the operation for supplying the power supply voltage VDD to the power supply line 33. On the other hand, the power supply control circuit 31 supplies operating power and a reset control signal to the constant current source 39.

  As a result, each constant current source 39 has an initialization current IR (reset current) for the reset shown in FIGS. 5A and 5B in the loop-like portions 33a, 33b,. ) For a certain period. When the initialization current IR flows through the power supply line 33, a magnetic field MF is generated around the power supply line 33. Since the flip-flop FF is disposed immediately below the wirings constituting the loop-shaped portions 33a, 33b,..., The generated magnetic field MF is generated in each MTJ element 12 in each flip-flop FF as shown in FIG. To be applied. As a result, the magnetization direction of the free layer 12c of each MTJ element 12 is the same as the magnetization direction of the pinned layer 12a, resulting in a low resistance state. As a result, all flip-flops FF store data “0” and are reset.

Thereafter, the power supply control circuit 31 stops the supply of the reset control signal and the operating power to the constant current source 39, and stops the operation of the constant current source 39. Subsequently, the power supply control circuit 31 resumes the supply of the power supply voltage VDD to the power supply line 33. When the circuit module 10 resumes operation, the internal circuit of each flip-flop FF reads data “0” corresponding to the resistance state of the MTJ element 12 and outputs it from the data output terminal Q.
Thus, a series of reset processing is completed, and thereafter, the normal operation described above is performed.

(Preset operation)
Next, an operation (preset process) for collectively setting the stored data of the flip-flops FF provided in each circuit module 10 to “1” will be described.

  Assume that a preset instruction signal is supplied from the outside, and the power supply control circuit 31 is instructed to preset the circuit module 10. Then, the power supply control circuit 31 stops the operation of supplying the power supply voltage VDD to the power supply line 33 and supplies the operation power and the preset control signal to the constant current source 39. Each constant current source 39 allows a preset current (a constant current in the direction opposite to the reset current shown in FIG. 5A) to flow through the loop-shaped portions 33a, 33b,. A preset magnetic field is generated around the power supply line 33 in the direction opposite to the magnetic field MF generated at the time of resetting, and this is applied to each MTJ element 12. As a result, the magnetization direction of the free layer 12c of each MTJ element 12 is opposite to the magnetization direction of the pinned layer 12a, resulting in a high resistance state. As a result, all flip-flops FF store data “1” and are preset.

Thereafter, the power supply control circuit 31 stops the supply of the preset control signal and the operating power to the constant current source 39 and stops the operation of the constant current source 39. Subsequently, the power supply control circuit 31 resumes the supply of the power supply voltage VDD to the power supply line 33. When the circuit module 10 resumes operation, the internal circuit of each flip-flop FF reads data “1” corresponding to the resistance state of the MTJ element 12 and outputs it from the data output terminal Q.
As described above, a series of preset processing is completed, and thereafter, the normal operation described above is performed.

  As described above, according to the LSI chip 100 according to the first embodiment, the magnetic field MF is generated around the power supply line 33 to which each circuit module 10 is connected, and the MTJ element 12 provided in each circuit module 10. Can be collectively set to a predetermined resistance state. This eliminates the need for a signal generation circuit for generating a reset signal and a preset signal, and wiring for connecting the signal generation circuit and each flip-flop FF, and the flip-flop FF (MTJ element 12) can be easily configured with a simple circuit configuration. It can be initialized.

  In the first embodiment, the internal circuit of the flip-flop FF stores the data input to the data input terminal D in the MTJ element 12 at each rising edge timing of the clock signal input to the clock terminal CLK. Although the example to perform is demonstrated, you may memorize | store the data input into the data input terminal D immediately before the power supply to the circuit module 10 is interrupted | blocked. In the first embodiment, the internal circuit of the flip-flop FF outputs the data stored in the MTJ element 12 to the data output terminal Q at every rising edge timing of the clock signal input to the clock terminal CLK ( In the example described above, the data stored in the MTJ element 12 is read only when the supply of power to the circuit module 10 is resumed, while the power to the circuit module 10 is being supplied. The data input to the data input terminal D may be output to the data output terminal Q at every rising edge timing of the clock signal input to the clock terminal CLK.

  Further, a switch is arranged between the power supply line 33 and the loop-shaped portions 33a, 33b... So that the switch is opened when the initialization current IR or the preset current flows through the loop-shaped portions 33a, 33b. It may be configured. With such a configuration, it is possible to collectively initialize (reset or preset) the flip-flops FF in the circuit module 10 with the power supply control circuit 31 applying the power supply voltage VDD to the power supply line 33. Become.

  Further, the power supply control circuit 31 may flow the initialization current IR only through a part of the loop-shaped portions 33a... To initialize only the flip-flops arranged in the vicinity of the loop-shaped portions. For example, when the flip-flop FF in the circuit module 10C shown in FIG. 1 is to be initialized, the power supply control circuit 31 does not supply an initialization control signal and operating power to the constant current source 39a. Only the initialization control signal and the operating power need be supplied to 39b. Thereby, the initialization of the flip-flop FF (MTJ element 12) can be performed for each constant current circuit (unit of circuit module 10 or block unit including a plurality of circuit modules 10).

  In the first embodiment, the aspect in which the constant current circuit is provided in a part of the power supply line 33 (the loop-shaped portions 33a and 33b) has been described. However, the constant current circuit is a ground line to which the circuit module 10 is connected. 35 may be provided in part. In this case, the initialization current IR flows through a part of the ground line 35, and the MTJ elements 12 provided in each circuit module 10 are collectively brought into a predetermined resistance state (low level) by the magnetic field generated around the ground line 35. Resistance state, high resistance state).

  The constant current circuit only needs to allow the initialization current IR to flow through the power supply line 33 or the ground line 35 to which the circuit module 10 including the MTJ element 12 to be initialized is connected. The position and quantity at which can be installed can be changed as appropriate.

  In the first embodiment, the mode in which the flip-flop FF (MTJ element 12) is disposed at a position immediately below the power supply line 33 and close to the power supply line 33 has been described. However, as illustrated in FIG. By arranging a pair of MTJ elements 12 and 14 symmetrically in the vertical direction, the MTJ elements 12 and 14 may be set in a predetermined resistance state by a magnetic field generated around the power supply line 33. Further, the flip-flop FF including the pair of MTJ elements 12 and 14 may be disposed at a position immediately below the power supply line 33 and close to the power supply line 33. In this case, the magnetization directions of the pinned layers 12a and 14a of the MTJ elements 12 and 14 are set to be the same direction. As a result, the resistance states of the pair of MTJ elements 12 and 14 are complementarily set such that one is in the high resistance state and the other is in the low resistance state. The combination of the resistance states of the pair of MTJ elements 12 and 14 is the data Corresponding to “1” or “0”. Thereby, 1-bit data can be stored in the flip-flop FF including the pair of MTJ elements 12 and 14.

  Further, as shown in FIGS. 8A and 8B, the MTJ element 12 may have the magnetization directions of the pinned layer 12a and the free layer 12c parallel to the stacking direction, and the pinned layer 12a is disposed in the uppermost layer. A top pin structure may be used. In this case, the MTJ element 12 is disposed directly beside the power supply line 33 as shown in FIG. Further, as shown in FIG. 8D, a pair of MTJ elements 12 and 14 may be arranged symmetrically in the left-right direction of the power supply line 33.

  In the above description, a part of the power supply line 33 (or the ground line 35) is formed in a loop in order to secure a current path through which an initialization current (reset current or preset current) flows. As long as a current path can be secured, the configuration itself is arbitrary.

  For example, a series circuit of a resistor and a switch may be connected between the power supply line 33 and the ground line 35, and the power supply control circuit 31 may be configured to turn on the switch at the time of initialization. When the switch is turned on, a current path of power supply control circuit 31 → power supply line 33 → resistance and switch series circuit → ground line 35 → power supply control circuit 31 is generated. If the flip-flop FF is disposed in the vicinity of the current path, the initialization of the plurality of flip-flops FF (MTJ elements 12) can be performed in parallel by the magnetic field generated by the flowing current.

(Embodiment 2)
In the first embodiment, the example in which the storage data of the flip-flop FF using the MTJ element as the storage element is collectively initialized (reset or preset) has been described. Any circuit can be used as long as it is used as a circuit. In the second embodiment, a case will be described in which a batch initialization target is a mass storage circuit including a plurality of memory cells.

  In the first embodiment, the example in which the nearby MTJ element is initialized by the magnetic field generated around the wiring through which the reset current flows is described. However, in the present embodiment, the loop-like circuit in which the initialization current flows is included in the loop circuit. An example of collectively initializing a plurality of arranged MTJ elements will be described.

  As illustrated in FIG. 9, the storage device 200 includes a plurality of memory cells 11. Each memory cell 11 includes an MTJ element 12 as a nonvolatile storage element. The memory device 200 has a function of writing data to the MTJ element 12 provided in each memory cell 11 by low current spin injection and a function of initializing the MTJ element 12 at once. The storage device 200 also includes a power supply control circuit 31, and the power supply control circuit 31 is connected to a power supply line 33 and a ground line 35 formed in a closed loop shape. A power line 33 and a ground line 35 are arranged around each memory cell 11 provided in the storage device 200.

  The storage device 200 includes a plurality of memory cells 11 arranged in a matrix (3 rows and 3 columns in FIG. 9), and word lines WL (WL1 to WL3 in FIG. 9) arranged for each row of the plurality of memory cells 11. ), A pair of bit lines BL and bit line bars / BL (BL1 to BL3, / BL1 to / BL3 in FIG. 9) arranged for each column of the plurality of memory cells 11, and a word line WL. The row decoder 21 includes a read / write circuit 22 connected to the bit line BL and the bit line bar / BL, a power supply control circuit 31, a power supply line 33, and a ground line 35.

  Each memory cell 11 includes an MTJ element 12 and an NMOSFET (N-channel metal oxide semiconductor field effect transistor) 13 that functions as a selection transistor.

  As shown in FIG. 9, the pinned layer 12a of the MTJ element 12 is connected to the bit line BL arranged in the same column. The free layer 12 c of the MTJ element 12 is connected to the drain of the NMOSFET 13 in the same memory cell 11. The source of the NMOSFET 13 is connected to the bit line bar / BL arranged in the same column. The gate of the NMOSFET 13 is connected to the word line WL arranged in the same row.

  FIG. 10 schematically shows a three-dimensional configuration of the memory cell 11. The NMOSFET 13 is formed on the semiconductor substrate 101, and the MTJ element 12, the word line WL, the bit line BL, and the bit line bar / BL are formed thereon via the insulating film 102.

  Here, the MTJ element 12 has a top pin structure, in which a free layer 12 c is disposed on the lower layer side close to the semiconductor substrate 101, and a pinned layer 12 a is disposed on the upper layer side far from the semiconductor substrate 101. The pinned layer 12a is connected to the bit line BL. The free layer 12c is connected to the drain 13D of the NMOSFET 13 through the plug 103. The source 13S of the NMOSFET 13 is connected to the bit line bar / BL via the plug 104. The gate 13G of the NMOSFET 13 is connected to the word line WL.

  The word line WL, the bit line BL, and the bit line bar / BL extend in the orthogonal direction.

  The row decoder 21 shown in FIG. 9 decodes a row address received from the outside and specifies a row (row) to be accessed. The row decoder 21 outputs a selection level selection signal to the word line WL of the specified row. For example, the row decoder 21 activates the word line WL by outputting a high level selection signal to the word line WL.

  When reading data, the read / write circuit 22 decodes a column address received from the outside and identifies a column to be read. The read / write circuit 22 applies a predetermined read voltage between the bit line BL and the bit line bar / BL of the specified column. The read / write circuit 22 compares the current flowing between the bit line BL and the bit line bar / BL with a reference value, and determines whether the MTJ element 12 is in a high resistance state or a low resistance state. Then, the data stored in the MTJ element 12 is read. On the other hand, when writing data, the read / write circuit 22 decodes a column address received from the outside, and identifies a column to be written. The read / write circuit 22 applies a voltage corresponding to write data between the bit line BL and the bit line bar / BL of the specified column. At this time, forward current or reverse current flows through the MTJ element 12 of the memory cell 11 to be written, and data is written by setting the magnetization direction of the free layer 12c.

  The power control circuit 31 is connected to a power line 33 and a ground line 35 formed in a closed loop shape. The power supply control circuit 31 normally applies the power supply voltage VDD to the power supply line 33 and applies the ground voltage Vss to the ground line 35. As a result, power for operation is supplied to each unit (including the row decoder 21 and the read / write circuit 22) in the storage device 200. On the other hand, when an initialization signal is supplied from the outside, the power supply control circuit 31 supplies an initialization current IR (constant current) to at least one of the power supply line 33 or the ground line 35 to generate an initialization magnetic field MF. . As a result, a uniform magnetic field MF is applied to all the memory cells 11 of the storage device 200, and the magnetization directions of the free layers 12c of the MTJ elements 12 provided in the memory cells 11 are all aligned (magnetized). ) Thereby, the data memorize | stored in the memory | storage device 200 can be initialized collectively.

  Specifically, as shown in FIG. 11, the power supply control circuit 31 includes a control unit 37 and a constant current source 39. When receiving the initialization signal from the outside, the control unit 37 connects the constant current source 39 to the power supply line 33 and causes the initialization current IR to flow from the constant current source 39 to the closed loop power supply line 33. When the initialization current IR flows through the power supply line 33, a magnetic field MF is generated around the power supply line 33 in the direction indicated by the arrow in accordance with the right-hand rule. Thereby, the magnetic field MF is applied to each memory cell 11 surrounded by the power supply line 33, and the magnetization of the free layer 12c of each MTJ element 12 changes in the direction opposite to the direction of the magnetic field. There are two types of initialization signals: a reset signal for resetting data stored in the MTJ element 12 (set to “0”) and a preset signal for presetting (setting “1”). The power supply control circuit 31 sets the direction of the initialization current IR that flows through the power supply line 33 according to the type of the initialization signal received from the outside. When the power supply control circuit 31 receives a reset signal and when the power supply control circuit 31 receives a preset signal, a reverse initialization current IR flows through the power supply line 33 and a reverse magnetic field around the power supply line 33. Will occur.

  The MTJ element 12 provided in each memory cell 11 is arranged so as to be in a predetermined resistance state according to the magnetic field MF generated in the power supply line 33. That is, the magnetization of the pinned layer 12a of the MTJ element 12 is arranged to be parallel to the magnetization direction of the free layer 12c at the time of resetting and to be antiparallel to the magnetization direction of the free layer 12c at the time of presetting. As a result, the MTJ element 12 enters a low resistance state when an initialization current IR (reset current) for resetting flows through the power supply line 33, and the initialization current IR (preset current) for presetting is set to the power supply line 33. When it flows into the high resistance state.

  Note that the magnitude of the initialization current IR and the period during which the initialization current IR flows are values necessary for the magnetization of the free layer 12c to be in a predetermined resistance state by the magnetic field MF generated around the power supply line 33 (above a threshold value). ) Is set. Further, in order to bring the magnetization of the free layer 12c into a predetermined resistance state, an initialization current IR of milliampere order is passed through the power supply line 33. The power supply control circuit 31 may flow the initialization current IR through the ground line 35 instead of the power supply line 33, or may flow the initialization current IR through both the power supply line 33 and the ground line 35. In addition, the power supply control circuit 31 may flow the initialization current IR to a dedicated line other than the power supply line 33 and the ground line 35. In this case as well, a current in the order of milliamperes is passed through the dedicated line.

  Next, the operation of the storage device 200 having the above configuration will be described.

(Data read operation)
First, a process for reading data stored in the memory cell 11 will be described.
In this operating state, the power supply control circuit 31 applies the power supply voltage VDD to the power supply line 33 and applies the ground voltage Vss to the ground line 35. The power supply control circuit 31 supplies operating power to a circuit group including the row decoder 21 and the read / write circuit 22 via the power supply line 33 and the ground line 35.

  A row address is supplied to the row decoder 21 and a column address is supplied to the read / write circuit 22.

  The row decoder 21 activates the word line WL by outputting a high level selection signal to the word line WL specified by decoding the row address. The NMOSFET 13 connected to the activated word line WL is turned on. On the other hand, the read / write circuit 22 decodes the column address and applies a predetermined read voltage between the bit line BL and the bit line bar / BL of the column designated by the column address.

  A current having a magnitude corresponding to the resistance value of the MTJ element 12 flows between the bit line BL and the bit line bar / BL via the ON-state NMOSFET 13. The read / write circuit 22 compares the flowing current with a reference value and specifies the resistance state (high resistance state or low resistance state) of the MTJ element 12 to read data stored in the MTJ element 12.

(Data write operation)
Next, a process for writing data to the memory cell 11 will be described.
In this operating state, the power supply control circuit 31 applies the power supply voltage VDD to the power supply line 33 and applies the ground voltage Vss to the ground line 35. The power supply control circuit 31 supplies operating power to a circuit group including the row decoder 21 and the read / write circuit 22 via the power supply line 33 and the ground line 35.

  A row address is supplied to the row decoder 21, and a column address and data to be written are supplied to the read / write circuit 22.

  The row decoder 21 decodes the row address and activates the designated word line WL (high level). The NMOSFET 13 connected to the activated word line WL is turned on. On the other hand, the read / write circuit 22 decodes the column address and applies a voltage corresponding to the write data between the bit line BL and the bit line bar / BL of the column designated by the column address. For example, when writing data “1”, the read / write circuit 22 applies the power supply voltage VDD to the bit line BL and the ground voltage Vss to the bit line bar / BL. When writing data “0”, the read / write circuit 22 applies the ground voltage Vss to the bit line BL and the power supply voltage VDD to the bit line bar / BL.

  At this time, a current flows through the MTJ element 12 via the ON-state NMOSFET 13, and a high resistance state (anti-parallel state) or a low resistance state (parallel) due to a potential difference between the bit line BL and the bit line bar / BL. Status). That is, data is written to the MTJ element 12.

(At initialization)
A process (initialization) in which data stored in the storage device 200 is collectively erased and predetermined data (for example, data “0”) is written will be described. When the control unit 37 of the power supply control circuit 31 receives an initialization signal from the outside, it sends an initialization current IR having a preset magnitude from the constant current source 39 to the power supply line 33 for a preset period. .

  As shown in FIG. 11A, when an initialization current IR flows through the power supply line 33, a magnetic field MF is generated around the power supply line 33, and the closed loop formed by the power supply line 33 has a right-handed screw law. A magnetic field MF is generated in the direction indicated by the arrow. As a result, a magnetic field MF is generated over the entire circumference of the power supply line 33, a substantially uniform magnetic field MF is generated in the closed loop of the power supply line 33, and the magnetic field MF is applied to each MTJ element 12. The direction of the magnetic field MF is opposite to the magnetization direction of the pinned layer 12a of the MTJ element 12, and has a magnitude equal to or larger than a threshold that can change the magnetization direction of the free layer 12c. As a result, the magnetization direction of the free layer 12c of the MTJ element 12 is the same as the magnetization direction of the pinned layer 12a as shown in FIG. On the other hand, the pinned layer 12a is not affected by the magnetic field MF, and the magnetization direction does not change. Therefore, each MTJ element 12 is in a parallel state (low resistance state), and data “0” is written. That is, the data “0” is collectively written to the plurality of MTJ elements 12 by the magnetic field MF, and can be set to the reset state.

  The data stored in each MTJ element 12 can be collectively set to the reset state even when the initialization current IR is passed through the ground line 35. The current stored in each MTJ element 12 provided in the storage device 200 is collectively “1” by causing a current in the direction opposite to the initialization current IR to flow through the power supply line 33 or the ground line 35. Preset processing may be performed.

  As described above, according to the storage device 200 according to the second embodiment, when it is not necessary to supply power to the memory cell 11 or the like, the power supply line used for supplying power to the memory cell 11 or the like. 33 or the ground line 35 can generate a magnetic field, and the MTJ elements 12 provided in the storage device 200 can be collectively set to a predetermined resistance state. Thus, the MTJ element 12 provided in the storage device 200 can be easily initialized with a simple circuit configuration.

  Note that the power supply control circuit 31 generates a magnetic field around the power supply line 33 or the ground line 35 and supplies the MTJ element 12 included in the storage device 200 even when power is supplied to the memory cell 11 or the like. A predetermined resistance state may be set collectively and initialized.

  For initialization of the flip-flop FF shown in the first embodiment, the method shown in the second embodiment may be adopted. Further, the method shown in the first embodiment may be adopted for the initialization of the mass storage circuit shown in the second embodiment.

(Embodiment 3)
In the second embodiment, the memory cell 11 is composed of one MTJ element 12 and one select transistor (NMOSFET) 13, but the configuration of the memory cell is arbitrary. In the third embodiment, an example in which a memory cell 111 including a pair of MTJ elements 112 and 114 is initialized as illustrated in FIG. 12 will be described. The memory cell 111 includes a pair of MTJ elements 112 and 114, a pair of selection transistors NMOSFETs 113 and 115, and NMOSFETs 116 and 117 that are cross-coupled to form an inverter.

  The MTJ elements 112 and 114 are complementarily set so that one is in a high resistance state and the other is in a low resistance state. Depending on the combination of the resistance states of the MTJ elements 112 and 114, data “1” or “0” is set. It is associated. For example, the combination of the MTJ element 112 in the high resistance state and the MTJ element 114 in the low resistance state is associated with data “1”, and the combination of the MTJ element 112 in the low resistance state and the MTJ element 114 in the high resistance state Is associated with data “0”. Thereby, the memory cell 111 can store 1-bit data by the pair of MTJ elements 112 and 114.

  The pin layers 112a and 114a of the MTJ elements 112 and 114 are connected to the virtual power supply line VVDDL because the memory cell 111 is subjected to power gating control. The free layer 112 c of the MTJ element 112 is connected to the bit line BL via the source / drain path of the selection transistor 113. The free layer 114c of the MTJ element 114 is connected to the bit line bar / BL via the source / drain path of the NMOSFET 115.

  The NMOSFETs 116 and 117 are cross-coupled to amplify the voltages at the connection nodes SN and / SN with the MTJ elements 112 and 114.

  Note that the configuration is the same as that of the storage device 200 shown in FIG. 9 except for the configuration of the memory cell 111 and the configuration for performing power gating control.

  The MTJ elements 112 and 114 are arranged as shown in FIG. 13A, and their resistance states are set complementarily such that one is in a high resistance state and the other is in a low resistance state during initialization. The MTJ elements 112 and 114 have a top pin structure, and the magnetization directions of the pinned layers 112a and 114a are opposite to each other. In this configuration, when the initialization current IR for resetting the MTJ elements 112 and 114 is supplied to the power supply line 33 and / or the ground line 35 to generate the magnetic field MF, as shown in FIG. The magnetization directions of 112c and 114c are aligned (magnetized) in the same direction. As a result, the MTJ element 112 is in a low resistance state, the MTJ element 114 is in a high resistance state (data “0”), and the memory cell 111 is reset (initialized).

  As described above, according to the memory device according to the third embodiment, the pair of MTJ elements 112 and 114 can be collectively set to complementary resistance states with a simple configuration and processing, and the memory cell 111 can be initialized.

  When an initialization current IR for presetting (a constant current in a direction opposite to that at the time of resetting) is passed, the MTJ element 112 is in a high resistance state and the MTJ element 114 is in a low resistance state (data “1”). The memory cell 111 is preset.

  Further, the MTJ elements 112 and 114 may be configured such that the magnetization directions of the pinned layers 112a and 114a and the free layers 112c and 114c may be perpendicular to the stacking direction, or have a bottom pin structure in which the pinned layers 112a and 114a are arranged in the lowest layer. Also good.

  Further, the flip-flop FF shown in the first embodiment may be provided with a pair of MTJ elements, and the flip-flop FF may be initialized by adopting the method shown in the third embodiment. Further, the method shown in the first embodiment may be adopted for the initialization of the mass storage circuit shown in the third embodiment.

(Embodiment 4)
In the third embodiment, the magnetization directions of the pin layers 112a and 114a of the pair of MTJ elements 112 and 114 are set in reverse directions in advance, and the resistance states of the MTJ elements 112 and 114 are set in a complementary manner. It can also be performed by the method. In the fourth embodiment, an example will be described in which the resistance states of the pair of MTJ elements 112 and 114 are complementarily set when the free layers 112c and 114c having different thresholds for reversing the magnetization direction are provided.

  As shown in FIG. 14A, the magnetization directions of the pinned layers 112a and 114a of the MTJ elements 112 and 114 are the same direction.

  Also, the magnetic field strength (referred to as Fth112) that must be applied to reverse the magnetization direction of the free layer 112c of the MTJ element 112 is applied to reverse the magnetization direction of the free layer 114c of the MTJ element 114. It is larger than the intensity of the magnetic field that must be (referred to as Fth114). That is, Fth112> Fth114.

  In addition, when a magnetic field MF having a predetermined strength is applied to the MTJ elements 112 and 114, a threshold of time (referred to as Tth112) that must be continuously applied in order to reverse the magnetization direction of the free layer 112c of the MTJ element 112. Is larger than a threshold of time (referred to as Tth114) that must be applied to reverse the magnetization direction of the free layer 114c of the MTJ element 114. That is, Tth112> Tth114.

  In such a configuration, the constant current source 39 supplies a relatively large initialization current IR1 under the control of the control unit 37. As a result, as shown in FIG. 14B, a relatively large magnetic field MF1 is generated and applied to the MTJ elements 112 and 114 in the downward direction (first direction) for a relatively long time T1. Thereby, the magnetization directions of the free layer 112c of the MTJ element 112 and the free layer 114c of the MTJ element 114 are aligned (magnetized) in the same direction. As a result, the MTJ elements 112 and 114 both have the same resistance state (the low resistance state in FIG. 14B).

  Subsequently, under the control of the control unit 37, the constant current source 39 allows a current smaller than the initialization current IR1 to flow as the initialization current IR2 in the direction opposite to the initialization current IR1. As a result, as shown in FIG. 14C, a magnetic field MF2 is generated and applied to the MTJ elements 112 and 114 in the upward direction (opposite direction to the first direction) for a time T2.

  Here, the magnetic field MF2 and the time T2 are set to values that change the magnetization direction of the free layer 114c of the MTJ element 114 but do not change the magnetization direction of the free layer 112c of the MTJ element 112. For example, the strength F2 of the initialization magnetic field MF2 is set to Fth112> F2> Fth114, and the application time T2 of the initialization magnetic field MF2 is set to Tth112> T2> Tth114. Thereby, each resistance state can be complementarily set such that the MTJ element 112 is in a low resistance state and the MTJ element 114 is in a high resistance state.

  As described above, according to the storage device 200 according to the fourth embodiment, the pair of MTJ elements 112 and 114 includes the free layers 112c and 114c having different thresholds for reversing the magnetization direction, and the direction and strength of the initialization current. By controlling this, the MTJ elements 112 and 114 can be set to complementary resistance states.

  Further, the flip-flop FF shown in the first embodiment may be provided with a pair of MTJ elements, and the flip-flop FF may be initialized by adopting the technique shown in the fourth embodiment.

(Embodiment 5)
In the second to fourth embodiments, all memory cells provided in the storage device 200 are targeted for initialization, but some memory cells may be targeted for initialization. For example, in the memory device 200 shown in FIG. 9, the memory cells 11 arranged in the first row and the second row are targeted for initialization, and the memory cells 11 arranged in the third row are excluded from the objects for initialization. You may do it.

  In this case, for example, as shown in FIG. 15, a dedicated loop circuit 41 is installed so as to surround only the memory cells 11 arranged in the first row and the second row, and the power supply control circuit 31 is connected to the loop circuit 41. An initialization current IR is supplied.

  The memory cells 11 in the first row and the second row surrounded by the loop circuit 41 are applied with the magnetic field MF in the first direction (the direction from the drawing to the back) generated by the initialization current IR. Cell 11 is initialized. On the other hand, the memory cells 11 in the third row located outside (not surrounded by) the loop circuit 41 are in the direction opposite to the first direction (the direction from the back to the front) due to the initialization current IR. A magnetic field is applied. Therefore, it is desirable to configure the memory cell 11 (or MTJ element 12) or to dispose the MTJ element 12 away from the loop circuit 41 so as not to be affected by the magnetic field in the reverse direction. Further, the MTJ elements 12 of the memory cells 11 in the third row may be arranged so as to be initialized by the magnetic field in the reverse direction.

(Embodiment 6)
In the fifth embodiment, the loop circuit 41 dedicated to initialization is arranged. However, other circuits used for normal operation can be used for initialization.

  For example, in the configuration of FIG. 16, the tips of the word line WL, the bit line BL, and the bit line bar / BL are connected to the ground line 35 via the NMOSFET 42.

  The power supply control circuit 31 controls the voltage applied to the gates of these NMOSFETs via a control line (not shown), and individually controls on / off of these NMOSFETs 42. In the normal operation, the power supply control circuit 31 turns off all the NMOSFETs 42 so as not to affect the read / write operation. On the other hand, when initializing the memory cell 11, the power supply control circuit 31 loops with the word line WL, the bit line BL, the bit line bar / BL, and the ground line 35 so as to include the memory cell 11 to be initialized. NMOSFET 42 is selected and turned on to form a circuit (not necessarily closed loop). For example, when it is desired to initialize only the memory cell 11 in the third column, the bit line BL3 and the ground line 35 are connected so as to form a loop with the bit line BL3, the ground line 35, and the bit line bar / BL3. The NMOSFET 42 and the NMOSFET 42 that connects the bit line bar / BL3 and the ground line 35 are turned on, and the other NMOSFETs 42 are kept off.

  Subsequently, the power supply control circuit 31 instructs the read / write circuit 22 to pass the initialization current IR between the bit line BL3 and the bit line bar / BL3. Here, each of the row decoder 21 and the read / write circuit 22 includes a constant current source for initialization, and the read / write circuit 22 follows the instruction from the bit line BL3 → the ground line 35 → the bit line bar. By applying a constant current through the route / BL3, the initialization magnetic field MF is applied to the memory cells 11 in the third column, and these are initialized. According to such a configuration, it is possible to initialize the memory cell 11 (MTJ element 12) to be initialized using a circuit for normal operation.

  Note that a switching circuit such as an NMOSFET may be disposed at an intersection of the word line WL, the bit line BL, and the bit line bar / BL, and these lines may be appropriately connected to form a loop circuit.

(Embodiment 7)
In the second to sixth embodiments, an example in which a loop circuit for flowing an initialization current is configured and the memory cells in the loop are initialized collectively has been described. It is also possible to initialize only the memory cells in the vicinity of. Hereinafter, an initialization method having such a configuration will be described.

  In the memory device 200 shown in FIG. 9, only the memory cells 11 in the first row and the second row are desired for batch initialization, and the memory cells 11 in the third row are not subject to initialization. Suppose there is. In this case, as shown in FIG. 17, an initialization wiring 43 is provided in the vicinity of the MTJ elements 12 of the memory cells 11 in the first row and the second row, and an initial wiring is supplied to the wiring 43 from the power supply control circuit 31. The activation current IR may flow.

  In this case, as schematically shown in FIG. 18, a magnetic field MF generated by the initialization current IR flowing through the wiring 43 is applied to the MTJ element 12 in the vicinity of the wiring 43. Therefore, the direction and magnitude of the initialization current IR and the application time may be adjusted by the magnetic field MF so that the magnetization direction of the free layer 12c of the MTJ element 12 is in a desired direction.

  According to such a configuration, the plurality of memory cells 11 can be initialized collectively with a relatively small initialization current IR. It is also possible to initialize only some of the memory cells 11.

  As for the memory cell 111 including the pair of MTJ elements 112 and 114 shown in FIG. 12, an initialization wiring 43 is arranged between the MTJ element 112 and the MTJ element 114 as shown in FIG. By passing the initialization current IR through the wiring 43, the MTJ elements 112 and 114 can be set to complementary resistance states and initialized.

  In addition, for a memory cell using two or more MTJ elements, each MTJ element can be initialized with the same specifications.

  In the above description, the magnetization direction of the pinned layer and the free layer of the MTJ element is exemplified as the direction parallel to the stacking direction of the three layers constituting the MTJ element. However, as shown in FIG. Direction may be used. Also in this case, the MTJ elements 112 and 114 can be initialized by passing the initialization current IR through the wiring 43 only by adjusting the arrangement of the initialization wiring 43 and the MTJ elements 112 and 114.

(Embodiment 8)
In the seventh embodiment, the initialization wiring 43 is arranged. However, the word line WL, the bit line BL, the bit line bar / BL, or the like may be used as the wiring 43. In this case, for example, the positional relationship between the word line WL, bit line BL, bit line bar / BL used as initialization wiring and the MTJ element of each memory cell is shown in FIGS. It forms so that it may become a positional relationship.

  In addition, as shown in FIG. 16, the tips of the word line WL, bit line BL, and bit line bar / BL are connected to the ground line 35 via the NMOSFET, and a current can flow through these lines. And

  In the normal operation, the power supply control circuit 31 turns off all the NMOSFETs 42 so as not to affect the read / write operation. On the other hand, when initializing the memory cell 11, the power supply control circuit 31 turns on the NMOSFET 42 connected to the tips of the word line WL, the bit line BL, and the bit line bar / BL through which the initialization current IR flows. To do.

  Subsequently, the power supply control circuit 31 controls the row decoder 21 and the read / write circuit 22 to flow the initialization current IR to each selected line. Thereby, as shown in FIGS. 18 to 20, the magnetic field MF is generated, and the MTJ elements arranged in the vicinity of each line are initialized. According to such a configuration, the memory cell can be initialized using a circuit for normal operation.

  As described above, according to the present invention, the MTJ element when the writing method is current writing can be easily initialized with a simple circuit configuration. In addition, this invention is not limited to each embodiment, A various deformation | transformation and application are possible. For example, the configuration of the memory circuit is not limited to each embodiment, and is arbitrary as long as the MTJ element is provided.

  Further, the circuit configuration, circuit arrangement, and the like can be changed as appropriate. For example, as the selection transistor or the switching element, a PMOSFET can be used instead of the NMOSFET, or another switching element can be used. In addition, in order to facilitate understanding, the constant current has been described as the initialization current IR. However, the initialization current IR may vary in time.

10, 10A, 10B, 10C Circuit module 11 Memory cell 12, 14 MTJ element 12a, 14a Pin layer 12b, 14b Insulating layer 12c, 14c Free layer 13 NMOSFET
13D drain (NMOSFET)
13S source (NMOSFET)
13G gate (NMOSFET)
15 Logic Gate 21 Row Decoder 22 Read / Write Circuit 31 Power Supply Control Circuit 33 Power Supply Line 33a, 33b Loop Part (Part of Power Supply Line)
35 Ground line 36a, 36b Switch 37 Control unit 39 Constant current source 40 Clock generation circuit 41 Loop circuit 42 NMOSFET
43 Wiring 100 LSI chip (memory device)
200 Memory device 101 Semiconductor substrate 102 Insulating film 103, 104 Plug 111 Memory cell 112, 114 MTJ element 112a, 114a Pin layer 112b, 114b Insulating layer 112c, 114c Free layer 113, 115, 116, 117 NMOSFET
FF flip-flop D data input terminal Q data output terminal CLK clock terminal WL, WL1, WL2, WL3 word line BL, BL1, BL2, BL3 bit line / BL, / BL1, / BL2, / BL3 bit line bar IR, IR1, IR2 Initialization current (constant current)

Claims (8)

A plurality of storage elements each comprising a pair of magnetic tunnel junction elements;
Writing means for individually writing data to the plurality of storage elements;
Magnetic field writing means for writing common data by applying a magnetic field to the plurality of storage elements,
The magnetic tunnel junction element includes a first layer in which the magnetization direction is fixed and a second layer in which the magnetization direction is not fixed, and the magnetization direction of the first layer and the second layer When the magnetization directions are parallel to each other, the resistance is low, and when the magnetization directions are antiparallel, the resistance is high.
The pair of magnetic tunnel junction elements constituting each storage element has either one of the magnetic tunnel junction elements in which the magnetization direction of the first layer and the magnetization direction of the second layer are parallel to each other. The direction of magnetization of the first layer and the direction of magnetization of the second layer of the other magnetic tunnel junction element are set to be complementary to each other,
The magnetic field writing means includes a current line through which a current flows.
Of the pair of magnetic tunnel junction elements constituting each storage element, the first magnetic tunnel junction element and the second magnetic tunnel junction element have the first magnetic tunnel junction element generated by one magnetic field generated by one current flowing through the current line. The direction of magnetization of the first layer of one magnetic tunnel junction element is parallel to the direction of magnetization of the second layer, and the direction of magnetization of the first layer of the second magnetic tunnel junction element is The magnetization directions of the second layer are arranged at positions that are antiparallel to each other,
A storage device. The magnetization directions of the first layer of each of the pair of magnetic tunnel junction elements are set in the same direction,
Each of the pair of magnetic tunnel junction elements is disposed at a position where the magnetization directions of the second layer are opposite to each other by a magnetic field generated by a current flowing through the current line.
The storage device according to claim 1. The direction of magnetization of the first layer of each of the pair of magnetic tunnel junction elements is set to be opposite to each other,
Each of the pair of magnetic tunnel junction elements is disposed at a position where the magnetization directions of the second layer are in the same direction by a magnetic field generated by a current flowing through the current line.
The storage device according to claim 1. A plurality of storage elements comprising a pair of magnetic tunnel junction elements;
Writing means for individually writing data to the plurality of storage elements by causing a current corresponding to the data to be written to flow through a magnetic tunnel junction element constituting the storage element to be written;
A magnetic line writing unit that includes a current line for flowing a current that generates a magnetic field, and stores common data by applying a magnetic field to the plurality of storage elements;
Each of the magnetic tunnel junction elements includes a first layer whose magnetization direction is fixed and a second layer whose magnetization direction is not fixed, and the magnetization direction of the first layer and the second layer Low resistance when the magnetization directions of the layers are parallel to each other, high resistance when the layers are antiparallel,
The pair of magnetic tunnel junction elements constituting each of the memory elements is configured such that the direction of magnetization of the first layer and the direction of magnetization of the second layer of any one of the magnetic tunnel junction elements are parallel to each other. The direction of magnetization of the first layer and the direction of magnetization of the second layer of the other magnetic tunnel junction element are set to be complementary to each other,
In the pair of magnetic tunnel junction elements constituting the memory element, the magnetization directions of the first layer and the second layer of one of the magnetic tunnel junction elements are parallel to each other due to the magnetic field generated by the magnetic field writing unit. And the magnetization directions of the first layer and the second layer of the other magnetic tunnel junction element are arranged to be antiparallel to each other.
A storage device. The current line is composed of a word line, a bit line, a bit line bar, a power line or a ground line.
The storage device according to claim 1, wherein the storage device is a storage device. A plurality of storage elements each comprising a magnetic tunnel junction element;
Writing means for individually storing data in the storage element;
A line including at least one of a power supply line and a ground line and arranged to surround a plurality of the storage elements ;
The power supply voltage or a ground voltage is applied to at least one power supply line and a ground line, or by supplying a current to the line, applies a magnetic field in the same direction in a plurality of said storage elements enclosed taken by the line A power supply control device for storing common data ;
A storage device comprising: Each of the storage elements includes a pair of magnetic tunnel junction elements,
The magnetic tunnel junction element includes a first layer whose magnetization direction is fixed and a second layer whose magnetization direction is not fixed,
When the magnetization direction of the first layer and the magnetization direction of the second layer are parallel to each other, the resistance is low, and when the magnetization direction is antiparallel, the resistance is high.
The magnetization directions of the first layers of the pair of magnetic tunnel junction elements constituting the memory element are set antiparallel to each other;
The storage device according to claim 6. The storage device includes both a power line and a ground line,
Each of the power supply line and the ground line is disposed so as to surround the plurality of storage elements,
The power supply control device causes a current to flow through at least one of a power supply line and a ground line.
The storage device according to claim 6, wherein the storage device is a storage device.

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