JP6031675B2 - Layout structure and layout method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device layout structure and layout method.

  When the threshold value of the transistor included in the integrated circuit is lowered, the power consumption of the transistor is reduced and the operation speed is increased. However, when the threshold value decreases, the leakage current between the source and drain of the transistor increases. For this reason, the static power (power consumption during rest) of the integrated circuit increases. Static power also increases with transistor miniaturization.

International Publication No. 2007/099841 Pamphlet

  An integrated circuit such as a system LSI (Large Scale Integration) temporarily stops (pauses) in response to a control signal and a block (for example, a control unit) that always operates while power is supplied to the LSI. Block (for example, each CPU included in the multi-core CPU).

  In such an integrated circuit, a power switch macro is provided between a block that temporarily stops and a power supply terminal. The power switch macro has a power switch. By turning off the power switch, power supply to a block that is in a pause (hereinafter referred to as a pause block) is temporarily stopped. Therefore, the power consumption of the inactive block is reduced.

  In order to restart the hibernation block, the power switch is turned on to restart the power supply to the hibernation block. At this time, if the current flowing through the pause block increases rapidly, a large noise is generated. Therefore, the power switch macro is provided with a power supply control circuit that controls the power switch to gradually increase the current. For this reason, the power switch macro is easy to increase in size.

  Each block forming the system LSI has a large number of cells. It is rare that all cells included in each block operate simultaneously, and in most cases, the remaining cells are idle while some cells are operating. In the method of stopping power supply for each block as described above, it is difficult to stop power supply only for a cell that is in a pause state.

  That is, there are various problems in the method of stopping the power supply to the sleep block for each block.

  In order to solve the above problem, according to one aspect of the present structure, the cell ground line disposed at one end, the cell power line disposed at the other end, the cell ground line, and the cell power line are connected. A first ground line, a second ground line parallel to the first ground line, the first ground line, and the second ground. A first power line disposed between the lines, a third ground line disposed on an extension of the first ground line, and a fourth ground line disposed on an extension of the second ground line And a plurality of unit cells arranged to form a second power line disposed between the third ground line and the fourth ground line on an extension of the first power line, A fifth ground line and a first power line arranged on a line connecting the first ground line and the third ground line; A unit cell having a third power line disposed on a line connecting the second power lines, a circuit connected to the third power line, and the fifth ground line; and the third power line. A detour power line and a control signal that share the line with the unit cell and further bypass the third power line and the sixth ground line disposed on the line connecting the second ground line and the fourth ground line A switch cell having a switch for connecting the bypass power supply line to the third power supply line, a seventh ground line for connecting the first ground line to the fifth ground line, and the first A first power isolation cell having an eighth ground line connecting two ground lines to the sixth ground line and a fourth power line connecting the first power line to the bypass power line; A ninth ground line and the fourth ground line connecting the third ground line to the fifth ground line are connected to the sixth ground line. There is provided a layout structure of a semiconductor device having a second power supply isolation cell having a tenth ground line connected to a ground line and a fifth power supply line connecting the second power supply line to the bypass power supply line. The

  According to the disclosed layout structure, the power supply of the semiconductor device can be controlled for each cell.

3 is an example of a floor plan of a semiconductor device having the layout structure of the first embodiment. FIG. 2 is a plan view of the layout structure of the first embodiment. FIG. 3 is a configuration diagram of a layout apparatus that executes the layout method according to the first embodiment. FIG. 4 shows an example of a layout structure formed by the arranged cell patterns. FIG. 5 is a diagram illustrating a metal layer (first layer) of the obtained unit cell. FIG. 6 is a floor plan of a semiconductor device that controls power supply for each block. FIG. 7 shows a layout structure of a semiconductor device that controls power supply for each block. FIG. 8 is an example of a cell pattern of unit cells. FIG. 9 is an example of a cell pattern of switch cells. FIG. 10 is a circuit diagram of the switch cell. FIG. 11 is an example of a cell pattern of the first power source separation cell. FIG. 12 is an example of a cell pattern of the second power source separation cell. FIG. 13 is a plan view of the layout structure of the second embodiment. FIG. 14 is a diagram showing a cross section in the vicinity of the detour power supply line among the cross sections along the XIV-XIV line in FIG. 13. FIG. 15 is an example of a cell pattern of switch cells. FIG. 16 is an example of a cell pattern of switch cells. FIG. 17 is an example of a cell pattern of the first power source separation cell. FIG. 18 is an example of a cell pattern of the first power source separation cell. FIG. 19 is a plan view of the layout structure of the third embodiment. FIG. 20 is a cross-sectional view of the vicinity of the wiring. FIG. 21 is a diagram for explaining the back gate potential of the transistor formed in the first n-type well. FIG. 22 is a cross-sectional view of the vicinity of the third power supply line in the first embodiment. FIG. 23 is a diagram for explaining the back gate potential of the transistor formed in the n-well of the first embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. In addition, the same code | symbol is attached | subjected to the corresponding part even if drawings differ, The description is abbreviate | omitted.

(Embodiment 1)
(1) Structure FIG. 1 is an example of a floor plan of a semiconductor device 4 including the layout structure 2a of the first embodiment. FIG. 2 is a plan view of the layout structure 2a of the first embodiment.

  As shown in FIG. 1, the layout structure 2a is included in, for example, a block 6 where the power is not turned ON / OFF. Although the semiconductor device 4 of FIG. 1 includes one block 6, the semiconductor device 4 may include a plurality of blocks. The layout structure 2a may be included in a block where the power is turned on / off.

  As shown in FIG. 2, the layout structure 2a includes a plurality of unit cells 8 (hereinafter referred to as normal cells) and another unit cell 10 (hereinafter referred to as power gating cell). The layout structure 2 a further includes a switch cell 12, a first power supply isolation cell 14, and a second power supply isolation cell 16. In FIG. 2, the cell frame (outer edge of the cell on the semiconductor substrate) 15 of each cell is indicated by a broken line.

  As shown in FIG. 2, each of the normal cells 8 is connected to a cell ground line 18 disposed at one end, a cell power line 20 disposed at the other end, and a cell ground line 18 and the cell power line 20. And a basic circuit 22. The basic circuit 22 is, for example, a buffer circuit, a flip-flop circuit, an inverter circuit, a NAND circuit, an AND circuit, an OR circuit, an XOR circuit, or the like. The normal cell 8 is supplied with power by the cell power line 20 and the cell ground line 18.

  A part 8a of the plurality of normal cells 8 has a first ground line 24a, a second ground line 24b, and a first power line 26a formed by the cell ground line 18 and the cell power line 20 respectively. Is arranged.

  The second ground line 24b is a ground line extending along the first ground line 24a. Specifically, for example, the second ground line 24b is a ground line parallel to the first ground line. The first power supply line 26a is a power supply line arranged between the first ground line 24a and the second ground line 24b.

  In the remaining 8b of the plurality of normal cells 8, the third ground line 24c, the fourth ground line 24d, and the second power line 26b are formed by the cell ground line 18 and the cell power line 20 respectively. Has been placed.

  The third ground line 24c is a ground line disposed on an extension line of the first ground line 24a. The fourth ground line 24d is a ground line arranged on an extension line of the second ground line 24b. The second power supply line 26b is a power supply line disposed between the third ground line 24c and the fourth ground line 24d on the extension line of the first power supply line 26a.

  The power gating cell 10 includes a fifth ground line 24e, a third power line 26c, and a basic circuit 22 (buffer circuit, flip-flop circuit, inverter circuit, NAND circuit, AND circuit, OR circuit, XOR circuit). Etc.).

  The fifth ground line 24e is a ground line arranged on a line connecting the first ground line 24a and the third ground line 24c. The third power supply line 26c is a power supply line arranged on a line connecting the first power supply line 26a and the second power supply line 26b. The circuit 22 of the power gating cell 10 is connected to the third power line 26c and the fifth ground line 24e, and is supplied with power.

  The switch cell 12 includes a sixth ground line 24 f, a bypass power supply line 30, and a switch 28. The switch cell 12 further shares the third power supply line 26 c with the power gating cell 10.

  The sixth ground line 24f is a ground line arranged on a line connecting the second ground line 24b and the fourth ground line 24d. The bypass power supply line 30 is a power supply line that is disposed between the third power supply line 26c and the sixth grounding line 24f and extends along the third power supply line 26c to bypass the third power supply line 26c.

  The switch 28 is a power switch that (electrically) connects the bypass power supply line 30 to the third power supply line 26 c in response to a control signal generated by a control unit (not shown) included in the semiconductor device 4. . The switch cell 12 is, for example, a p-channel MOS-FET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the bypass power supply line 30, a drain connected to the third power supply line 26c, and a gate supplied with a control signal. is there.

  The first power source separation cell 14 includes a seventh ground line 24g, an eighth ground line 24h, and a fourth power line 26d.

  The seventh ground line 24g is a ground line that connects the first ground line 24a to the fifth ground line 24e. The eighth ground line 24h is a ground line that connects the second ground line 24b to the sixth ground line 24f. The fourth power supply line 26 d is a power supply line that connects the first power supply line 26 a to the bypass power supply line 30.

  The second power supply separation cell 16 includes a ninth ground line 24i, a tenth ground line 24j, and a fifth power line 26e.

  The ninth ground line 24i is a ground line that connects the third ground line 24c to the fifth ground line 24e. The tenth ground line 24j is a ground line that connects the fourth ground line 24d to the sixth ground line 24f. The fifth power supply line 26 e is a power supply line that connects the second power supply line 26 b to the bypass power supply line 30. The first to tenth ground lines 24a to 24j, the first to fifth power supply lines 26a to 26e, and the bypass power supply line 30 are conductive wirings and are formed in a common interlayer insulating film.

(2) Layout method-Layout device-
FIG. 3 is a configuration diagram of the layout apparatus 32 that executes the layout method of the first embodiment. The layout device 32 in FIG. 3 is, for example, a computer.

  The layout device 32 generates a photomask pattern (hereinafter referred to as a mask pattern) corresponding to the semiconductor device 4 of FIG.

  The layout device 32 includes, for example, a central processing unit (CPU) 34, a read only memory (ROM) 36, a random access memory (RAM) 38, and a hard disk drive (HDD) 40 having a hard disk. The layout device 32 further includes a bus 42, an input device 44, and a display device 46.

  The input device 44 is a device that takes in data from the outside. The output device 46 is a device that outputs data to the outside.

  The CPU 34 controls the HDD 40, loads a program recorded in the HDD 40 into the RAM 38, and executes the loaded program. That is, the HDD 40 is a computer-readable recording medium.

  In the ROM 36, basic programs executed by the CPU 34 are recorded. In addition to the program, the RAM 38 temporarily stores midway data when the CPU 34 executes the program.

  In the HDD 40, a cell library 48, a netlist 50, and a placement and routing program (P & R (Place and Route) tool) 52 are recorded. The netlist 50 is connection information of cells and macrocells that form the semiconductor device 4. The placement and routing program 52 is a program that causes the CPU 46 to execute placement and routing processing based on the net list 50.

  In the cell library 48, cell patterns arranged and routed by the CPU 46 are registered. The cell library 48 has at least cell patterns corresponding to a plurality of unit cells (the normal cell 8 and the power gating cell 10), the switch cell 12, the first power source separation cell 14, and the second power source separation cell 16. It is registered.

  Unit cells registered in the cell library 48 are, for example, a buffer circuit, a flip-flop circuit, an inverter circuit, a NAND circuit, an AND circuit, an OR circuit, an XOR circuit, and the like. Macro cells may be registered in the cell library 48.

  Specifically, in the cell library 48, data of each of a plurality of cell patterns is recorded in a GDS II (Graphic Design System II) format or an OASIS (Open Artwork System Interchange Standard) format.

  That is, for each cell pattern, data (for example, a record) having graphic information representing basic graphics included in each layer of the cell pattern and identification information of the layer is recorded in the cell library 48. The layer is a photomask pattern and is also called a “layer”.

  The graphic information representing the polygon is, for example, vertex coordinates. The graphic information representing the path connecting the two points is, for example, the coordinates (start point coordinates and end point coordinates) of the center line of the path and the width of the path.

  The CPU 34 accesses the cell library 48 to acquire a cell pattern corresponding to the unit cell and arranges each layer of the acquired cell pattern on the arrangement plane.

  FIG. 4 shows an example of a layout structure formed by the arranged cell patterns. The solid line in FIG. 4 shows the structure of the metal layer. A broken line indicates a portion (for example, the circuit 22) or the cell frame 15 corresponding to another layer.

-Acquisition of the first cell pattern (normal cell)-
The CPU 34 accesses the cell library 48 and acquires a first cell pattern corresponding to a plurality of unit cells. The first cell pattern is a pattern corresponding to the normal cell 8 described with reference to FIG.

  As shown in FIG. 4, each of the normal cells 8 has a predetermined height, a cell ground line 18 disposed at one end, a cell power line 20 disposed at the other end, a cell ground line 18 and a cell power line 20. Connected circuit 22. The cell ground line 18 is hereinafter referred to as a first cell ground line. The cell power line 20 is hereinafter referred to as a first cell power line.

  FIG. 5 is a diagram showing the first metal layer (first layer) 54 a of the normal cell 8. As shown in FIG. 5, the first metal layer 54 a has a pattern 218 corresponding to the first cell ground line 18 and a pattern 220 corresponding to the first cell power line 20.

  In FIG. 5, a rectangular cell frame 15 having one end 62 and the other end 64 is indicated by a broken line. The cell height H is a distance between one end 62 and the other end 64 extending along the first cell ground line 18. The same applies to other cells.

-Acquisition of second cell pattern (power gating cell)-
The CPU 34 accesses the cell library 48 and acquires a second cell pattern corresponding to the unit cell. The second cell pattern is a pattern corresponding to the power gating cell 10 described with reference to FIG.

  As shown in FIG. 4, the power gating cell 10 includes the predetermined height H, a second cell ground line 18b disposed at one end, a second cell power line 20b disposed at the other end, And a circuit 22 connected to the second cell ground line 18b and the second cell power line 20b.

  The second cell pattern has a metal layer (a layer corresponding to the first layer 54a) including a pattern corresponding to the second cell ground line 18b and a pattern corresponding to the second power supply line 20b.

-Acquisition of third cell pattern (switch cell)-
The CPU 34 accesses the cell library 48 and acquires a third cell pattern corresponding to the switch cell 12. The third cell pattern is the switch cell 12 described with reference to FIG.

  As shown in FIG. 4, the switch cell 12 includes the predetermined height H, a third cell ground line 18c disposed at one end, a third cell power line 20c disposed at the other end, Cell detour power line 66 extending along the cell power line 20c. The switch cell 12 further includes a switch 28 that connects the cell bypass power supply line 66 to the third power supply line 20c in response to the control signal.

  In the third cell pattern, a pattern corresponding to the third cell ground line 18c, a pattern corresponding to the third cell power line 20c, and a pattern corresponding to the cell detour power line 66 are combined with the metal layer (first A layer corresponding to the layer 54a).

-Acquisition of the fourth cell pattern (first power supply isolation cell)-
The CPU 34 accesses the cell library 48 and acquires the fourth cell pattern corresponding to the first power supply separation cell 14. The fourth cell pattern is a pattern corresponding to the first power source separation cell 14 described with reference to FIG.

  As shown in FIG. 4, the first power separation cell 14 has a height twice the predetermined height H, a fourth cell ground line 18d arranged at one end, and a fifth cell arranged at the other end. Cell ground line 18e. The first power supply separation cell 14 further includes a fourth cell power supply line 20d disposed between the fourth cell ground line 18d and the fifth cell ground line 18e in plan view.

  As shown in FIG. 4, the first end 68a of the fourth cell power line 20d has a first side (left side) sandwiched between the fourth cell ground line 18d and the fifth cell ground line 18e. Located in the center. The second end 68b of the fourth cell power supply line 20d is disposed at a position corresponding to one end of the cell detour power supply line 66 in the second side (right side) facing the first side in plan view. .

  The fourth cell pattern includes a metal layer (including a pattern corresponding to the fourth cell ground line 18d, a pattern corresponding to the fifth cell ground line 18e, and a pattern corresponding to the fourth cell power line 20d). Layer corresponding to the first layer 54a).

-Acquisition of the fifth cell pattern (second power supply isolation cell)-
The CPU 34 accesses the cell library 48 and acquires the fifth cell pattern corresponding to the second power supply separation cell 16. The fifth cell pattern is a pattern corresponding to the second power source separation cell 16 described with reference to FIG.

  As shown in FIG. 4, the second power source separation cell 16 has a height twice the predetermined height H, a sixth cell ground line 18f arranged at one end, and a seventh cell arranged at the other end. Cell ground line 18g. The second power supply isolation cell 16 further includes a fifth cell power supply line 20e disposed between the sixth cell ground line 18f and the seventh ground line 18g in plan view.

  As shown in FIG. 4, the third end 68c of the fifth cell power line 20e is the center of the third side (right side) sandwiched between the sixth cell ground line 18f and the seventh cell ground line 18g. Located in. The fourth end 68d of the fifth cell power supply line 20e is arranged at a position corresponding to the other end of the cell bypass power supply line 66 in the fourth side (left side) facing the third side in plan view. The

  The fifth cell pattern includes a metal layer (including a pattern corresponding to the sixth cell ground line 18f, a pattern corresponding to the seventh cell ground line 18g, and a pattern corresponding to the fifth cell power line 20e). Layer corresponding to the first layer 54a).

-Acquisition of sixth cell pattern-
When the semiconductor device 4 includes a sixth cell pattern different from the first to fifth cell patterns, the CPU 34 obtains the sixth cell pattern. The first to sixth cell patterns may be acquired for each layer or may be acquired for each cell pattern.

-Cell pattern layout-
The CPU 34 arranges each layer (for example, metal layer) included in each acquired cell pattern so that corresponding layers (for example, metal layers) are included in a common arrangement plane.

  At this time, as shown in FIG. 4, the CPU 34 overlaps the patterns corresponding to the first cell power supply lines 20 of the plurality of normal cells 8 with each other, and the pattern corresponding to the first power supply line 26a and the second power supply line 26b. The first cell pattern is double-backed so as to form a pattern corresponding to.

  Further, the CPU 34 overlaps the pattern corresponding to the second cell power line 20b of the power gating cell 10 and the pattern corresponding to the third cell power line 20c of the switch cell 12 to correspond to the third power line 26c. The second cell pattern and the third cell pattern are arranged in a double back so as to form.

  Further, the CPU 34 has a pattern corresponding to the first to third power supply lines 26 a, 26 b and 26 c, a pattern corresponding to the fourth cell power supply line 20 d of the first power supply isolation cell 14, and the second power supply isolation cell 16. The first to fifth cell patterns are arranged so that the patterns corresponding to the fifth cell power supply line 20e are connected in a line.

―Placement of wiring pattern―
Thereafter, the CPU 34 arranges a wiring pattern (not shown) for connecting the input / output terminals of the arranged cell pattern. At this time, a wiring pattern for connecting the pattern corresponding to the control unit (not shown) of the semiconductor device 4 and the pattern of the switch cell 12 is also arranged. These wiring patterns may be arranged on an arrangement plane on which a pattern corresponding to the first cell ground line 18 is arranged, or may be arranged on another arrangement plane.

―Formation of layout structure―
The CPU 34 outputs the arranged cell pattern and wiring pattern (mask pattern) data in the GDS II format or the OASIS format. Thereby, the layout of the semiconductor device 4 is completed.

  A photomask is manufactured using the output data, and the semiconductor device 4 including the layout structure 2a is formed by the photomask.

(3) Operation The power gating cell 10 is a circuit having an idle period. For example, the power gating cell 10 is a large output buffer circuit provided on a long signal line. Alternatively, the power gating cell 10 is a high-speed circuit having a pause period.

  When the signal processing of the power gating cell 10 stops, the control unit (CPU or the like) transmits a control signal (for example, a disable signal) to the switch cell 12. Then, the switch cell 12 opens the switch 28. Thereby, the power supply to the power gating cell 10 is stopped.

  The control unit transmits another control signal (for example, an enable signal) to the switch cell 12 before the power gating cell 10 starts signal processing. Then, the switch cell 12 closes the switch 28. As a result, the power supply to the power gating cell 10 is resumed, and the power gating cell 10 becomes ready for signal processing.

  That is, according to the layout structure 2a of the first embodiment, power feeding to the power gating cell 10 is controlled for each cell.

  FIG. 6 is a floor plan of the semiconductor device 70 that controls power supply for each block.

  A semiconductor device (for example, a system LSI) 70 includes a block 72 (hereinafter referred to as a constant power supply block) that continuously operates while power is supplied to the LSI, and a block 74 (hereinafter referred to as power gating) that temporarily stops operation. (Referred to as a block).

  The semiconductor device 70 further includes a power switch macro 76 provided between the power gating block 74 and a power supply terminal (not shown). The power switch macro 76 is a circuit including a power switch.

  The constant power supply block 72 is a control unit that controls the operation of the semiconductor device 70, for example. The power gating block 74 is, for example, each CPU of a multi-core CPU (in this case, a plurality of power gating blocks 74 forming each CPU are provided. A plurality of power switch macros 76 are also provided).

  The power switch macro 76 stops power supply to the power gating block 74 that is in a rest state by turning off the power switch. As a result, the static power of the power gating block 74 is reduced.

  The power switch macro 76 turns on the power switch before the dormant power gating block 74 resumes signal processing. Then, power supply to the power gating block 74 is started, and the power gating block 74 is ready for signal processing.

  At this time, if the current flowing through the power gating block 74 increases rapidly, a large noise is generated. Therefore, the power switch macro 76 is provided with a power supply control circuit that controls the power switch to gradually increase the current. For this reason, the power switch macro 76 is easily increased in size.

  The constant power supply block 72 and the power gating block 74 are formed by a large number of cells. Although these blocks operate as a whole block, some cells may temporarily stop operating. In the method of stopping power supply for each block as described above, it is difficult to suppress power consumption by stopping only power supply to a suspended cell.

  These problems are solved by controlling the power supply for each cell.

  Since the current flowing through each cell is small, noise generated in each cell at the start of power feeding is small. Therefore, the power supply control circuit can be omitted by controlling the power supply for each cell.

  Furthermore, by controlling power feeding for each cell, it is possible to stop power feeding only to a cell that is not in operation. Therefore, it is possible to suppress the power consumption of the operating block.

  FIG. 7 shows a layout structure of the semiconductor device 70 that controls power supply for each block. As shown in FIG. 7, in the semiconductor device 70 of FIG. 6, the circuit 22 of the cell 82 is connected to the ground lines 78 and the power lines 80 that are alternately arranged. Therefore, it is difficult to control power supply for each cell 82.

  On the other hand, in the layout structure 2a of the first embodiment, the power supply line 26c of the power gating cell 10 is separated from the power supply lines 26a and 26b of the normal cell 8 by the power supply separation cells 14 and 16, as shown in FIG. . Therefore, the power supply to the power gating cell 10 can be controlled for each cell. Therefore, the above-described problem caused by controlling the power supply for each block is solved according to the first embodiment.

(4) Cell Pattern Next, specific examples of the first to fifth cell patterns are shown.

-Unit cell (first and second cell patterns)-
FIG. 8 is an example of a cell pattern of unit cells (normal cell 8 and power gating cell 10). FIG. 8 shows a cell pattern of the inverter.

FIG. 8A shows an n-well layer 84a, a p-well layer 86a, a gate layer 90a, a contact layer 92a, a first diffusion layer 88a, and a second diffusion layer 89a. . The first diffusion layer 88a corresponds to the p ⁺ diffusion region in the n well. The second diffusion layer 89a corresponds to the n ⁺ diffusion region in the p well.

  FIG. 8B shows the contact layer 92a and the first metal layer 54a. The first metal layer 54a includes a pattern 218 corresponding to the cell ground lines 18 and 18b (see FIG. 4), a pattern 220 corresponding to the cell power supply lines 20 and 20b (see FIG. 4), and a pattern 222 corresponding to the intra-cell wiring. Including.

  Each wiring pattern 218, 220, 222 in the first metal layer 54a is connected to the first diffusion layer 88a, the second diffusion layer 89a, or the gate layer 90a by the contact layer 92a.

-Switch cell (third cell pattern)-
FIG. 9 is an example of a cell pattern of the switch cell 12. The switch forming the switch cell 12 in FIG. 9 has a plurality of transistors connected in parallel.

FIG. 9A shows an n-well layer 84b, a p-well layer 86b, a gate layer 90b, a contact layer 92b, and a first diffusion layer 88b. The first diffusion layer 88b corresponds to the p ⁺ diffusion region in the n well.

  FIG. 9B shows the contact layer 92b and the first metal layer 54b (a layer corresponding to the first layer 54a). The first metal layer 54b includes a pattern 218c corresponding to the third cell ground line 18c (see FIG. 4) and a pattern 220c corresponding to the third cell power line 20c (see FIG. 4). The first metal layer 54b further includes a pattern 266 corresponding to the cell bypass power supply line 66 (see FIG. 4) and a pattern 222b corresponding to the intra-cell wiring.

  FIG. 10 is a circuit diagram of the switch cell 12. As shown in FIG. 10, the switch cell 12 includes a third cell power supply line 20c, a cell bypass power supply line 66, and a switch 28 provided between the third cell power supply line 20c and the cell bypass power supply line 66. And have. The switch 28 is, for example, a p-channel MOS-FET (Metal Oxide Semiconductor Field Effect Transistor). A cell bypass power supply line 66 is connected to the source S of the p-channel MOS-FET. A third cell power supply line 20c is connected to the drain D of the p-channel MOS-FET. A control signal for turning on / off the switch 28 is supplied to the gate G of the p-channel MOS-FET.

  Each wiring pattern 218c, 220c, 266, 222b in the first metal layer 54b is connected to the first diffusion layer 88b or the gate layer 90b by a contact layer 92b.

-1st power source separation cell (4th cell pattern)-
FIG. 11 is an example of a cell pattern of the first power source separation cell 14.

  FIG. 11A shows an n-well layer 84c and a p-well layer 86c. The height of the first power supply separation cell 14 is twice the height of each of the unit cells 8 and 10 and the switch cell 12. Therefore, n well layer 84c is connected to the n well layers of these four cells arranged on both sides of first power supply isolation cell. The same applies to the p-well layer 86c.

  FIG. 11B shows the n-well layer 84c and the p-well 86c and the first metal layer 54c (a layer corresponding to the first layer 54a). The first metal layer 54c includes a pattern 218d corresponding to the fourth cell ground line 18d, a pattern 218e corresponding to the fifth cell ground line 18e, and a pattern 220d corresponding to the fourth cell power line 20d. Have.

-Second power isolation cell (fifth cell pattern)-
FIG. 12 is an example of a cell pattern of the second power source separation cell 16.

  FIG. 12A shows an n-well layer 84d and a p-well layer 86d. The height of the second power source separation cell 16 is twice the height of the unit cells 8 and 10 and the height of the switch cell 12. Therefore, n well layer 84d is connected to the n well layers of the four cells arranged on both sides of second power supply isolation cell 16.

  FIG. 12B shows the n-well layer 84d and the first metal layer 54d (a layer corresponding to the first layer 54a). The first metal layer 54d includes a pattern 218f corresponding to the sixth cell ground line 18f, a pattern 218g corresponding to the seventh cell ground line 18g, and a pattern 220e corresponding to the fifth cell power line 20e. Have.

  The cell patterns shown in FIGS. 8 to 12 are examples, and the first to fifth cell patterns can take various forms. For example, the pattern 220d corresponding to the fourth cell power line 20d may be a pattern that obliquely crosses the cell frame. The same applies to the pattern 220e corresponding to the fifth cell power line 20e.

(Embodiment 2)
The layout structure of the second embodiment is similar to the layout structure 2a of the first embodiment. Therefore, description of parts common to the first embodiment is omitted or simplified.

(1) Structure FIG. 13 is a plan view of a layout structure 2b according to the second embodiment. FIG. 14 is a view showing a cross section in the vicinity of the bypass power supply line 30b among the cross sections along the XIV-XIV line in FIG.

  As shown in FIG. 13, the third power supply line 26c is shared by the switch cell 12b and the power gating cell 10 as in the layout structure 2a of the first embodiment. As shown in FIG. 14, the third power supply line 26 c is disposed on the first interlayer insulating film 94 a formed on the semiconductor substrate 97.

  On the other hand, the bypass power supply line 30b included in the switch cell 12b is disposed on a second interlayer insulating film 94b different from the first interlayer insulating film 94a. The second interlayer insulating film 94b is an insulating film formed on the first interlayer insulating film 94a, for example. As shown in FIG. 14, the bypass power supply line 30b is disposed, for example, above the third power supply line 26c.

  As shown in FIG. 14, the fourth power supply line 26d2 included in the first power supply isolation cell 14b includes a first metal layer wiring 96a disposed in the first interlayer insulating film 94a and a second interlayer insulating film. A second metal layer wiring 96b disposed in the film 94b, and a first via 100a connecting the first metal layer wiring 96a and the second metal layer wiring 98b are provided.

  Similarly, the fifth power supply line 26e2 included in the second power supply isolation cell 16b is arranged in the third metal layer wiring 96c and the second interlayer insulating film 94b arranged in the first interlayer insulating film 94a. A fourth metal layer wiring 96d, and a third metal layer wiring 96c and a second via 100b connecting the fourth metal layer wiring 96d.

(2) Cell Pattern The cell pattern structure corresponding to the normal cell 8 and the power gating cell 10 is the same as the cell pattern structure corresponding to the unit cell described in the first embodiment.

―Switch cell―
15 and 16 are examples of the cell pattern of the switch cell 12b. The switch forming the switch cell 12b has a plurality of transistors connected in parallel.

  FIG. 15A shows an n-well layer 84b, a p-well layer 86b, a gate layer 90b, a contact layer 92b, and a first diffusion layer 88b.

  FIG. 15B shows a first first metal layer 54b2 (a layer corresponding to the first layer 54a) formed on the first interlayer insulating film 94a and the contact layer 92b. .

  The first first metal layer 54b2 includes a pattern 218c corresponding to the third cell ground line 18c (see FIG. 13), a pattern 220c corresponding to the third cell power line 20c (see FIG. 13), a cell And a pattern 222b2 corresponding to the internal wiring. A portion of the pattern 222b2 that protrudes from the pattern 220c is disposed on the first diffusion layer 88b (see FIG. 15).

  FIG. 16 shows the contact layer 92b and the second metal layer 55a (second layer) formed on the second interlayer insulating film 94b. The second metal layer 55a includes a pattern 366b corresponding to the cell bypass power supply line 66b (see FIG. 13) and a pattern 322b corresponding to the intra-cell wiring. The pattern 322b corresponding to the intra-cell wiring is arranged on the upper side of the first diffusion layer 88b.

  A contact hole penetrating the first interlayer insulating film 94a and the second interlayer insulating film 94b is formed by a portion of the contact layer 92b below the pattern 322b. A contact hole penetrating the first interlayer insulating film 94a is formed by another portion of the contact layer 92b. Therefore, the lower part of the pattern 322b and the other part of the contact layer 92b are preferably formed in different layers.

-First power supply isolation cell-
17 and 18 are examples of the cell pattern of the first power source separation cell 14b (see FIG. 13).

  FIG. 17A shows an n-well layer 84c and a p-well layer 86c.

  In FIG. 17B, a first first metal layer 54c2 (a layer corresponding to the first layer 54a) formed on the first interlayer insulating film 94a and a second interlayer insulating film 94b are formed. The first via layer 400a corresponding to the first via 100a is shown. FIG. 17B also shows the n-well layer 84c and the p-well 86c.

  The first metal layer 54c2 includes a pattern 218d corresponding to the fourth cell ground line 18d (see FIG. 13), a pattern 218e corresponding to the fifth cell ground line 18e, and a first metal layer wiring 96a (FIG. 14)).

  FIG. 18 shows a second metal layer 55b (a layer corresponding to the second layer 55a) formed on the second interlayer insulating film 94b and the via layer 400a. The second metal layer 55b has a pattern 296b corresponding to the second wiring portion 96b (see FIG. 14).

-Second power supply isolation cell-
The cell pattern of the second power supply isolation cell 16b is similar to the cell pattern of the first power supply isolation cell 14b. The cell pattern of the second power source separation cell 16b is a pattern obtained by inverting each cell pattern shown in FIGS. 16 and 17 with respect to the paper.

  According to the second embodiment, as in the first embodiment, the power feeding to the power gating cell 10 can be controlled for each cell.

(Embodiment 3)
The layout structure of the third embodiment is similar to the layout structure 2a of the first embodiment. Therefore, description of parts common to the first embodiment is omitted or simplified.

(1) Structure FIG. 19 is a plan view of a layout structure 2c according to the third embodiment. FIG. 19 does not show a circuit included in each cell.

  Similar to the layout structure 2a of the first embodiment, the layout structure 2c includes the normal cell 8, the power gating cell 10, the switch cell 12, the first power supply isolation cell 14c, and the second power supply isolation cell 16c. Have

  As shown in FIG. 19, the layout structure 2c includes a p-type (first conductivity type) well 106 and an n-type (second conductivity type) that includes the third power supply line 26c and is surrounded by the p-type well 106 in plan view. ) First well 108a.

  The layout structure 2c further includes an n-type second well 108b with which the first power supply line 26a overlaps in plan view. The layout structure 2c further includes an n-type third well 108c on which the second power supply line 26b overlaps in plan view.

As shown in FIG. 19, the first power supply isolation cell 14c is similar to the first power supply isolation cell 14 (see FIG. 2) of the first embodiment. However, the first power supply isolation cell 14c has a wiring 104 that connects the third power supply line 26c to the n-type first well 108a. For example, the wiring 104 is connected to an n ⁺ region 110 provided in the n-type first well 108a.

  As shown in FIG. 19, the second power source separation cell 16c has a structure in which the left and right sides of the first power source separation cell 14c are reversed with respect to the paper surface.

FIG. 20 is a cross-sectional view of the vicinity of the wiring 104. As shown in FIG. 20, the wiring 104 has a metal layer wiring 112 connected to the third power supply line 26 c and a contact 114 connecting the metal layer wiring 112 to the n ⁺ region 110.

FIG. 21 is a diagram illustrating the back gate potential of the transistor 116a formed in the first n-type well 108a. V _DD is a power supply potential. GND is a ground potential.

As shown in FIG. 19, the n-type first well 108a in which the transistor 116a is formed is separated from other n-type wells (second well 108b and third well 108c). Further, the n-type first well 108a is connected to the bypass power supply line 30 via the switch 28 (see FIG. 21). Therefore, when the switch 28 is opened, the n-type first well 108a is separated from the power supply potential V _DD . For this reason, not only the leakage current (subthreshold leakage current) between the source S and the drain D but also the leakage current (junction leakage current) between the first well 108a and the drain D is suppressed.

  FIG. 22 is a cross-sectional view of the vicinity of the third power supply line 26c (see FIG. 2) in the first embodiment. As shown in FIG. 22, the third power supply line 26 c is separated from the n-well 108.

  FIG. 23 is a diagram illustrating the back gate potential of the transistor 116b formed in the n-well 108 of the first embodiment.

As shown in FIG. 23, the n-well 108 is connected to the first power supply line 26a (or the second power supply line 26b). Therefore, power supply potential V _DD is always supplied to n well 108. Therefore, even if the switch 28 is opened, the leakage current (junction leakage current) between the n-well 108 and the drain D continues to flow.

  On the other hand, as described with reference to FIG. 21, according to the third embodiment, such a junction leakage current is suppressed. Therefore, according to the third embodiment, the power consumption of the inactive cell is further reduced.

  In the example shown in FIG. 19, a wiring 104 for connecting the third power supply line 26c to the second conductivity type well 108a is provided in both the first power supply isolation cell 14c and the second power supply isolation cell 16c. However, the wiring 104 for connecting the third power supply line 26c to the second conductivity type well 108a may be provided only in one of the first power supply isolation cell 14c and the second power supply isolation cell 16c.

  In the above example, as shown in FIG. 2 and the like, two cell rows in which the normal cells 8 and the like are arranged in the horizontal direction of the drawing are provided in the vertical direction. However, three or more cell rows may be arranged.

  In the above example, the first conductivity type is p-type, and the second conductivity type is n-type. However, the first conductivity type may be n-type and the second conductivity type may be p-type.

  Regarding the above first to third embodiments, the following additional notes are disclosed.

(Appendix 1)
A cell ground line disposed at one end, a cell power line disposed at the other end, the cell ground line, and a circuit connected to the cell power line; and the cell ground line and the cell power line. The first ground line, the second ground line parallel to the first ground line, and the first power line disposed between the first ground line and the second ground line A third ground line disposed on an extension line of the first ground line, a fourth ground line disposed on an extension line of the second ground line, and an extension line of the first power line. A plurality of unit cells arranged so as to form a second power line arranged between the third ground line and the fourth ground line;
A fifth ground line disposed on a line connecting the first ground line and the third ground line; and a third ground line disposed on a line connecting the first power line and the second power line. A unit cell, and a circuit connected to the third power line and the fifth ground line,
The third power line is shared with the unit cell, and further, a sixth ground line arranged on a line connecting the second ground line and the fourth ground line, and bypassing the third power line A switch cell having a bypass power supply line and a switch that connects the bypass power supply line to the third power supply line in response to a control signal;
A seventh ground line connecting the first ground line to the fifth ground line; an eighth ground line connecting the second ground line to the sixth ground line; A first power supply isolation cell having a fourth power supply line connecting a power supply line to the bypass power supply line;
A ninth ground line for connecting the third ground line to the fifth ground line; a tenth ground line for connecting the fourth ground line to the sixth ground line; and the second ground line. A layout structure of a semiconductor device, comprising: a second power supply isolation cell having a fifth power supply line connecting a power supply line to the bypass power supply line.

(Appendix 2)
In the semiconductor device according to attachment 1,
The semiconductor device layout structure, wherein the bypass power supply line is disposed between the third power supply line and the sixth ground line.

(Appendix 3)
In the semiconductor device according to attachment 1,
A layout structure of a semiconductor device, wherein the bypass power supply line is arranged in an interlayer insulating film different from the interlayer insulating film in which the third power supply line is arranged.

(Appendix 4)
In the layout structure according to any one of appendices 1 to 3,
A second conductivity type well including the third power supply line in plan view and surrounded by the first conductivity type well;
A layout structure of a semiconductor device, comprising: a wiring for connecting the third power supply line to the second conductivity type well.

(Appendix 5)
In the layout structure described in Appendix 4,
The layout structure of a semiconductor device, wherein the wiring is arranged in one or both of the first power supply isolation cell and the second power supply isolation cell.

(Appendix 6)
6. The layout structure according to any one of appendices 1 to 5, wherein the first power source separation cell and the second power source separation cell are twice as high as each unit cell and the switch cell in plan view. A layout structure of a semiconductor device, wherein

(Appendix 7)
Connected to a predetermined height, a first cell ground line disposed at one end, a first cell power line disposed at the other end, the first cell ground line and the first cell power line Obtaining a plurality of first cell patterns corresponding to unit cells having a circuit comprising:
Connected to the predetermined height, a second cell ground line disposed at one end, a second cell power line disposed at the other end, the second cell ground line and the second cell power line Obtaining a second cell pattern corresponding to a unit cell having a configured circuit;
The predetermined height, a third cell ground line disposed at one end, a third cell power line disposed at the other end, a cell bypass power line bypassing the third cell power line, and a control Obtaining a third cell pattern corresponding to a switch cell having a switch connecting the cell bypass power supply line to the third cell power supply line in response to a signal;
A height of twice the predetermined height, a fourth cell ground line disposed at one end, a fifth cell ground line disposed at the other end, and the fourth cell ground line in plan view; A fourth cell power line disposed between the fifth cell ground lines, and a first end of the fourth cell power line is connected to the fourth cell ground line and the fifth cell ground line. The second end of the fourth cell power supply line is located at the center of the first side sandwiched between cell ground lines, and the second end of the fourth cell power line is opposed to the first side in plan view. Obtaining a fourth cell pattern corresponding to the first power source separation cell disposed at a position corresponding to one end of the detour power line;
A height of twice the predetermined height, a sixth cell ground line disposed at one end, a seventh cell ground line disposed at the other end, and the sixth cell ground line in plan view; A fifth cell power line disposed between the seventh cell ground lines, and a third end of the fifth cell power line is connected to the sixth cell ground line and the seventh cell power line. The fourth end of the fifth cell power supply line is located at the center of the third side sandwiched between the cell ground lines, and the fourth end of the fifth cell power line is opposed to the third side in plan view. Obtaining a fifth cell pattern corresponding to a second power source separation cell disposed at a position corresponding to the other end of the bypass power source line;
The patterns corresponding to the first cell power supply lines of the plurality of unit cells overlap each other to form a pattern corresponding to the first power supply line and a pattern corresponding to the second power supply line, and the first of the unit cells. A pattern corresponding to the third power supply line is formed by overlapping a pattern corresponding to the second cell power supply line and a pattern corresponding to the third cell power supply line of the switch cell, and the first to third power supply lines And the pattern corresponding to the fourth cell power supply line of the first power supply isolation cell and the pattern corresponding to the fifth cell power supply line of the second power supply isolation cell are connected. Arranging the obtained first to fifth cell patterns. A semiconductor device layout method.

2 ... Layout structure 8 ... Multiple unit cells (normal cells)
10 ... Unit cell (power gating cell)
12 ... switch cell 14 ... first power supply isolation cell 16 ... second power supply isolation cell 18 ... cell ground line, 18b ... second cell ground line 18c ... third Cell ground line, 18d ... fourth cell ground line 18e ... fifth cell ground line, 18f ... sixth cell ground line 18g ... seventh cell ground line 20 ... Cell power line, 20b ... Second cell power line 20c ... Third cell power line, 20d ... Fourth cell power line 20e ... Fifth cell power line 22 ... Circuit 24a ... first ground wire, 24b ... second ground wire, 24c ... third ground wire 24d ... fourth ground wire, 24e ... fifth ground wire, 24f .. Sixth ground line 24g .. Seventh ground line, 24h .. Eighth ground line, 24i .. Ninth ground line 24j .. Tenth ground line 6a ... 1st power supply line, 26b ... 2nd power supply line, 26c ... 3rd power supply line 26d ... 4th power supply line, 26e ... 5th power supply line 28. ..Switch 30 ... detour power line 84 ... n well layer 86 ... p well layer 104 ... wiring 106 ... p type well 108a ... n type well

Claims (6)

A cell ground line disposed at one end, a cell power line disposed at the other end, the cell ground line, and a circuit connected to the cell power line; and the cell ground line and the cell power line. The first ground line, the second ground line parallel to the first ground line, and the first power line disposed between the first ground line and the second ground line A third ground line disposed on an extension line of the first ground line, a fourth ground line disposed on an extension line of the second ground line, and an extension line of the first power line. A plurality of unit cells arranged so as to form a second power line arranged between the third ground line and the fourth ground line;
A fifth ground line disposed on a line connecting the first ground line and the third ground line; and a third ground line disposed on a line connecting the first power line and the second power line. A unit cell, and a circuit connected to the third power line and the fifth ground line,
The third power line is shared with the unit cell, and further, a sixth ground line arranged on a line connecting the second ground line and the fourth ground line, and bypassing the third power line A switch cell having a bypass power supply line and a switch that connects the bypass power supply line to the third power supply line in response to a control signal;
A seventh ground line connecting the first ground line to the fifth ground line; an eighth ground line connecting the second ground line to the sixth ground line; A first power supply isolation cell having a fourth power supply line connecting a power supply line to the bypass power supply line;
A ninth ground line for connecting the third ground line to the fifth ground line; a tenth ground line for connecting the fourth ground line to the sixth ground line; and the second ground line. A layout structure of a semiconductor device, comprising: a second power supply isolation cell having a fifth power supply line connecting a power supply line to the bypass power supply line. The semiconductor device according to claim 1,
The semiconductor device layout structure, wherein the bypass power supply line is disposed between the third power supply line and the sixth ground line. The semiconductor device according to claim 1,
A layout structure of a semiconductor device, wherein the bypass power supply line is arranged in an interlayer insulating film different from the interlayer insulating film in which the third power supply line is arranged. The layout structure according to any one of claims 1 to 3, further comprising:
A second conductivity type well including the third power supply line in plan view and surrounded by the first conductivity type well;
A layout structure of a semiconductor device, comprising: a wiring for connecting the third power supply line to the second conductivity type well. In the layout structure according to any one of claims 1 to 4, wherein the first power source separation cell and said second power separation cell, Te viewed smell, each of the plurality of unit cells, said unit cell , layout structure of a semiconductor device characterized by having twice the height of our and said switch cell. Connected to a predetermined height, a first cell ground line disposed at one end, a first cell power line disposed at the other end, the first cell ground line and the first cell power line Obtaining a plurality of first cell patterns corresponding to unit cells having a circuit comprising:
Connected to the predetermined height, a second cell ground line disposed at one end, a second cell power line disposed at the other end, the second cell ground line and the second cell power line Obtaining a second cell pattern corresponding to a unit cell having a configured circuit;
The predetermined height, a third cell ground line disposed at one end, a third cell power line disposed at the other end, a cell bypass power line bypassing the third cell power line, and a control Obtaining a third cell pattern corresponding to a switch cell having a switch connecting the cell bypass power supply line to the third cell power supply line in response to a signal;
A height of twice the predetermined height, a fourth cell ground line disposed at one end, a fifth cell ground line disposed at the other end, and the fourth cell ground line in plan view; A fourth cell power line disposed between the fifth cell ground lines, and a first end of the fourth cell power line is connected to the fourth cell ground line and the fifth cell ground line. The second end of the fourth cell power supply line is located at the center of the first side sandwiched between cell ground lines, and the second end of the fourth cell power line is opposed to the first side in plan view. Obtaining a fourth cell pattern corresponding to the first power source separation cell disposed at a position corresponding to one end of the detour power line;
A height of twice the predetermined height, a sixth cell ground line disposed at one end, a seventh cell ground line disposed at the other end, and the sixth cell ground line in plan view; A fifth cell power line disposed between the seventh cell ground lines, and a third end of the fifth cell power line is connected to the sixth cell ground line and the seventh cell power line. The fourth end of the fifth cell power supply line is located at the center of the third side sandwiched between the cell ground lines, and the fourth end of the fifth cell power line is opposed to the third side in plan view. Obtaining a fifth cell pattern corresponding to a second power source separation cell disposed at a position corresponding to the other end of the bypass power source line ;
The patterns corresponding to the first cell power supply lines of the plurality of first cell patterns overlap with each other to form a pattern corresponding to the first power supply line and a pattern corresponding to the second power supply line, and the second A pattern corresponding to the second cell power line of the cell pattern and a pattern corresponding to the third cell power line of the switch cell overlap to form a pattern corresponding to the third power line, To a pattern corresponding to the third power supply line, a pattern corresponding to the fourth cell power supply line of the first power supply isolation cell, and a pattern corresponding to the fifth cell power supply line of the second power supply isolation cell. And arranging the first to fifth cell patterns acquired so as to be connected to each other.

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