JP6054080B2 - 支持体及びその製造方法、配線基板の製造方法、電子部品装置の製造方法、配線構造体 - Google Patents
支持体及びその製造方法、配線基板の製造方法、電子部品装置の製造方法、配線構造体 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/12—Using specific substances
- H05K2203/122—Organic non-polymeric compounds, e.g. oil, wax or thiol
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1383—Temporary protective insulating layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/23—Sheet including cover or casing
- Y10T428/239—Complete cover or casing
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
[第1の実施の形態に係る配線基板の構造]
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する断面図である。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2〜図7は、第1の実施の形態に係る配線基板の製造工程を例示する図である。本実施の形態では、支持体の両面に複数の配線基板となる部分を作製し支持体を除去後個片化して各配線基板とする工程の例を示すが、支持体の両面に1個ずつ配線基板を作製し支持体を除去する工程としてもよい。
第1の実施の形態の変形例では、支持基板21に対する接着力調整層22の他の配置例を示す。なお、第1の実施の形態の変形例において、既に説明した実施の形態と同一構成部品についての説明は省略する。図8は、第1の実施の形態の変形例に係る支持体を例示する平面図である。但し、図8では、支持体の一部のみを示している。
11、13、15、17 配線層
11a 第1層
11b 第2層
11p 第1電極パッド
12、14、16 絶縁層
12x、14x、16x ビアホール
17p 第2電極パッド
18 ソルダーレジスト層
18x 開口部
19 表面処理層
20、20A、20B 支持体
21 支持基板
21a プリプレグ
22 接着力調整層
22a、22b、22c、22d、22e、22f 領域
23 剥離層
24 金属箔
30 接合部
40 半導体チップ
50 アンダーフィル樹脂
100 レジスト層
100x 開口部
Claims (9)
- 支持基板上の外縁部を除く所定領域に前記支持基板と剥離層との接触面積を調整する接着力調整層を配置する工程と、
前記接着力調整層上及び前記支持基板の外縁部上に一方の面に前記剥離層が形成された金属箔を前記剥離層を前記支持基板側に向けて配置し、前記支持基板の外縁部と前記剥離層とを剥離可能な状態で仮接着する工程と、を有し、
前記剥離層として、シリコーン系樹脂、フッ素系樹脂、シリコーン系離型剤、又はフッ素系離型剤を用い、
前記支持基板と前記剥離層との剥離強度が30g/cm〜400g/cmであり、
前記仮接着する工程では、前記支持基板と前記接着力調整層とは接着され、前記剥離層と前記接着力調整層とは接着されずに接している支持体の製造方法。 - 前記接着力調整層を配置する工程では、プリプレグ上の外縁部を除く所定領域に前記接着力調整層を配置し、
前記仮接着する工程では、前記接着力調整層上及び前記プリプレグの外縁部上に一方の面に前記剥離層が形成された前記金属箔を前記剥離層を前記プリプレグ側に向けて配置し、前記プリプレグを加熱しながら前記金属箔を前記プリプレグ側に押圧して前記プリプレグを硬化させ、前記プリプレグから前記支持基板を得ると共に、前記支持基板と前記接着力調整層とを接着し、前記支持基板の外縁部と前記剥離層とを剥離できる状態で仮接着する請求項1記載の支持体の製造方法。 - 前記接着力調整層は、前記支持基板上の外縁部を除く所定領域に、複数の領域に分割されて配置される請求項1又は2記載の支持体の製造方法。
- 前記接着力調整層を配置する工程では、前記支持基板の両面側に、前記接着力調整層を配置し、
前記仮接着する工程では、前記支持基板の両面側に、一方の面に前記剥離層が形成された前記金属箔を配置する請求項1乃至3の何れか一項記載の支持体の製造方法。 - 請求項1乃至4の何れか一項記載の支持体の製造方法で前記支持体を作製する工程と、
前記支持体の前記金属箔の他方の面に、所定数の配線層及び絶縁層が積層された配線部材を作製する工程と、
前記支持基板と前記剥離層との間を剥離して前記支持基板及び前記接着力調整層を除去し、前記金属箔の一方の面に前記剥離層が形成され他方の面に前記配線部材が形成された構造体を作製する工程と、
前記構造体から前記剥離層及び前記金属箔を除去する工程と、を有する配線基板の製造方法。 - 請求項5記載の配線基板の製造方法で配線基板を作製する工程と、
前記配線基板上に電子部品を実装する工程と、を有する電子部品装置の製造方法。 - 支持基板上の外縁部を除く所定領域に配置された、前記支持基板と剥離層との接触面積を調整する接着力調整層と、
前記接着力調整層上及び前記支持基板の外縁部上に配置された、一方の面に前記剥離層が形成された金属箔と、を有し、
前記剥離層として、シリコーン系樹脂、フッ素系樹脂、シリコーン系離型剤、又はフッ素系離型剤を用い、
前記支持基板と前記剥離層との剥離強度が30g/cm〜400g/cmであり、
前記金属箔は、前記剥離層を前記支持基板側に向けて配置され、前記支持基板の外縁部と前記剥離層とが剥離可能な状態で仮接着されている支持体。 - 前記支持基板と前記接着力調整層とは接着され、前記剥離層と前記接着力調整層とは接着されずに接している請求項7記載の支持体。
- 支持基板上の外縁部を除く所定領域に配置された、前記支持基板と剥離層との接触面積を調整する接着力調整層と、
前記接着力調整層上及び前記支持基板の外縁部上に配置された、一方の面に前記剥離層が形成された金属箔と、を有し、
前記剥離層として、シリコーン系樹脂、フッ素系樹脂、シリコーン系離型剤、又はフッ素系離型剤を用い、
前記支持基板と前記剥離層との剥離強度が30g/cm〜400g/cmであり、
前記金属箔は、前記剥離層を前記支持基板側に向けて配置され、前記支持基板の外縁部と前記剥離層とが剥離可能な状態で仮接着されている支持体と、
前記支持体の前記金属箔の他方の面に、所定数の配線層及び絶縁層が積層された配線部材と、を有する配線構造体。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012162005A JP6054080B2 (ja) | 2012-07-20 | 2012-07-20 | 支持体及びその製造方法、配線基板の製造方法、電子部品装置の製造方法、配線構造体 |
| KR1020130084571A KR101937717B1 (ko) | 2012-07-20 | 2013-07-18 | 지지체, 지지체 제조 방법, 배선 기판 제조 방법, 전자 부품 제조 방법, 및 배선 구조체 |
| US13/945,266 US9215812B2 (en) | 2012-07-20 | 2013-07-18 | Support body, method of manufacturing support body, method of manufacturing wiring board, method of manufacturing electronic component, and wiring structure |
| TW102125890A TWI592062B (zh) | 2012-07-20 | 2013-07-19 | 支持體及其製造方法,佈線板之製造方法,電子零件之製造方法,暨佈線構造 |
| US14/938,157 US9763332B2 (en) | 2012-07-20 | 2015-11-11 | Support body, method of manufacturing support body, method of manufacturing wiring board, method of manufacturing electronic component, and wiring structure |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2012162005A JP6054080B2 (ja) | 2012-07-20 | 2012-07-20 | 支持体及びその製造方法、配線基板の製造方法、電子部品装置の製造方法、配線構造体 |
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| Publication Number | Publication Date |
|---|---|
| JP2014022665A JP2014022665A (ja) | 2014-02-03 |
| JP2014022665A5 JP2014022665A5 (ja) | 2015-08-06 |
| JP6054080B2 true JP6054080B2 (ja) | 2016-12-27 |
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| US (2) | US9215812B2 (ja) |
| JP (1) | JP6054080B2 (ja) |
| KR (1) | KR101937717B1 (ja) |
| TW (1) | TWI592062B (ja) |
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|---|---|---|---|---|
| TWI830474B (zh) * | 2021-11-05 | 2024-01-21 | 日商揖斐電股份有限公司 | 配線基板 |
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| CN105451471B (zh) * | 2014-06-19 | 2018-03-27 | 健鼎(无锡)电子有限公司 | 多层电路板的制作方法 |
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| US20160073505A1 (en) * | 2014-09-05 | 2016-03-10 | Unimicron Technology Corp. | Manufacturing method of multilayer flexible circuit structure |
| US10249561B2 (en) * | 2016-04-28 | 2019-04-02 | Ibiden Co., Ltd. | Printed wiring board having embedded pads and method for manufacturing the same |
| US10727081B2 (en) * | 2016-07-01 | 2020-07-28 | Mitsubishi Gas Chemical Company, Inc. | Method for manufacturing package substrate for mounting a semiconductor device, and method for manufacturing semiconductor device mounting substrate |
| CN106211638B (zh) * | 2016-07-26 | 2018-07-24 | 上海美维科技有限公司 | 一种超薄多层印制电路板的加工方法 |
| KR102396894B1 (ko) * | 2016-08-05 | 2022-05-11 | 미츠비시 가스 가가쿠 가부시키가이샤 | 지지 기판, 지지 기판이 부착된 적층체 및 반도체 소자 탑재용 패키지 기판의 제조 방법 |
| CN109788665B (zh) * | 2017-11-14 | 2020-07-31 | 何崇文 | 含电子元件的线路基板及其制作方法 |
| CN113243146B (zh) | 2018-12-14 | 2024-11-19 | 三菱瓦斯化学株式会社 | 半导体元件搭载用封装基板的制造方法 |
| US10624213B1 (en) * | 2018-12-20 | 2020-04-14 | Intel Corporation | Asymmetric electronic substrate and method of manufacture |
| JP7521258B2 (ja) * | 2020-05-26 | 2024-07-24 | Toppanホールディングス株式会社 | 基板ユニット、基板ユニットの製造方法及び半導体装置の製造方法 |
| TW202211748A (zh) * | 2020-09-11 | 2022-03-16 | 巨擘科技股份有限公司 | 能被精確剝除之多層基板結構及其製造方法 |
| US11178774B1 (en) * | 2021-03-23 | 2021-11-16 | Chung W. Ho | Method for manufacturing circuit board |
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| TWI365026B (en) * | 2009-06-11 | 2012-05-21 | Unimicron Technology Corp | Method for fabricating packaging substrate and base therefor |
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| KR101043540B1 (ko) * | 2009-10-01 | 2011-06-21 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
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| US8828245B2 (en) * | 2011-03-22 | 2014-09-09 | Industrial Technology Research Institute | Fabricating method of flexible circuit board |
| MY167064A (en) * | 2011-03-30 | 2018-08-09 | Mitsui Mining & Smelting Co | Multilayer printed wiring board manufacturing method |
| CN103430642B (zh) * | 2011-03-30 | 2016-04-06 | 三井金属矿业株式会社 | 多层印刷线路板的制造方法 |
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2013
- 2013-07-18 US US13/945,266 patent/US9215812B2/en active Active
- 2013-07-18 KR KR1020130084571A patent/KR101937717B1/ko not_active Expired - Fee Related
- 2013-07-19 TW TW102125890A patent/TWI592062B/zh not_active IP Right Cessation
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI830474B (zh) * | 2021-11-05 | 2024-01-21 | 日商揖斐電股份有限公司 | 配線基板 |
Also Published As
| Publication number | Publication date |
|---|---|
| US9215812B2 (en) | 2015-12-15 |
| KR101937717B1 (ko) | 2019-01-11 |
| JP2014022665A (ja) | 2014-02-03 |
| TWI592062B (zh) | 2017-07-11 |
| KR20140011963A (ko) | 2014-01-29 |
| TW201412201A (zh) | 2014-03-16 |
| US20160066433A1 (en) | 2016-03-03 |
| US9763332B2 (en) | 2017-09-12 |
| US20140020931A1 (en) | 2014-01-23 |
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