JP6045351B2 - Verification apparatus and verification method - Google Patents

Description

  The present invention relates to a technique for verifying reliability such as soft error resistance of an electronic device.

  With the miniaturization and high integration of semiconductor devices, the problem of soft errors caused by environmental radiation (such as cosmic neutrons and alpha rays on the ground) is causing various electronic devices, especially circuits such as SRAM, logic gates, and clock systems. It has become obvious about. There is a need for a technique for verifying reliability such as soft error resistance of electronic devices.

  The mechanism of soft error caused by environmental radiation is described as follows, for example. When neutrons with extremely high energy enter the nuclei constituting the device, the nucleons (neutrons and protons) in the nucleus repeatedly collide, and nucleons with particularly high energy are emitted outside the nucleus. When the nucleon cannot have enough kinetic energy to jump out of the nucleus, light particles such as protons, neutrons, deuterons, and alpha particles evaporate from the residual nuclei in the excited state. Finally, the residual nuclei also have a counterattack energy, so all of these secondary particles fly in the device at a distance corresponding to their range.

  When secondary ions having α-rays generated from radioisotopes contained in a semiconductor package or the like or charges generated as a result of a nuclear reaction pass through a depletion layer of a storage node in an SRAM “high” state, for example, Is absorbed by the node, and holes flow in the opposite direction, and the charge is collected in the storage node by a funneling mechanism in which the charge collection region extends along the track of the ions. When charges exceeding the critical charge amount are collected, the “high” state changes to the “low” state, and a soft error occurs. The above is a typical mechanism that has been considered as a soft error mechanism caused by environmental radiation, and is also referred to as SEU (Single Event Upset).

  Regarding the SEU of the memory device, a case where a plurality of cells cause an error simultaneously is called MCU (Multi Cell Upset) and is distinguished from SBU (Single Bit Upset). When the MCU occurs in the same word, it is called MBU (Multiple Bit Upset), and it is difficult to repair with normal ECC (Error Correction Code), and therefore, there is a possibility of system down.

  Soft errors including the above SEU are different from hardware errors (fixed hardware failures), and are updated to new data even after an error occurs. There is also a problem that is difficult. As described above, the influence of the soft error generated in the logic circuit of the electronic device means that a malfunction occurs in the computer processor, ASIC, control digital circuit, and the like, and causes malfunction of the electronic system. There is concern.

  In recent years, programmable devices or programmable logic devices (hereinafter abbreviated as PLDs as appropriate) are frequently used as control logic circuits for various electronic systems. The PLD includes a programmable logic circuit or memory, and can be used as a dedicated logic circuit by programming a desired function (user logic) in the logic circuit after the user purchases the PLD. Among PLDs, the use of FPGA (Field Programmable Gate Array) is increasing. The FPGA constructs an arithmetic circuit and a control circuit by storing logic circuit information (configuration information of the user logic circuit) in a memory inside the device (configuration memory, hereinafter abbreviated as CM as appropriate).

  However, it is becoming a problem that the data or logic stored in the memory of the FPGA is likely to cause malfunction of the electronic system by being destroyed by a soft error. Normally, the electronic device / electronic system is considered in the design so as not to be affected by malfunction, but this causes an increase in power consumption, development / verification man-hours, cost, and the like.

  As a technique for verifying the effectiveness (soft error tolerance) of soft error countermeasures for circuit devices such as FPGA, an error (error data) is intentionally generated for the target device (data programmed in its memory or logic circuit). There is a method for verifying the operation of the device when it is inserted, so-called error insertion method.

  Regarding the above technique, for example, there is JP-T-2010-507170 (Patent Document 1) ("Method and apparatus for injecting transient hardware failure for software test"). In Patent Document 1, “The present invention includes a method and apparatus for injecting a dynamic fault into a circuit device. The apparatus includes a selected one of a plurality of outputs of a circuit device and a plurality of errors of the circuit device. A first register adapted to receive selection data identifying at least one of the selected ones of the registers, a selected one of the outputs and at least one of the selected ones of the error registers; A second register adapted to receive dynamic fault data for transmission to the first and at least one of each selected one of the outputs and each selected one of the error registers Including a controller for applying the selection data to the first register and the dynamic fault data to the second register to provide dynamic faults to the first register. " It has been described as. That is, it describes a quality evaluation method for changing the error detection register to simulate error insertion and evaluating the operation of software.

  As a technique for estimating the total number of failures / defects in error tolerance verification, there is a technique using time series data (in other words, history information). For example, there is JP-A-5-324309 (Patent Document 2) (“Software Quality Evaluation Device”). In Patent Document 2, “the object of the present invention is to enable completion degree evaluation with high reliability.” “Execution means for executing evaluation target software (SW) according to a test case (T.Cs); Collection means for collecting data on the number of T.Cs used for execution, test coverage information for SW, and the number of detected bugs; ability estimation means for estimating the ability of T.Cs based on the collected data; Based on the SW reliability growth model based on the collected data of the means for collecting the means of collecting T.Cs based on the collected data of the T.Cs by correcting the T.Cs ability according to the prescribed rules SW potential bug total number based on the reliability growth model using the first estimation means to obtain the SW potential bug total number estimated value and the T.Cs number information and the detected bug number among the collected data of the collecting means Each of the second estimation means for obtaining the estimated value and the first and second estimation means It is composed of comprehensive judgment means that processes the estimated value according to a predetermined rule to obtain the estimated total number of bugs. " That is, it describes a verification method for estimating the total number of faults and defects using time-series data evaluated using test cases at an intermediate stage before all test cases are evaluated.

Special table 2010-507170 gazette JP-A-5-324309

  As described above, with the miniaturization and high integration of semiconductor devices, the influence of soft errors caused by environmental radiation in electronic devices is expanding. Among them, the frequency of soft errors in PLDs such as FPGAs increases, and there is a possibility that the impact on electronic systems where the use of PLDs such as FPGAs is increasing will increase.

  In response to this situation, conventional PLD countermeasures include error tolerance such as error detectors and error detection / correction mechanisms using ECC (error correction code), and TMR (triple redundancy). Designs using improved technology are being made. Moreover, in an electronic system equipped with a PLD, measures such as a redundant configuration such as hardware duplication are taken.

  However, it is not easy to verify (or test) the tolerance of transient errors such as soft errors in electronic devices (PLD) and electronic systems that have been subjected to these error tolerance techniques.

  For example, conventionally, verification by neutron irradiation experiments has been performed as a method for verifying resistance to soft errors caused by neutrons. Although this method can be verified by actual measurement, a large-scale experiment using a particle accelerator or the like is necessary, and the experiment time is limited and the cost is high. That is, there is a problem that it cannot be used easily when designing electronic devices and electronic systems.

  As a method of verifying soft error tolerance by emulation with a real machine, there is the error insertion method described above. For example, an error insertion function is provided by an FPGA vendor. In this method and function, by comparing an operation result when an error is inserted into a portion (desired portion in the memory) determined on the user side in the target device (FPGA) and an operation expectation value corresponding thereto. Verify the soft error tolerance.

  However, the method for determining the error insertion location is not taken into consideration. For effective verification, it is considered necessary to effectively select the error insertion point, but such a method and function are not considered. The prior art document does not mention the method for determining the error insertion location.

  In addition, as the capacity of PLD such as FPGA increases, the number of error insertion target parts and candidates increase. Therefore, there is a problem that the verification time increases if the conventional method is used. Therefore, it is essential to establish a verification method using highly efficient emulation that can cope with an increase in the number of error insertion target locations in the entire PLD memory area.

  An object of the present invention is to provide a technique capable of increasing the efficiency of verification of error resistance such as a soft error for an electronic device such as a PLD.

  In order to achieve the above object, for example, the configuration described in the claims is adopted.

  The present application includes a plurality of means for solving the above-described problems. For example, “a verification apparatus for verifying error tolerance of an electronic device including a programmable device, and a configuration of a user logic circuit of the electronic device” A control unit for reading and writing data to a memory for storing information, an error insertion unit for writing error insertion information for verification of the error tolerance to a user logic circuit configured in the memory of the electronic device, and A comparison unit that compares and checks an operation result obtained by executing an operation in a user logic circuit configured in a memory of the electronic device and an expected value thereof, and error information including the comparison result and the error insertion information as a history. A recording unit for recording, an input unit for inputting information of a user logic circuit configured in a memory of the electronic device, and the error An analysis unit that analyzes information including an error detection error rate of a part of the user logic circuit based on the information and outputs an analysis result, and the error insertion unit includes information on the user logic circuit, Based on the error information and the analysis result, the error insertion information for the next round is determined.

  Also, “the error insertion unit generates a new error insertion pattern based on the random pattern generation unit that generates a random error insertion pattern, the information of the user logic circuit, the error information, and the analysis result. An error insertion pattern generation unit, and the error insertion unit uses the random error insertion pattern and the newly generated error insertion pattern to generate an error insertion pattern to be used next time and an error corresponding thereto. It is characterized in that an insertion location is selected and determined as the error insertion information ”.

  According to a typical embodiment of the present invention, verification of error resistance such as a soft error can be made highly efficient with respect to an electronic device such as a PLD.

It is a figure which shows the structure of the verification system of Embodiment 1 of this invention. 6 is a diagram illustrating a data configuration example in an error information recording unit in Embodiment 1. FIG. In Embodiment 1, it is a figure which shows the structural example of an error information analysis part. In Embodiment 1, it is a figure which shows the structural example of an error insertion pattern production | generation part. In Embodiment 1, it is a figure shown about the error insertion method. In Embodiment 1, it is explanatory drawing which shows the example of the error insertion pattern determination method. FIG. 10 is a diagram illustrating an example of a display screen related to error tolerance verification in the first embodiment. In Embodiment 1, it is a figure which shows the example of a processing flow of a verification apparatus and a verification method. It is a figure which shows the structure of the verification system of Embodiment 2 of this invention. It is a figure which shows the structure of the verification system of Embodiment 3 of this invention. It is a figure which shows the structure of the principal part of the verification system of Embodiment 4 of this invention. It is a figure which shows the structure of the principal part of the verification system of Embodiment 5 of this invention. It is a figure which shows the image of the dynamic control of this Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Note that only some of the lines such as arrows between the processing units shown in the drawings are illustrated.

<Summary>
In the present embodiment, a case will be described in which the present invention is applied to a method for verifying the tolerance of soft errors caused by environmental radiation targeting PLD. This verification apparatus and the corresponding verification method use the above-described error insertion method as a method for verifying the soft error tolerance of the configuration memory (CM) of the PLD, and have an error insertion function and a verification function corresponding thereto. In this function, during verification (or test), as described above, an error (error insertion pattern) is inserted into the PLD (CM), and the calculation result in the PLD (CM) is compared with the calculated expected value. Error check and record the error information as history (time-series data). And it has a function of performing analysis etc. using error information (history) and dynamically changing / determining error insertion contents (error insertion pattern, error insertion location, etc.) of the next round. In other words, feedback control is performed so as to effectively determine future error insertion contents based on past error information or verification results. This function effectively selects the next error insertion location from the entire target memory area. In particular, selection is made so as to reduce the number of error insertion points, thereby increasing the efficiency of verification. It becomes possible to verify the increase in the capacity of the PLD in a practical time.

  The verification apparatus generates error insertion (error insertion pattern) information at the time of verification and controls error insertion, and means for directly reading and writing the PLD CM corresponding to the error insertion (error insertion pattern) , Means for comparing the operation result corresponding to the error insertion in the user logic constructed in the PLD CM and its expected value, and information including the comparison result and the error insertion pattern information is error information (history). As means for recording, means for analyzing an index value of error tolerance such as error detection error rate of the target user block based on the error information (history), means for analyzing circuit information of user logic (for example, circuit) Means for analyzing logical information including interblock connection information of user block from logical data, and user block object from circuit mounting data Based on the error information (history), index value analysis results, and user logic analysis information, the next error insertion (error insertion pattern) information is generated. Or a means for selecting and executing error insertion for the PLD. As an operation / processing example in the above configuration, an error is inserted into the CM in accordance with the error insertion pattern to operate the user logic, the output is checked for errors, the presence / absence of error occurrence, the error insertion pattern, and the like are recorded. Then, from the accumulated record information (error information), the inter-user block connection information obtained from the PLD logic information and the mounting information, the physical arrangement information, and the like, the error insertion location and pattern for the next round are determined.

<Embodiment 1>
A first embodiment of the present invention will be described with reference to FIGS.

[system]
FIG. 1 shows the overall configuration of a soft error tolerance verification system for a programmable device (PLD), which is the system of the first embodiment. The system includes a verification device 1 and a programmable device (PLD) 2. The PLD 2 and the verification device 1 are connected. The verification apparatus 1 is a PDL2 environmental radiation-induced soft error tolerance verification apparatus and has a function of verifying the soft error (SE) resistance of the CM3 of the PLD2. A terminal 100 of a user (verifier) U is connected to the verification device 1.

  The PLD 2 includes a configuration memory (CM) 3 and a configuration memory read / write (CMR / W) circuit 4. PLD2 is, for example, an FPGA. Any device similar to PLD2 can be applied to this system. CM3 is a memory for storing configuration information of the user logic circuit, and includes a memory element or an array of logic elements, and circuit information (user logic: UL) for realizing a desired function (user logic: UL) according to input data (D0). User logic circuit configuration information) is stored (in other words, the UL is programmed). The CMR / W circuit 4 is a memory control unit having a function of directly reading / writing data at a designated position in the CM 3. The PLD 2 includes an error detection mechanism using ECC or the like.

  The terminal 100 of the user (verifier) U is, for example, a PC or the like, and includes a screen processing unit 101, a display 102, and the like. The screen processing unit 101 performs processing for displaying a screen serving as a GUI (graphical user interface) on the display 102. A user (verifier) U can check various data information and input instructions to the verification apparatus 1 on this screen (described later). The screen processing unit 101 acquires various data information such as the analysis result (d15) and error information (d14) of the verification device 1.

  The verification device 1 includes an error insertion unit 20 (an error insertion pattern generation unit 21 and a random pattern generation unit 22), a logic information analysis unit 11, a mounting information analysis unit 12, an operation expected value comparison unit 13, an error information recording unit 14, and an error The information analysis unit 15 and the like are included. The verification apparatus 1 inputs or stores necessary data information such as UL information (d0) and operation expected value data (d6). Further, the user U can input / output these data information with the verification device 1 or the terminal 100.

  The logic information analysis unit 11 receives and analyzes the circuit logic data (d1) in the UL information (d0), and acquires, stores and outputs the UL logic information (d11) as a result. UL logical information (d11) includes logical connection information between circuits in CM3 (UL) of PLD2. The mounting information analysis unit 12 receives and analyzes the circuit mounting data (d2) in the UL information (d0), and acquires, stores, and outputs the UL mounting information (d12) as a result. The UL mounting information (d12) includes physical circuit arrangement information in CM3 (UL) of PLD2. In the above 11 and 12, by referring to and analyzing the UL information (d0), it is possible to know which area in the CM 3 is used as the UL. The error insertion unit 20 determines an error insertion location using the information (d11, d12). The UL information (d0) corresponds to the input data (D0). In other words, the above 11 and 12 are UL input units or analysis units.

  The operation expected value comparison unit 13 compares the UL operation result data (d5) input from the output of the CM3 of the PLD 2 with the operation expected value data (d6) and outputs the comparison result (d13). The UL calculation result data (d5) is calculation result data in the UL of CM3 of PLD2 based on the data (d21) input from the error insertion unit 20 (21). The operation expected value data (d6) is the expected value data of the UL operation (d5) of the CM3 of the PLD2 calculated in advance by the verification device 1 or the like before executing the error insertion. This is the data of the operation result operated (normal operation result data when no soft error occurs). Alternatively, the expected result data (d6) may be the result data of the logic simulation described later (Embodiment 2).

  The error information recording unit 14 includes detection error information (d8) indicating an error detected by an error detection mechanism such as ECC of the PLD2 in accordance with the input of d21 and the output of d5 in the PLD2, and the calculated expected value comparison unit 13. The comparison result information (d13) that is the output of the error insertion and the error insertion pattern (d21) that is output from the error insertion pattern generation unit 21 are input, and these are combined and recorded and stored as error information (d14). That is, the error information (d14) is error data and error history information during the UL operation. The error information recording unit 14 manages an error information recording table T1 and an expected value error bit position list table T2 shown in FIG.

  Based on the error information (d14) accumulated in the error information recording unit 14, the error information analysis unit 15 generates and outputs a verification result or analysis result (d15) of soft error tolerance through analysis processing. The terminal 100 inputs the analysis result (d15) and performs screen display processing.

  In the terminal 100, other various data information (d11, d12, d6, d14, d21, etc.) handled by the verification apparatus 1 may be displayed on the screen in a similar manner so that the user can check and edit.

  In the error insertion unit 20, the random pattern generation unit 22 uses the UL mounting information (d12) to generate a random pattern (random error insertion pattern) for error insertion with respect to a random position with respect to the entire physical area of CM3. d22) is generated. The random pattern (d22) is used for generating the error insertion pattern (d21). Note that 22 and 21 may be integrated into one.

  The error insertion pattern generation unit 21 uses the error information (d14), the analysis result (d15), the logic information (d11), the mounting information (d12), and the random pattern (d22) to give to the CM3. The error insertion pattern (d21) is generated and determined, and the CMR / W circuit 4 is controlled using the error insertion pattern (d21). Then, the CMR / W circuit 4 writes the data of the error insertion pattern (d21) to the designated location (position) of the CM 3 according to the error insertion pattern (d21) (that is, error insertion is performed). The error insertion pattern (d21) does not include the UL input (D0), but includes information on an error insertion location (position) in the CM3 area and information on the timing of the insertion.

  In the system according to the first embodiment, the verification device 1 is provided and connected as a dedicated circuit or device outside the PLD 2 (CM 3). The configuration is not limited to the configuration in which the verification apparatus 1 and the user terminal 100 are separated, and may be integrated into one. As another form described later, the verification apparatus 1 can be provided as a part of the PLD 2 (CM 3).

[Error information]
FIG. 2A shows an example of the configuration of an error information recording table T1 that records and holds error information (d14) in the error information recording unit 14 as a history. The error information recording table T1 includes (a) an identification number, (b) an error insertion pattern, (c) error detection information, and (d) expected value error information in order from the leftmost item. (A) The identification number is a number for identifying an error insertion event (in other words, each verification or test). (B) The error insertion pattern is information (for example, a bit string) of the error insertion pattern (d21) generated and output by the error insertion pattern generation unit 21, and an error insertion position or position information (for example, a memory cell in which an error bit is written), And timing information. (C) The error detection information is detection error information (d8) detected by the error detection mechanism of the PLD 2, and is, for example, the above-described ECC information. In addition, it is applicable not only to ECC. (D) The expected value error information is information on the comparison result (d13) in the operation expected value comparison unit 13, and is, for example, a flag indicating match / mismatch. When there is a bit that has been inverted in the comparison between the calculation result (d5) and the calculation expected value (d6), it is recorded as a mismatch flag and also as an expected value error bit position in the following table T2. Note that the information of (d) is not limited to the flag, and for example, information on a mismatched portion (position in the CM 3) may be recorded simultaneously.

  FIG. 2B is a configuration example of a table T2 that stores a list of expected value error bit positions, which will be described later. The table T2 may be recorded at another location such as the error insertion unit 20.

[Error information analysis section]
FIG. 3 shows a configuration example of the error information analysis unit 15. The error information analysis unit 15 includes an error insertion count counting unit 31, an error event weighting unit 32, an error number adding unit 33, and an error detection error rate calculating unit 34. As an outline, the error information analysis unit 15 performs calculation for estimating the error detection error rate (d34) using the error information (d14) and the UL information (d0) as necessary.

  The error insertion count counter 31 counts the number of error insertions from the input error information (d14). The error event weighting unit 32 weights information as an error event on the error information (d14). The error number adding unit 33 adds the number of errors (number of error events) according to the weighting by 32. The error detection error rate calculation unit 34 calculates the error detection error rate (d34) from the number of error insertions by 31 and the number of weighted error events by 33. The error detection error rate (d34) is an index value of error tolerance (a value for determining a part (for example, a block or a circuit part) that is highly likely to generate a soft error), and is included in the output analysis result (d15). include. In particular, the error information analysis unit 15 uses the UL information (logical connection information and physical arrangement information) to estimate and calculate the error detection error rate (d34) in units of blocks or circuit units constituting the UL.

  In this embodiment, in order to verify SE tolerance, control is performed to dynamically change the error insertion location and the corresponding error insertion pattern (d21) based on the error information (d14). In the configuration example of the unit 15, the error detection error rate (d34) is calculated (in other words, estimated), and the calculation error is calculated at the same time. At this time, the error detection error rate (d34) and the calculation error are calculated by a Monte Carlo method (random method) weighted by an error insertion pattern realization probability, such as a focused sampling method.

  As another embodiment, in the error information analysis unit 15 or the like, error information (d14) as a result of a single error insertion using physical arrangement information (included in d12) of a user logic block or circuit unit. Based on the above, the error detection error rate (d34) when a multi-bit error occurs may be analyzed.

[Error insertion pattern generator]
FIG. 4 shows a configuration example of the error insertion pattern generation unit 21. The error insertion pattern generation unit 21 includes an error appearance probability calculation unit 41, an error insertion pattern generation unit 42, and an error insertion pattern selection unit 43.

  The error appearance probability calculation unit 41 calculates the probability (error appearance probability: d41) that an error that has occurred in CM3 in a certain test round (error insertion event) appears as a calculation result (error appearance probability: d41). And the UL mounting information (d12), the error information (d14), and the analysis result (d15).

  The error insertion pattern generation unit 42 generates an error insertion pattern (d42) for a candidate for the next test based on the error appearance probability (d41) obtained in 41 above.

  The error insertion pattern selection unit 43 selects one of the error insertion pattern (d42) created in 42 and the random pattern (d22) described above, and uses the error insertion pattern ( d21) is determined and output to PLD2 (CMR / W circuit 4).

  For example, when the error information (d14) has a small history (when the number of tests is still small), the random pattern (d22) is selected. The error insertion pattern (d42) generated in the above 42 is selected. Note that it is not always necessary to make a deterministic selection, and a method of selecting one of them probabilistically may be used.

[Error insertion method]
FIG. 5 briefly shows the error insertion method as a supplement. (A) shows the bit state of UL at a certain position (a plurality of memory cells) in the CM3 region of PLD2. Let X be a column and Y be a row in an array of memory cells. As a certain position, attention is paid to a plurality of bits in the X1 to Xm columns of the Y1 row. For example, the order is 00110 ... 0. (A) corresponds to data of a normal expected operation value (d6). For example, assuming the occurrence of an SBU soft error, the bit at the position (Y1, X2) is set as the error insertion location. In this case, an error insertion pattern (in the case of overwriting) as shown in (b) is obtained, and the position (Y1, X2) is an inverted bit. (C) is pattern information in the case of an inverted bit position instruction corresponding to (b). The error insertion pattern generation unit 21 gives the error insertion pattern information (d21) as described above to the CMR / W circuit 4, and the data of the pattern is written (overwritten) from the CMR / W circuit 4 to the area of the corresponding position of CM3. The When an error is detected in the bit at the error insertion position (Y1, X2) as a result of the calculation, an “calculated expected value error” is recorded, and an “expected value error bit position” (FIG. 2B) is recorded. In other words, the operation result (d5) and the operation expected value (d6) are compared, and the bit position that has been inverted as the difference in the operation result (d5) is referred to as an “expected value error bit position”. Record as in (b).

[Error insertion pattern determination method]
FIG. 6 shows an example of a method of determining the error insertion pattern (d21) in the error insertion pattern generation unit 21. As a premise (initial stage), an error insertion pattern (d21) based on the random pattern (d22) generated by the random pattern generation unit 22 is inserted into the CM3 area a predetermined number of times, and the resulting error information (d14) is the error information recording unit. 14 is stored.

  First, as shown in FIG. 6A, in the present embodiment (error insertion pattern generation unit 21), the entire target area of CM3 (UL) is virtually divided into a plurality of blocks (user blocks). That is, the unit of the divided block area is handled. FIG. 6A shows an example of dividing the area of CM3 (UL) into blocks (referred to as b). For example, there are blocks b11 to b44.

  Next, the error insertion pattern generation unit 21 calculates the similarity of the appearance of the operation error in units of block b in the plurality of blocks b in the CM3 area based on the accumulated error information (d14). A block b having a high similarity is extracted.

  As an example of a qualitative reference for the appearance of the calculation error, an expected value error bit position list table T2 in FIG. 2B is shown. In this table T2, the position of the bit whose value was inverted when the above-described operation expected value error occurred is recorded as the expected value error bit position. In other words, T2 indicates error occurrence record information.

  In the table T2 of FIG. 2B, the left column indicates the number of error insertions, and the right column indicates the expected value error bit position for each block b in the CM3 (UL) area. For example, when the first error is inserted, the expected value error bit positions in the block b11 in FIG. 6 are the 10th and 31st bits in terms of conversion from the first bit in the block. The error insertion pattern generation unit 21 calculates the similarity of how the calculation error appears in units of the block b based on the table T2 and the like.

  Further, as a method for extracting blocks having a high degree of similarity, for example, an extraction method using a known correspondence analysis method (AFC) or the like that can extract a highly similar target for a qualitative variable can be applied. The block having a high degree of similarity is configured by a circuit unit having a similar influence on the operation output, such as a highly related circuit unit on the UL data flow or a circuit unit configuring the same bus ( The UL content can also be analyzed from the UL information (d0)). Therefore, it is considered that the error implementation rate (also referred to as error appearance probability) is similar (substantially the same). Therefore, in this system, one block is selected from the extracted group of blocks with high similarity (two or more blocks), the error implementation rate is calculated with the block, and the result is used as the calculation result of the remaining blocks. use. As a result, the calculation of the error implementation rate can be simplified and reduced, and the speed can be increased. Therefore, the number of error insertions for the CM3 area can be reduced, and verification can be made more efficient.

  FIG. 6B is an example of simplification of the calculation of the error realization rate. Let e be the error realization rate of block b. For example, since the similarity between the block b11 and the block b22 (how the calculation error appears) is high, they are extracted as similar blocks, approximated as their error realization rate e11 = e22, and represented by one block b22. is there. In the test after the next time, it is efficient if error insertion is performed with one block b22 as a target location. As a result, error insertion into the block b11 becomes unnecessary. Therefore, it is possible to reduce the number of error insertions necessary for calculating the error rate (error detection error rate d34, error appearance probability d41, etc.), and to calculate the error rate at high speed. At the time of each error insertion from the error insertion pattern generation unit 21, the above calculation is adopted based on the error information (d14), and the error insertion location and the error insertion pattern are made efficient.

  A similar method can be applied in addition to the above-described block division method. For example, the UL information (d0) or the analysis information thereof may be used to divide flexibly in units such as a UL circuit unit. Moreover, you may divide | segment not only in a block (rectangular) but in the unit (for example, vertical or horizontal line unit) of a desired shape.

  In the present embodiment, the number of error insertions (total number) of the error insertion pattern (d21) is not particularly limited. For example, when the purpose is to verify tolerance against SEU that is a single error, one error is inserted, and when the purpose is to verify tolerance against MCU that is a multi-bit error, a plurality of errors are inserted. In the MCU tolerance verification, an error is inserted in consideration of the range where electrons are spread by radiation. Basically, if the number of error insertions is increased, the verification accuracy increases, but it takes time. In the present embodiment, the number of times and time can be reduced while achieving verification accuracy of a certain level or more by the above-described function.

[Screen example]
FIG. 7 shows an example of a screen (user operation screen) 51 at the time of soft error tolerance verification in the first embodiment. For example, the main screen 51 is displayed on the display 102 of the terminal 100 of the user U described above. On this screen 51, an operation window 52 for verifying soft error tolerance of PLD2 (CM3) is displayed. The operation window 52 includes a verification parameter 53, a verification result 54, an error insertion result list 55, and the like as information.

  In the verification parameter 53, a parameter for the operation of the SE tolerance verification of the verification device 1 is displayed and can be input and set by the user U. Examples of parameters include “number of error insertions”, “calculation significance level”, “target calculation error”, and the like. Other parameters may be displayed. Here, the “number of error insertions” corresponds to the number of feedback information in the control of dynamic change of error insertion in this verification, and indicates the number of past error insertion information used when generating the error insertion pattern (d21). . The “calculation significance level” indicates the significance level at the time of calculation (FIGS. 3 and 15) for estimating the error detection error rate (d34) described above. “Target calculation error” indicates a target calculation error range when the above significance level is assumed.

  In the verification result 54, information on each item of the verification result and a list of 55 error insertion results for the entire UL area of the CM3 of the PLD 2 and each block b described above are displayed. Information on each item of the verification result includes “error insertion number”, “error detection number”, “expected value error number”, “error detection error rate”, and “calculation error”. The “number of error insertions” is the total number, and corresponds to the number of error insertions in the table T2 in FIG. “Number of detected errors” indicates the number of detected all errors including those detected in d8. The “number of expected value errors” indicates the number of all errors detected as the aforementioned expected value error bits. The “error detection error rate” corresponds to the error detection error rate (d34) of the analysis result (d15) described above. “Calculation error” indicates a calculation error that becomes a convergence condition (FIG. 8 to be described later) of the process of this verification (test).

  In the error insertion result list 55, an identification number, “insertion location”, “error detection”, “expected value comparison”, and the like are displayed as information based on the table T1 in FIG. . “Insertion location” indicates the insertion location or position of the error insertion pattern in CM3. “Error detection” indicates the presence / absence of error detection and its contents (ECC or the like). “Expected value comparison” indicates match / mismatch.

  In addition, on this screen, setting items relating to the way of dividing the block (b) may be provided.

[Verification processing]
FIG. 8 shows an example of a processing flow of the verification method for the soft error resistance of the CM 3 of the PLD 2 by the verification apparatus 1 according to the first embodiment. The verification device 1 is activated by the user U and the verification process is started.

  In step S61, the user U inputs verification parameters (including the number of error insertions) on the above-described screen (FIG. 7). Further, UL information (d0) configured in the CM 3 may be input by the user U on the same screen.

  In step S62, the error insertion pattern generation unit 21 generates an error insertion pattern (d21) as the start of a certain test (verification). In other words, the error insertion content (including the error insertion location and pattern) is determined.

  In step S63, the error insertion pattern (d21) generated in S62 is input from the error insertion pattern generation unit 21 to the CMR / W circuit 4, and the error insertion pattern (d21) is transmitted from the CMR / W circuit 4 to the UL in CM3. Insert an error according to d21).

  In step S64, the UL in the CM 3 of the PLD 2 is operated, that is, a predetermined calculation is executed.

  In step S65, the expected operation value comparison unit 13 performs an expected value error check process for comparing the operation result data (d5) from the CM 3 with the corresponding operation expected value data (d6).

  In step S66, the error information recording unit 14 records the aforementioned error information (d14) in the table T1 (and T2) based on each input information (d13, d8, d21).

  In step S67, the error information analysis unit 15 performs an analysis process using the error information (d14) or the like. At this time, a calculation error is calculated as a convergence condition for verification. At this time, if necessary, either or both of the error insertion result information and the calculation result are displayed on the operation window 52 on the above-described screen (FIG. 7) (may be displayed in the same manner at other timings).

  In step S68, as the convergence condition determination process in the error information analysis unit 15, the calculation error calculated in S67 is compared with the target calculation error range (the set value by the user input). If the calculation error is less than or equal to the target calculation error range (S68-Y), the process is terminated. If not (N), the process returns to the error insertion pattern generation (S62) and the test (verification) by the next error insertion is performed. Repeat in the same way.

[Control image]
FIG. 13 shows an image of dynamic control according to the present embodiment as a supplement. In (a), as an initial stage, (1) First, random error insertion locations mainly in random error insertion patterns (d22, d21) in the block b group similar to FIG. 6 in CM3 (UL) of PLD2 Run the test to. For example, b11, b22, etc. are each block b that becomes an error insertion area. (2) Then, error information (d14) as a result of the test is analyzed.

  In (b), as feedback control, (3) based on the above analysis results, the effective error insertion contents in the next and subsequent tests are determined. In other words, the next error insertion location is selected in consideration of the error appearance probability of each block b, etc., and the error insertion location and the number of times are reduced or reduced (the block similarity described above, etc.) Using the error insertion pattern (d42, d21), a test is performed on the corresponding target portion. (4) Then, error information (d14) as a result of the test is analyzed. (5) After that, the feedback control is repeated in the same manner and the process is terminated by the convergence determination.

[Effects]
According to the system of the first embodiment, error insertion is performed during a test (verification) of soft error resistance caused by environmental radiation such as neutrons for CM3 of PLD2 (particularly FPGA) used in various electronic systems. It has a function to dynamically change patterns and locations. As a result, the time for verifying the soft error resistance can be shortened, and the verification efficiency can be improved. As a result, it is possible to reduce the tolerance design / verification man-hours, increase the accuracy of verification of calculation errors such as SDC (Silent Data Corruption), and improve the reliability of electronic devices / electronic systems.

  In the present embodiment, a verification method using highly efficient emulation or the like that reduces the error insertion target portion in the entire CM3 region of the PLD 2 such as an FPGA is realized.

<Embodiment 2>
Next, Embodiment 2 will be described with reference to FIG. FIG. 9 shows the configuration of the verification system of the second embodiment. The verification system according to the second embodiment has a function of performing soft error tolerance verification using a logic simulation result. The second embodiment has many elements in common with the first embodiment, but as a different part, the verification device 1B includes input of logic simulation result data (d3), simulation result storage unit 17, error insertion unit 20B ( Error insertion pattern generation unit 21B). In the verification apparatus 1B of the second embodiment, the error insertion number 20B is improved in the efficiency of reducing the number of error insertions using the result (d3) of the UL logic simulation performed in advance.

  The verification device 1B is different from the verification device 1 of FIG. 1 in that a simulation result storage unit 17 is added and the processing content of the error insertion unit 20B is different. The simulation result storage unit 17 inputs and stores UL logic simulation result data (d3). The logic simulation result data (d3) is a result of the UL logic simulation on the computer. In addition, although it has a processing part (for example, in the terminal 100) which performs logic simulation execution and the result data (d3) separately, it is good also as a form which provided the said processing part in the verification apparatus 1B.

  Based on the error information (d14), the analysis result (d15), the logic information (d11), the mounting information (d12), the logic simulation result (d17), and the random pattern (d22), the error insertion pattern generation unit 21B An error insertion pattern (d21) is generated and determined, and the CMR / W unit 4 is controlled.

  As a function of the error insertion pattern generation unit 21B, in addition to the function of the error insertion pattern generation unit 21 (FIG. 4 and the like), an expected value comparison result (d13) and a logic simulation result (d17) by error insertion are used. Alternatively, it has a function of calculating the similarity between the aforementioned divided blocks (b) (FIG. 6 and the like) using only the logic simulation result (d17).

  The error information analysis unit 15 may calculate the error detection error rate (d34) using the logic simulation result (d17).

  According to the second embodiment, it is possible to efficiently calculate the similarity between the blocks (b) using the logic simulation result (d17) (FIG. 6), and to reduce the number of error insertion points / numbers. Verification efficiency can be improved.

<Embodiment 3>
Next, Embodiment 3 will be described with reference to FIG. FIG. 10 shows the configuration of the verification system of the third embodiment. The verification system of the third embodiment has a function of performing soft error resistance verification using a neutron irradiation experiment result (background technology). The verification apparatus 1C of the third embodiment improves the efficiency of reducing the number of error insertions by using the radiation irradiation experiment result of the UL (all or a part thereof or a corresponding test circuit) performed in advance.

  In the verification apparatus 1C of the third embodiment, an irradiation experiment result accumulation unit 18 for accumulating the irradiation experiment result data (d4) of the radiation of the UL or test circuit is added to the verification apparatus 1. Further, the error insertion pattern generation unit 21C is based on the error information (d14), the analysis result (d15), the logic information (d11), the mounting information (d12), the irradiation experiment result (d18), and the random pattern (d22). Then, an error insertion pattern (d21) is generated and determined, and the CMR / W circuit 4 is controlled.

  Regarding the function of the error insertion pattern generation unit 21C, in addition to the functions described above (FIG. 4 and the like), the expected value comparison result (d13) and the irradiation experiment result (d18) by error insertion are used, or the irradiation experiment result ( Only d18) is used to calculate the similarity between the aforementioned divided blocks (b) (FIG. 6 and the like).

  In addition, the error information analysis unit 15 may calculate the error detection error rate (d34) described above using the irradiation experiment result (d18).

  According to the third embodiment, it is possible to efficiently calculate the similarity between the blocks (b) using the irradiation experiment result (d18), and to reduce the number and the number of error insertion points, that is, high efficiency of verification. Can be made.

<Embodiment 4>
Next, Embodiment 4 will be described with reference to FIG. FIG. 11 shows a configuration of a main part of the verification system according to the fourth embodiment. In the fourth embodiment, a configuration example in which a verification port (901) for outputting data of an arbitrary part in the UL of CM3 of PLD2 to the outside is shown for the purpose of improving the efficiency of reducing the number of inserted errors. FIG. 11 shows an example in which the data of the node 92 (target portion) in the portion 91 is used for verification for the arbitrary portion 91 of the UL configured in the CM 3 in the PLD 2. Although 900 is a partial enlargement in CM3 (UL), other parts can be similarly configured. In order to detect, that is, output the data of the node 92 to the outside, a verification output circuit 93 is newly configured in the CM 3. Then, the verification data 94 (corresponding to d5) output from the verification output circuit 93 is output to the outside through the verification output port 901. The verification data 94 output to the outside is input to a verification data expectation value comparison unit 96 that is a processing unit corresponding to the above-described calculation expected value comparison unit 13. The verification data expected value comparison unit 96 compares the verification data 94 with the verification data expected value 95 (corresponding to d6). The comparison result (97) is recorded in the error information recording unit 14 as a part of the above-described calculation expected value comparison result (d13). Further, the error information analysis unit 15 calculates an error detection error rate (d34) using data including the verification data (94).

  The verification output circuit 93 and the port 901 can be provided as a logical element by a program as a part of the CM3 of the PLD2.

  According to the fourth embodiment, it is possible to further increase the efficiency of verification using the additional element.

<Embodiment 5>
Next, Embodiment 5 will be described with reference to FIG. FIG. 12 shows a configuration of a main part of the verification system according to the fifth embodiment. In the fifth embodiment, the function corresponding to the above-described verification device 1 is configured as a part of the CM 3 of the PLD 2 (separate from the UL) as the logic of the verification circuit. In FIG. 12, the PLD 2 includes a part 301 in which the UL in the CM 3 is configured and a part 302 in which the verification circuit is configured. The verification circuit 302 includes a circuit unit having the function of the above-described verification device 1 and the CMR / W circuit 4. A verification result d30 (corresponding to d15 described above) is output from the verification circuit 302 and can be used in the same manner as described above. The verification circuit 302 provided in the CM 3 may be provided as either a hard macro or a soft macro.

  In the fifth embodiment, a verification circuit 302 having all the functions of the verification device 1 described above is provided in the CM 3. As another embodiment, only a part of the functions of the verification apparatus 1 may be provided as 302 in the CM 3 and other functions may be provided outside the PLD 2 to be connected and linked. Or it is good also as a form which provides the circuit of the said function outside CM3 in PLD2.

  In the fifth embodiment, the verification circuit 302 corresponding to the verification device 1 can be realized as a program, and the device configuration can be simplified with the same effects as those of the first embodiment.

<Others>
By using the system of the present embodiment, it is possible to estimate the soft error resistance with high efficiency even at the development / design stage of the PLD2, for example. In this case, as the user logic configured (programmed) in the CM 3, a predetermined logic may be configured and verified.

  In the present embodiment, feedback control is performed so as to determine error insertion contents (location and pattern) each time using the logical information (d11) and the mounting information (d12) in the UL information (d0). Error insertion content can be made more efficient over time, such as reducing the next insertion target block. For example, a random pattern (d22) is first tried for the entire area of CM3 (UL). As a result, when an error is detected at several places (block b or the like), the error insertion is tried in the same manner from the next time on that place and its periphery. In the conventional method, since there are many targets (candidates) for error insertion after the next time, it takes time to verify the entire area. On the other hand, in the present embodiment, it is possible to reduce and determine the target (candidate) for error insertion from the next time onward based on the error information history, so that the verification time for the entire region can be reduced.

  Although the random pattern (d22) is used in the verification in the present embodiment, a specific pattern may be used. For example, a specific pattern according to design time or manufacturing time may be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the verification device 1 of the present invention can be realized by a software program. The present invention can be applied not only to soft errors caused by radiation but also to verification (or testing, evaluation, etc.) of transient errors. The present invention can be applied to any device similar to PLD2 (such as a system LSI including a programmable memory such as CM3). For example, an LSI obtained by adding other elements to the FPGA is also applicable. The error type is not limited to SEU and MCU, and can be applied.

  DESCRIPTION OF SYMBOLS 1 ... Verification apparatus, 2 ... Programmable device (PLD), 3 ... Configuration memory (CM), 4 ... Configuration memory read / write circuit (CMR / W circuit), 11 ... Logic information analysis part, 12 ... Mounting information Analysis unit 13 ... Expected calculation comparison unit 14 Error information recording unit 15 Error information analysis unit 20 Error insertion unit 21 Error insertion pattern generation unit 22 Random pattern generation unit 100 Terminal

Claims (15)

A verification device for verifying error tolerance of an electronic device including a programmable device,
A control unit that reads and writes data to and from a memory that stores configuration information of a user logic circuit of the electronic device;
An error insertion unit that writes error insertion information for verification of the error tolerance to a user logic circuit configured in a memory of the electronic device;
A comparison unit that compares and checks the calculation result of the operation execution in the user logic circuit configured in the memory of the electronic device and the expected value;
A recording unit for recording error information including the comparison result and the error insertion information as a history;
An input unit for inputting information of a user logic circuit configured in a memory of the electronic device;
An analysis unit that analyzes information including a convergence condition based on the error information and outputs an analysis result; and
The error insertion section determines the error insertion information of the next round based on the information of the user logic circuit, the error information, and the analysis result. The verification device according to claim 1,
The error insertion part is
A random pattern generation unit for generating a random error insertion pattern;
An error insertion pattern generation unit that newly generates an error insertion pattern based on the information of the user logic circuit, the error information, and the analysis result;
The error insertion unit selects an error insertion pattern to be used in the next round and an error insertion position corresponding thereto from the random error insertion pattern and the newly generated error insertion pattern, and serves as the error insertion information. A verification device characterized by determining. The verification device according to claim 1,
The input unit is
A logic analysis unit that analyzes logic connection information between blocks or circuit units constituting the user logic circuit by inputting logic information of the user logic circuit;
A mounting analysis unit that analyzes physical arrangement information of blocks or circuit units constituting the user logic circuit by inputting the mounting information of the user logic circuit;
The error insertion unit determines the error insertion information of the next time using the logical connection information and physical arrangement information. The verification device according to claim 3,
The analysis unit performs calculation to estimate an error detection error rate in units of blocks or circuit units constituting the user logic circuit, using the error information and the logical connection information and physical arrangement information. A verification device characterized by The verification device according to claim 2,
The recording unit, as the error information, the comparison result, detection error information by the error detection mechanism of the electronic device output from the electronic device, error insertion information including the error insertion pattern and the error insertion location, A verification apparatus characterized by recording the data. The verification device according to claim 1,
A verification apparatus using logic simulation result data for all or part of the user logic circuit in addition to the error information. The verification device according to claim 1,
A verification apparatus characterized by using, in addition to the error information, radiation irradiation experiment result data previously executed for all or a part of the user logic circuit or a corresponding test circuit. The verification device according to claim 1,
The memory of the electronic device is configured with a verification port including a verification output circuit connected to the node in order to output and verify data of an arbitrary target node in the user logic circuit.
The comparison unit compares the verification data output from the verification port with the expected value and checks the comparison data,
The recording unit holds the comparison result as the error information,
Wherein the analysis unit, the verification data by using, calculating the error detection error rate, the verification device characterized by. The verification device according to claim 1,
The processing unit including the error insertion unit is configured as a verification circuit in a region different from the region of the user logic circuit to be verified inside the memory of the electronic device including the programmable device, Verification device to do. The verification device according to claim 1,
The analysis unit analyzes the error detection error rate when a multi-bit error occurs based on error information of a single error insertion result using physical arrangement information of the block or circuit unit of the user logic circuit A verification device characterized by: The verification device according to claim 1,
The error insertion unit, as the content of the error insertion information,
A first error insertion pattern for inserting an error into a single bit as an error insertion position;
And a second error insertion pattern for inserting an error into a plurality of bits as an error insertion position. The verification device according to claim 1,
It has a screen processing unit that outputs a screen that allows the user to input information,
The screen includes an item that allows a user to input parameters for the verification, an item that outputs a result of the verification or an intermediate state, and an item that outputs detailed contents of the error insertion information. The verification apparatus characterized by this. The verification device according to claim 1,
The error insertion unit calculates the similarity of how the error appears for each unit of a plurality of blocks or circuit units in the entire area of the user logic circuit configured in the memory of the electronic device, and the plurality of the similarity is high. When a block or a circuit unit is extracted, a part of the extracted block or circuit unit is selected as a target for the next error insertion. In the verification apparatus as described in any one of Claims 1-13,
A verification apparatus, wherein the electronic device is an FPGA. A verification method for verifying error tolerance of an electronic device including a programmable device using a verification device,
A first step of inputting, by a user, information on a user logic circuit configured in a memory storing parameters for verification and configuration information of a user logic circuit of the electronic device;
A second step of determining error insertion information for verification of the error tolerance with respect to a user logic circuit configured in a memory of the electronic device;
A third step of writing data of the error insertion information to a user logic circuit configured in a memory of the electronic device;
A fourth step of outputting a calculation result and detection error information by operation execution in a user logic circuit configured in a memory of the electronic device;
A fifth step of comparing and checking the operation result and its expected value;
A sixth step of recording error information including the comparison result, the detected error information, and the error insertion information as a history;
A seventh step of analyzing information including a convergence condition based on the error information and outputting an analysis result;
Determining the convergence condition for the end of the verification and ending if the convergence condition is satisfied, and if not satisfying, an eighth step returning to the second step, and
In the second step,
Generating a random error insertion pattern; and
Generating a new error insertion pattern based on the information on the user logic circuit, the error information, and the analysis result, and
In the second step, based on the information on the user logic circuit, the error information, and the analysis result, the random error insertion pattern and the newly generated error insertion pattern are used in the next round. A verification method characterized by selecting an error insertion pattern to be used and an error insertion location corresponding to the error insertion pattern and determining the error insertion information as the error insertion information.

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