JP5601176B2 - Switching regulator - Google Patents

Description

  The present invention relates to a switching regulator.

  Conventionally, a power supply circuit that converts an input voltage into a desired voltage is provided in an electronic device. Such a power supply circuit includes, for example, a switching regulator that performs output control of a power supply voltage by switching operation of a transistor, a smoothing circuit that smoothes the output voltage of the switching regulator, and a switching regulator that divides the smoothed output voltage. And a voltage dividing circuit for feedback output (see Patent Document 1).

  A switching regulator of such a power supply circuit includes a high-side (high-potential-side) transistor connected to a power supply, a comparator that compares a feedback voltage with a reference voltage, and generates a comparison signal. And a drive pulse generation circuit for generating a drive pulse for driving the gate of the transistor based on the level shift circuit for increasing the voltage level of the drive pulse generated by the drive pulse generation circuit. The high-side transistor is turned on by the high-level pulse of the drive pulse whose voltage level is increased.

  Since the level shift circuit is provided to increase the voltage of the drive pulse generated by the drive pulse generation circuit to a predetermined voltage that can control the high-side transistor, a high voltage is supplied to the level shift circuit. The Therefore, a high voltage resistance is required for a transistor to which a high voltage is applied in the level shift circuit. In order to prevent the breakdown of the transistor due to the high voltage, the gate oxide film of the transistor to which the high voltage is applied (hereinafter abbreviated as a high breakdown voltage transistor) is formed thick.

JP 2007-028770 A

  As described above, since the gate oxide film of the high breakdown voltage transistor in the level shift circuit is formed thick, the high breakdown voltage transistor has a low transfer conductance and a low switching speed. Therefore, if a high level drive pulse is input to the level shift circuit and the level of the drive pulse is shifted, the high level pulse width after the level shift is shortened.

  The drive pulse generation circuit generates a high-precision drive pulse having a high level pulse width in order to control the conduction time (ON time) of a transistor of the switching regulator (hereinafter abbreviated as an output transistor) with high accuracy. However, as described above, if the pulse width of the high level pulse supplied to the output transistor is shortened by the low speed operation of the high voltage transistor in the level shift circuit, the conduction time of the output transistor cannot be controlled with high accuracy. As a result, the switching regulator cannot control the current supplied to the load with high accuracy.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a switching regulator that controls a high-side output transistor with high accuracy.

The first side surface of the switching regulator includes a first transistor connected to a high potential power source,
A switching element provided between the first transistor and a reference power supply, wherein the conduction state changes according to the conduction state of the first transistor;
A comparator that compares a voltage obtained by feeding back an output voltage at a connection point between the first transistor and the switching element with a reference voltage to generate a comparison signal;
A level shift circuit for increasing the voltage level of the comparison signal and outputting a high voltage comparison signal;
And a drive pulse generation circuit for generating a drive pulse for driving the gate of the first transistor based on the high voltage comparison signal.

  According to the first aspect, the high-side output transistor can be controlled with high accuracy.

It is a figure explaining the power supply circuit relevant to this Embodiment. 6 is a timing chart for explaining the operation of the power supply circuit related to the present embodiment. It is a block diagram of a level shift circuit. It is a circuit diagram of a level shift circuit. It is a timing chart of a level shift circuit. It is a figure explaining the power supply circuit of 1st Embodiment. 3 is a timing chart illustrating the operation of the power supply circuit according to the first embodiment. It is a figure explaining a drive pulse generation circuit. 6 is a timing chart for explaining the operation of the drive pulse generation circuit. 6 is another timing chart for explaining the operation of the drive pulse generation circuit. It is a figure explaining the power supply circuit of 2nd Embodiment. It is a timing chart explaining operation | movement of the power supply circuit of 2nd Embodiment.

  FIG. 1 is a diagram for explaining a power supply circuit related to the present embodiment. A power supply circuit 1 in FIG. 1 includes a switching regulator 10 that performs output control of a power supply voltage Vdd by a switching operation of a transistor Q0, a smoothing circuit 21 that smoothes an output voltage of the switching regulator 10 at a connection point N1, and a smoothing circuit. And a voltage dividing circuit 22 that divides the output voltage Vout smoothed by the output voltage 21 and outputs it as a feedback voltage Vfb to the comparator 11 of the switching regulator 10.

  The switching regulator 10 compares the reference voltage Vref and the feedback voltage Vfb and outputs a comparison signal Cmp, and generates a drive pulse Ton based on the comparison signal Cmp output from the comparator 11. The circuit (DPG) 12, the level shift circuit (LS) 13 that increases the voltage level of the drive pulse Ton output from the drive pulse generation circuit 12 and outputs the high voltage drive pulse Dp, and the drive output from the level shift circuit 13 Based on the pulse Dp, the transistor Q0 is turned on and off (off state). The transistor Q0 is provided between the transistor Q0 and a reference power source, for example, GND. The conduction state changes according to the conduction state of the transistor Q0. And a diode D0 (switching element).

  The comparator 11 is also referred to as a comparator, and a reference voltage Vref is input to a non-inverting input terminal (+ terminal), and a feedback voltage Vfb is input to an inverting input terminal (−terminal). The comparator 11 generates a high level comparison signal Cmp when the reference voltage Vref is higher than the feedback voltage Vfb. Further, the comparator 11 generates a low level comparison signal Cmp when the reference voltage Vref is lower than the feedback voltage Vfb. Then, the comparator 11 outputs the comparison signal Cmp to the drive pulse generation circuit 12.

  The drive pulse generation circuit 12 is a so-called mono-multi (monostable multivibrator) circuit that generates a pulse based on an input signal. Specifically, the drive pulse generation circuit 12 generates a high-level drive pulse Ton that turns on the transistor Q0 for the first period using the rising edge of the comparison signal Cmp output from the comparator 11 as a trigger. The drive pulse generation circuit will be described in detail with reference to FIGS.

  The level shift circuit 13 increases the voltage level of the drive pulse Ton input from the drive pulse generation circuit 12, and outputs a high voltage drive pulse Dp to the gate of the transistor Q0. In order to increase the voltage level in this manner, it is necessary to apply a voltage higher than the source voltage corresponding to the power supply voltage Vdd to the gate of the high-side transistor Q0 to turn on the transistor Q0. Because. Details will be described later.

  The transistor Q0 is an NMOS transistor having a smaller on-resistance than the PMOS transistor. Hereinafter, the transistor Q0 will be described as an NMOS transistor. The drain of the transistor Q0 is connected to the power supply of the power supply voltage Vdd (high potential power supply), and the source is connected to the connection point N1.

  The smoothing circuit 21 has at least an inductor L0 and a capacitor C0. The smoothing circuit 21 smoothes the output voltage of the switching regulator 10 at the connection point N <b> 1 and outputs it to the voltage dividing circuit 22 and the load 23 connected to the output of the smoothing circuit 21. The load 23 is, for example, a CPU or LSI.

  The voltage dividing circuit 22 includes a resistor R0 and a resistor R1 that divide the output voltage Vout. The voltage dividing circuit 22 outputs the divided voltage as a feedback voltage Vfb to the inverting input terminal of the comparator 11 of the switching regulator 10.

  The diode D0 is a switching element provided between the transistor Q0 and a reference power source, for example, GND, and has a cathode connected to the connection point N1. The diode D0 is also called a free wheel diode. The diode D0 is provided to discharge the magnetic energy accumulated in the inductor L0 of the smoothing circuit 21 as a current when the transistor Q0 is turned off. Therefore, the conduction state of this switching element (diode D0) changes according to the conduction state of transistor Q0. Specifically, the transistor Q0 is turned off when the transistor Q0 is turned on, and is turned on when the transistor Q0 is turned off.

  The diode D1 whose anode is connected to the power supply voltage Vpp and the capacitor C1 connected to the connection point N2 constitute a so-called bootstrap circuit, and are provided for applying “power supply voltage Vdd + power supply voltage Vpp” to the level shift circuit 13. Yes. Details will be described later.

  The power supply voltage Vpp is applied to the diode D1, and the power supply voltage Vdd is applied to the drain of the transistor Q0. The bias voltage Vbias is applied to the comparator 11, the drive pulse generation circuit 12, and the level shift circuit 13. The reference voltage Vref is applied to the non-inverting input terminal of the comparator 11. For example, the power supply voltage Vpp is 5 V, the power supply voltage Vdd is 12 V, the bias voltage Vbias is 5 V, and the reference voltage Vref is determined according to the output voltage Vout.

  FIG. 2 is a timing chart for explaining the operation of the power supply circuit 1 in FIG. 1. From the top, the comparison signal Cmp output from the comparator 11, the drive pulse Ton output from the drive pulse generation circuit 12, and the level shift circuit 13 are shown. Output level-shifted drive pulse Ton, that is, drive pulse Dp, transistor Q0 on-state, off-state, voltage LM at point LM, current I10 and output current Io of inductor L0, feedback voltage Vfb, and reference voltages Vref and VH The voltage Vh is shown.

  The operation of the power supply circuit 1 in FIG. 1 will be described below with reference to the timing chart in FIG.

  If the feedback voltage Vfb becomes lower than the reference voltage Vref between time T0 and time T1, the comparator 11 outputs a high level comparison signal Cmp. Then, the drive pulse generation circuit 12 outputs a high level drive pulse Ton, and the level shift circuit 13 outputs a high level drive pulse Dp in which the voltage of the drive pulse Ton is increased.

  At this time, the output timing of the drive pulse Dp is delayed by a certain time (between time T0 and time T1) from the input timing of the drive pulse Ton by a high voltage transistor of the level shift circuit 13 described later. Further, the high level pulse width W2 of the drive pulse Dp is shorter than the high level pulse width W1 of the drive pulse Ton. That is, the high level of the drive pulse Ton is reduced in the drive pulse Dp.

  The reason why the output timing of the drive pulse Dp is delayed and the pulse width W2 of the drive pulse Dp is shortened will be described with reference to FIGS. 3 is a block diagram of the level shift circuit 13, FIG. 4 is a circuit diagram of the level shift circuit 13, and FIG. 5 is a timing chart of the level shift circuit 13.

  First, the voltage applied to the level shift circuit 13 will be described with reference to FIG. The voltage at the VH (L) point on the low side becomes the bias voltage Vbias, and the voltage at the VL (L) point becomes the ground GND in FIG. The voltage at the VH (H) point on the high side is from the power supply voltage Vpp (minimum: 5 V) to “power supply voltage Vdd + power supply voltage Vpp” (maximum: 12 V + 5 V), and the voltage at the VL (H) point is from the vicinity of the ground GND The power supply voltage becomes Vdd. The reason why the voltage at the VH (H) point on the high side becomes “power supply voltage Vdd + power supply voltage Vpp” will be described later.

  Next, the operation of the level shift circuit 13 will be described with reference to FIGS. Transistors Q1, Q3, Q4, and Q7 in FIG. 4 are NMOS transistors, and transistors Q2, Q5, Q6, and Q8 are PMOS transistors. The timing chart of FIG. 5 shows, in order from the top, the drive pulse Ton input to the input terminal In, the voltage Va at the point A, the voltage Vb at the point B, and the drive pulse Dp output from the output terminal Out. Vth at the voltage Vb at the point B is a threshold voltage of the inverter constituted by the transistors Q7 and Q8. The voltage Vth is, for example, a voltage in the vicinity of an intermediate voltage between the maximum voltage (power supply voltage Vdd + power supply voltage Vpp) applied to the point VH (H) and the minimum voltage (GND = 0) applied to the point VL (H). Suppose that

  When a high-level drive pulse Ton is input to the input terminal In, the transistor Q2 is turned off, the transistor Q1 is turned on, the transistor Q3 is turned off, and the transistor Q4 is turned on. When the transistor Q4 is turned on, the point B becomes low level and the transistor Q5 is turned on. When the transistor Q5 is turned on, the point A becomes high level and the transistor Q6 is turned off. At this time, as shown in FIG. 5, the voltage Va at the point A increases from 0V to the power supply voltage Vdd + power supply voltage Vpp, and the voltage Vb at the point B decreases from the power supply voltage Vdd + power supply voltage Vpp to 0V. When the voltage Vb becomes equal to or lower than the threshold voltage Vth, the transistor Q8 functioning as an inverter is turned on, the transistor Q7 is turned off, and a high-level drive pulse Dp is output from the output terminal Out. A maximum of “power supply voltage Vdd + power supply voltage Vpp” is applied to the gate of transistor Q6.

  When a low level driving pulse Ton is input to the input terminal In, that is, when the driving pulse Ton falls, the transistor Q2 is turned on, the transistor Q1 is turned off, the transistor Q3 is turned on, and the transistor Q4 is turned off. Become. When the transistor Q3 is turned on, the point A becomes low level and the transistor Q6 is turned on. When the transistor Q6 is turned on, the point B becomes high level and the transistor Q5 is turned off. At this time, as shown in FIG. 5, the voltage Va at the point A drops from the power supply voltage Vdd + the power supply voltage Vpp to 0V, and the voltage Vb at the point B rises from 0V to become the power supply voltage Vdd + the power supply voltage Vpp. When the voltage Vb becomes equal to or higher than the threshold voltage Vth, the transistor Q8 functioning as an inverter is turned off and the transistor Q7 is turned on, and a low-level driving pulse Dp is output from the output terminal Out. Note that a maximum of “power supply voltage Vdd + power supply voltage Vpp” is applied to the gates of the transistors Q5, Q7, and Q8.

  As described above, the high-level drive pulse Dp having the width W5 is output from the output terminal Out until the voltage Vb becomes equal to or lower than the threshold voltage Vth and again becomes equal to or higher than the threshold voltage Vth.

  As described above, the maximum voltage of “power supply voltage Vdd + power supply voltage Vpp” is applied to the gates of the transistors Q5 to Q8. Therefore, it is necessary to increase the thickness of the gate oxide film of the transistors Q5 to Q8 to prevent the transistor from being destroyed by applying a high voltage to the gate. However, when the gate oxide film is thickened, the transfer conductance of the MOS transistor is lowered and the switching speed is also slowed down.

  When the transfer conductance of the transistors Q5 to Q8 is lowered, the amount of change in the voltages Va and Vb for a certain time, that is, the slope of the voltage change is smaller than that in the case where the transfer conductance is not lowered. As a result, as shown in FIG. 5, the level-shifted drive pulse Dp rises with a delay from the rise timing of the drive pulse Ton. Further, the high level pulse width W5 of the drive pulse Dp is shorter than the high level pulse width W4 of the drive pulse Ton output from the drive pulse generation circuit 12.

  Further, as shown by the broken line in FIG. 5, when the high level pulse width of the drive pulse Ton is shortened, the voltage Vb does not become lower than the threshold voltage Vth when the drive pulse Ton falls, and the drive pulse after the level shift. Dp itself is not output.

  By the way, in recent years, the power supply voltage of an LSI serving as a load has decreased with the miniaturization of the LSI. As a result, the allowable voltage accuracy of the output voltage Vout generated by the switching regulator is narrowed, and high-speed follow-up (responsiveness) of the power supply circuit is required even for a sudden change in load current. In order to further improve the responsiveness in the future, it is necessary to increase the oscillation frequency of the power supply circuit, that is, to shorten the high-level pulse width (on-pulse width) of the drive pulse Ton generated by the drive pulse generation circuit 12, This high level pulse width must be controlled with high accuracy.

  Further, although there is a demand for downsizing the smoothing circuit 21, in order to downsize the smoothing circuit 21, the inductor L0 must be downsized. Also in this case, it is necessary to shorten the high level pulse width of the drive pulse Dp.

  When the high level pulse width of the drive pulse Ton generated by the drive pulse generation circuit 12 is shortened by the level shift circuit 13 under the situation where the high level pulse width needs to be shortened in this way, the transistor Q0 is turned on (time). Cannot be controlled with high accuracy. As a result, the current supplied to the load cannot be controlled with high accuracy. In the worst case, the high-level pulse width of the drive pulse Dp becomes 0, the transistor Q0 cannot be turned on, and remains off. As a result, current cannot be supplied to the load.

  As described above, even when the high level pulse width of the drive pulse Ton generated by the drive pulse generation circuit 12 is shortened, the conduction time of the transistor Q0 is controlled with high accuracy and the current supplied to the load is controlled with high accuracy. It is desirable to do.

  Next, the operation of the power supply circuit 1 between time T1 and time T2 in FIG. 2 will be described. When the high level drive pulse Ton is input to the level shift circuit 13, the level shift circuit 13 shifts the level of the drive pulse Ton and outputs the high level drive pulse Dp to the gate of the transistor Q0. Then, the transistor Q0 is turned on, and the voltage Vlm at the LM point (node N1) changes from the ground GND or lower (about −0.7 V) to the power supply voltage Vdd. The reason why the voltage Vlm at the LM point becomes equal to or lower than the ground GND is due to the forward voltage drop of the diode D0.

  When the transistor Q0 is turned on, a current flows from the power supply Vdd to the inductor L0, and the current Il0 of the inductor L0 increases. The current Io (load current) is a time average of the current I10 and is constant. Further, the voltage Vh at the point VH is changed from the power supply voltage Vpp to “power supply Vdd + power supply voltage Vpp” by the bootstrap circuit having the diode D1 and the capacitor C1. This change will be described below.

  Charge is already stored in capacitor C1 by power supply voltage Vpp. When the transistor Q0 is turned on in this state, the connection point N1 and the connection point N2 rise to the power supply voltage Vdd, and the electrode on the side opposite to the connection point N2 of the capacitor C1 is boosted to the power supply voltage Vdd + the power supply voltage Vpp. Become. As a result, the voltage Vh at the point VH becomes the power supply voltage Vdd + the power supply voltage Vpp. Using this power supply voltage Vdd + power supply voltage Vpp as a power supply, the level shift circuit 13 generates a drive pulse Dp for conducting the transistor Q1.

  As described above, when the transistor Q0 is turned on, the current Il0 rises and the current Il0 becomes larger than the current Io. At this time, the feedback voltage Vfb that has continued to fall starts to rise.

  Next, the operation of the power supply circuit 1 between time T2 and time T3 will be described.

  When the drive pulse Dp falls and becomes low level, the transistor Q0 is turned off. As a result, the power supply voltage Vdd is not applied to the connection point N1, the voltage Vlm at the LM point changes from the power supply voltage Vdd to the ground GND or lower, and the diode D0 is turned on. As a result, the current IL0 of the inductor L0 continues to flow through the diode D0. However, when the transistor Q0 is turned off, no current flows from the power supply voltage Vdd to the inductor L0, and the current IL0 of the inductor L0 decreases. At this time, the electric charge accumulated in the capacitor C0 is supplied to the load 23. In addition, charges are supplied to and stored in the capacitor C1 by the power supply voltage Vpp. At this time, the voltage Vh at the point VH changes to the power supply voltage Vpp.

  When the feedback voltage Vfb that has risen becomes larger than the reference voltage Vref, the comparator 11 outputs a low level comparison signal Cmp.

  Next, the operation of the power supply circuit 1 between time T3 and time T4 will be described.

  When the comparator 11 outputs the low level comparison signal Cmp, the drive pulse generation circuit 12 outputs the low level drive pulse Ton while the comparison signal Cmp is at the low level as described above. The level shift circuit 13 outputs the drive pulse Ton as a boosted drive pulse Dp.

  As described above, when the transistor Q0 is turned off, the current IL0 decreases and becomes smaller than the current Io. At this time, the feedback voltage Vfb that has continued to rise turns down, and the feedback voltage Vfb becomes smaller than the reference voltage Vref. Then, the comparator 11 outputs a high level comparison signal Cmp.

By repeating these series of operations, the power supply circuit 1 can stably control the output voltage Vout to the reference voltage Vref × (R 0 + R 1 ) / R 1 .

  As described with reference to FIGS. 1 to 5, when the level shift circuit 13 level-shifts the high-level drive pulse Ton output from the pulse generation circuit 12, the high-level pulse width of the output drive pulse Dp is short. Become. More specifically, the high level pulse width W1 of the drive pulse Ton output from the pulse generation circuit 12 is defined as the time for turning on the transistor Q0, and the low level pulse width W3 of the drive pulse Ton is set to turn off the transistor Q0. It is defined as the time to do. However, the level shift circuit 13 shortens the time for turning on the transistor Q0. As a result, the conduction time of the transistor Q0 cannot be controlled with high accuracy, and the current supplied to the load cannot be controlled with high accuracy. In the worst case, the high level pulse width becomes 0, the transistor Q0 cannot be made conductive, and it does not function as a power supply circuit.

  Therefore, in the power supply circuit of the first embodiment, even if the switching regulator 10 described in FIG. 1 is improved and the high-level pulse width of the drive pulse output from the pulse generation circuit 12 is shortened, the high-side transistor Q0 The conduction time is controlled with high accuracy (accurate) so that the current supplied to the load can be controlled with high accuracy.

(First embodiment)
FIG. 6 is a diagram illustrating the power supply circuit 6 according to the first embodiment. The power supply circuit 6 of FIG. 6 differs from the switching regulator 10 and the smoothing circuit 21 of the power supply circuit 1 of FIG. 1 in the configuration of the switching regulator 60 and the smoothing circuit 21 ′. Other configurations are the same as those of the power supply circuit 1 described with reference to FIG. 1, and therefore, in FIG.

  The switching regulator 60 includes a comparator (CMP) 61, a level shift circuit (LS) 62 that outputs a high voltage comparison signal Ls by increasing the voltage level of the comparison signal Cmp, and a high voltage comparison output by the level shift circuit 62. The conduction of the transistor Q0 provided between the driving pulse generation circuit (DPG) 63 for generating the driving pulse Dp for driving the gate of the transistor Q0 (first transistor) based on the signal Ls and the transistor Q0 and a reference power source, for example, GND. And a diode D0 (switching element) whose conduction state changes depending on the state. As is clear from FIG. 6, a level shift circuit 62 is provided after the comparator 61, a drive pulse generation circuit 63 is provided after the level shift circuit 62, and the drive pulse generation circuit 63 outputs the transistor Q0. Driven by the driving pulse Dp.

  The comparator 61 is a comparator having the same function as the comparator 11 of FIG. 1, compares the feedback voltage Vfb with the reference voltage Vref, generates a comparison signal Cmp, and outputs the comparison signal Cmp to the level shift circuit 62. The feedback voltage Vfb is a voltage obtained by dividing the output voltage Vout by the voltage dividing circuit 22. The output voltage Vout is a voltage obtained by smoothing the voltage at the connection point N1 between the diode D0 and the transistor Q0 by the smoothing circuit 21 '. That is, the feedback voltage Vfb is a voltage obtained by smoothing the output voltage at the connection point N1 through the smoothing circuit 21 'and further dividing the voltage by the voltage dividing circuit 22. The output voltage Vout of the smoothing circuit 21 ′ may be fed back to the comparator 61 as it is without being divided by the voltage dividing circuit 22.

  In the level shift circuit 62, as described with reference to FIGS. 3 and 4, the low-side input power supply terminal is connected to the power supply for generating the voltage Vref, and the output power supply terminal is connected to the ground GND. The high-side input power supply terminal is connected to the VH point, and the output power supply terminal is connected to the connection point N4. As described with reference to FIG. 2, “power supply voltage Vdd + power supply voltage Vpp” is supplied to the level shift circuit 62 from the point VH. Then, the level shift circuit 62 increases the voltage level of the comparison signal Cmp output from the comparator 61 by the supplied “power supply voltage Vdd + power supply voltage Vpp”, and supplies the high voltage comparison signal Ls to the drive pulse generation circuit 63. Output.

  The drive pulse generation circuit 63 is a circuit having the same function as the drive pulse generation circuit of FIG. 1, but the input power supply terminal is connected to the connection point N3 and the output power supply terminal is connected to the connection point N4. That is, the drive pulse generation circuit 63 is provided between a connection point N3 between the diode D1 and the capacitor C1 and a connection point N4 on the source side of the transistor Q0. The drive pulse generation circuit 63 operates by “power supply voltage Vdd + power supply voltage Vpp” supplied from the connection point N3.

  The drive pulse generation circuit 63 uses the rising edge of the high voltage comparison signal Ls output from the level shift circuit 62 as a trigger to set the drive pulse Dp to a high level that turns on the transistor Q0 for the first period, and to the gate of the transistor Q0. Output. Details of the drive pulse generation circuit 63 will be described later with reference to FIGS. 8 to 10 in the second half of the first embodiment.

  The smoothing circuit 21 'has the same configuration as the smoothing circuit 21 described in FIG. However, the parameters of the inductor L0 'and the capacitor C0' are smaller than the parameters of the inductor L0 and the capacitor C0 described in FIG. 1, and the smoothing circuit 21 'is downsized.

  Note that the smoothing circuit 21 ′ and the voltage dividing circuit 22 may be included in the switching regulator 60.

  FIG. 7 is a timing chart for explaining the operation of the power supply circuit 6 of FIG. 6, in order from the top, the comparison signal Cmp output from the comparator 61, the high voltage comparison signal Ls output from the level shift circuit 62, and the drive pulse generation. The drive pulse Dp output from the circuit 63, the on / off state of the transistor Q0, the current I10 and the output current Io of the inductor L0 ′, the feedback voltage Vfb, and the reference voltage Vref are shown.

  First, the operation of the power supply circuit 6 from time T10 to time T11 in FIG. 7 will be described. When the feedback voltage Vfb becomes lower than the reference voltage Vref, the comparator 61 outputs a high level comparison signal Cmp. In response to the rising edge of the comparison signal Cmp, the level shift circuit 62 shifts the level of the high voltage comparison signal Ls to rise from the voltage Vdd to “power supply voltage Vdd + power supply voltage Vpp”.

  Next, the operation of the power supply circuit 6 between time T11 and time T12 will be described. When the high level high voltage comparison signal Ls is input to the drive pulse generation circuit 63, the drive pulse generation circuit 63 uses the rising edge of the high voltage comparison signal Ls as a trigger to generate the high level drive pulse Dp for a certain time as a transistor. Output to the gate of Q0. Then, the transistor Q0 is turned on, a current flows from the power supply voltage Vdd to the inductor L0 ', the current Il0 of the inductor L0' increases, and the current Il0 becomes larger than the current Io. At this time, the feedback voltage Vfb that has continued to fall starts to rise. After a certain period of time, the high level drive pulse Dp falls and the transistor Q0 is turned off. As a result, no current flows from the power supply voltage Vdd into the inductor L0 ', and the current Il0 of the inductor L0' decreases. The subsequent operation of the power supply circuit 6 between time T12 and time T14 is the same as the operation of the power supply circuit 1 described with reference to FIG.

  Since the comparison signal Cmp has a low frequency (high level pulse width and low level pulse width are long), the comparison signal Cmp is level-shifted by the level shift circuit 62 and becomes 0 even if the high level width is shortened. Absent. Further, since the drive pulse generation circuit 63 outputs a high level drive pulse Dp triggered by the rising edge of the high voltage comparison signal Ls output from the level shift circuit 62, the high level width of the high voltage comparison signal Ls is extremely high. Even if it becomes shorter, the drive pulse Dp that is at the high level for a certain time can be output to the gate of the transistor Q0. That is, the drive pulse generation circuit 63 can give the drive pulse Dp that becomes high level for a certain time without being affected by the operation of the high voltage transistor of the level shift circuit 62 to the transistor. Therefore, the high level pulse width of the drive pulse Dp does not change, and the pulse width can be controlled with high accuracy. As a result, the conduction time of the transistor Q0 can be controlled with high accuracy. The maximum value of the coil current IL0 can be accurately controlled, and the current Io supplied to the load can be controlled with high accuracy.

  Further, as described above, the smoothing circuit 21 '(inductor L0') is downsized to shorten the high level pulse width of the drive pulse Dp. As a result, the amount of increase (slope) per unit time of the current I10 becomes larger than the slope of the current I10 described with reference to FIG. 2, and it is possible to respond to a sudden change in load current at a high speed.

  Hereinafter, the drive pulse generation circuit 63 will be described with reference to FIGS.

  FIG. 8 is a diagram for explaining the drive pulse generation circuit 63, and FIGS. 9 and 10 are first and second timing charts for explaining the operation of the drive pulse generation circuit 63. The drive pulse generation circuit 63 described with reference to FIG. 8 is an example, and the present invention is not limited to this.

  The drive pulse generating circuit 63 changes the voltage Vp by turning on / off the transistor Q10, and generates high and low level drive pulses by changing the voltage Vp. In the following description, the transistor Q10 is an NMOS transistor and has a relationship of power supply voltage V1> power supply voltage V2> 0. The voltage V1 and the voltage V2 define the high level pulse width and low level pulse width of the drive pulse. The inverter (INV) 81, the comparators (CMP) 82 and 83, the OR (logical sum) circuit 84, the NAND (negative logical product) circuits 85 and 86, and the inverter (INV) 87 of the drive pulse generation circuit 63 are connected. It operates with power supplied from the point N3.

  The operation of the drive pulse generation circuit 63 will be briefly described. The drive pulse generation circuit 63 generates the drive pulse Dp by controlling the rise and fall of the output signal NandX1 of the flip-flop circuit composed of the NAND circuits 85 and 86 based on the levels of the comparison signals Cmp, CmpX1 and CmpX2. To do.

  The operation of the drive pulse generation circuit 63 from time T20 to time T21 in FIG. 9 will be described. At this time, it is assumed that the voltage Vp is 0 V in a state where no charge is accumulated in the capacitor C2. The comparator 82 outputs a high level comparison signal CmpX1 to the NAND circuit 85, and the comparator 83 outputs a low level comparison signal CmpX2 to the OR circuit 84. The OR circuit 84 outputs a high-level signal OR, the NAND circuit 85 outputs a high-level signal NNAndX1, and the NAND circuit 86 outputs a low-level signal NNAndX2.

  Therefore, when the comparison signal Cmp rises, the inverter 81 outputs the inverted signal Inv1. As a result, the OR circuit 84 outputs a low-level signal OR to the NAND circuit 86, and the output signal NAndX2 of the NAND circuit 86 becomes high level. As a result, the NAND circuit 85 outputs a low-level signal NandX1 to the inverter 87 and the transistor Q10. As a result, the inverter 87 outputs a high level drive pulse Dp. In this way, the drive pulse Dp rises simultaneously with the comparison signal Cmp rising. The transistor Q10 is turned off by the low level signal NandX1. As a result, the current Ix flows into the capacitor C2, charges are accumulated in the capacitor C2, and the voltage Vp increases.

  Next, the operation of the drive pulse generation circuit 63 between time T21 and time T22, that is, when the voltage Vp is between the voltage V2 and the voltage V1, will be described. At this time, the voltage Vp rises and becomes equal to or higher than the voltage V2 due to the current Ix flowing into the capacitor C2. Then, the comparator 83 outputs the high level comparison signal CmpX2 to the OR circuit 84, and the OR circuit 84 outputs the high level signal OR to the NAND circuit 86, but the levels of the signals NAndX1 and NAndX2 do not change. . Therefore, the drive pulse Dp remains at the high level, the transistor Q10 remains in the off state, and the voltage Vp continues to rise.

  Next, the operation of the drive pulse generation circuit 63 from time T22 to time T23, that is, until the voltage Vp drops below the voltage V1 and reaches the voltage V1 again will be described. When the voltage Vp rises and exceeds the voltage V1, the comparator 82 outputs a low level comparison signal CmpX1 to the NAND circuit 85. As a result, the NAND circuit 85 outputs a high-level signal NAndX1. Then, the drive pulse Dp falls and goes to a low level, and the signal NAndX2 also goes to a low level. Further, the transistor Q10 is turned on by the high level signal NandX1. When the transistor Q10 is turned on, the charge stored in the capacitor C2 is gradually released and the voltage Vp decreases.

  Next, the operation of the drive pulse generation circuit 63 between time T23 and time T24, that is, when the voltage Vp is between the voltage V1 and the voltage V2, will be described. Here, it is assumed that the comparison signal Cmp falls and becomes low level at time T24. When the comparison signal Cmp falls and goes to a low level, the high-level inverted signal Inv1 is input to the OR circuit 84. The OR circuit 84 outputs the high level signal OR as it is. Further, the NAND circuit 86 performs a NAND operation on the high level signal NAndX1 and the high level signal OR, and continues to output the low level signal NAndX2. Similarly, the NAND circuit 85 continues to output the high level signal NAndX1. Accordingly, the transistor Q10 continues to be on, and the voltage Vp drops to 0V. As a result, the drive pulse generation circuit 63 continues to output the low level drive pulse Dp.

  The high level pulse width (W6) of the drive pulse Dp described above is represented by (capacitance C × voltage V1) / current Ix, where C is the capacitance of the capacitor C2. As described above, the drive pulse generation circuit 63 continues to output the high-level drive pulse Dp for a certain time (width W6) by raising the drive pulse Dp at the same time when the comparison signal Cmp rises. Then, due to this drive pulse Dp, the feedback voltage Vfb becomes larger than the reference voltage Vref and the comparison signal Cmp falls, and at the same time, the drive pulse Dp falls to output a low level drive pulse Dp.

  When the required current of the load 23 is heavy, that is, the load is heavy, the feedback voltage Vfb may not be greater than the reference voltage Vref and the comparison signal Cmp may not fall with a one-shot high level drive pulse. In this case, as will be described with reference to FIG. 10, the drive pulse generation circuit 63 generates the high level drive pulse Dp again.

  The operation of the drive pulse generation circuit 63 in this case will be described with reference to FIG.

  The operation of the drive pulse generation circuit 63 between time T30 and time T33 is the same as that in FIG.

  The operation of the drive pulse generation circuit 63 between time T33 and time T34, that is, when the voltage Vp is between the voltage V1 and the voltage V2, will be described. The comparator 82 outputs the high level comparison signal CmpX1 to the NAND circuit 85. However, since the signal NAndX2 remains at the low level, the signal NAndX1 maintains the high level state, and the transistor Q10 remains on. As a result, the voltage Vp decreases and reaches the voltage V2.

  Next, the operation of the drive pulse generation circuit 63 between time T34 and time T35, that is, when the voltage Vp is between the voltage V2 and the voltage 0 will be described. When the voltage Vp becomes the voltage V2, the comparator 83 outputs a low level comparison signal CmpX2 to the OR circuit 84. The OR circuit 84 calculates the logical sum of the low level inversion signal Inv1 and the low level comparison signal CmpX2, and outputs the low level signal OR to the NAND circuit 86. Then, the NAND circuit 86 outputs a high level signal NAndX2. Then, the NAND circuit 85 outputs a low level signal NandX1. As a result, the drive pulse Dp rises and a high level drive pulse Dp is output. Further, the transistor Q10 is turned off. Thereafter, until the feedback voltage Vfb becomes higher than the reference voltage Vref and the comparison signal Cmp falls, the drive pulse generation circuit 63 generates a drive pulse Dp having a constant high level pulse width from time T30. The operation at time T35 is repeated.

  The configuration of the drive pulse generation circuit described above is an example, and various other configurations can be employed.

(Second Embodiment)
In the power supply circuit 6 of FIG. 6, the diode D0 is used as a switching element for reflux. However, when a diode is used, power loss occurs due to a forward voltage drop of the diode. Therefore, a transistor is used as a switching element instead of the diode D0.

  FIG. 11 is an explanatory diagram of the power supply circuit 9 using the transistor Q20 (second transistor) as a switching element.

  The switching regulator 110 includes a level shift circuit (LS) 111, a drive pulse generation circuit (DPG) 112, an inverter (INV) 113, and a transistor Q20 functioning as a switching element, in addition to the switching regulator 60 of FIG. Have. Since the other configuration is the same as that of the power supply circuit 6 described with reference to FIG. 6, in FIG. 11, the same reference numerals are given to the portions corresponding to those in FIG.

  The transistor Q20 is an NMOS transistor like the transistor Q0. The transistor Q20 is turned on when the transistor Q0 is turned off, and releases the magnetic energy accumulated in the inductor L0 'of the smoothing circuit 21' as a current.

  The level shift circuit 111 on the low side has the same configuration as the level shift circuit 62 on the high side, but is connected to the power supply voltage Vbias, and the comparison signal Cmp output from the comparator 61 is like the level shift circuit 62. It is not a high voltage comparison signal. The level shift circuit 111 outputs the comparison signal Cmp to the drive pulse generation circuit 112 as the comparison signal Ls1 without level shifting. The level shift circuit 111 has a delay characteristic equivalent to that of the level shift circuit 62 in order to match the timing at which the transistor Q0 is turned on / off and the timing at which the transistor Q20 is turned on / off.

  The drive pulse generation circuit 112 is a circuit having the same function as the drive pulse generation circuit 63 of FIG. 6, generates a high level drive pulse Ton1 for a predetermined time at the rising edge of the comparison signal Ls1, and outputs the drive pulse Ton1 to the inverter 113. That is, the drive pulse generation circuit 112 generates the drive pulse Ton1 that drives the gate of the transistor Q20 based on the comparison signal Ls1.

  The inverter 113 outputs an inverted pulse Dp1 of the drive pulse Ton1 output from the drive pulse generation circuit 112 to the gate of the transistor Q20.

  FIG. 12 is a timing chart for explaining the operation of the power supply circuit 9 of FIG. 11. From the top, the comparison signal Cmp output from the comparator 61, the high voltage comparison signal Ls output from the level shift circuit 62, and drive pulse generation are shown. The drive pulse Dp output from the circuit 63, the ON / OFF state of the transistor Q0, the comparison signal Ls1 output from the level shift circuit 111, the drive pulse Ton output from the drive pulse generation circuit 112, the Dp1 output from the inverter 113, and the transistor Q20 Indicates the on state and off state.

  First, the reason why the level shift circuit 111 is provided will be described. The transistor Q20 is provided on the low side, and it is not necessary to provide the level shift circuit 111 to increase the voltage level of the drive pulse for driving the transistor Q20. As described above, when the transistor Q0 is turned off, the transistor Q20 is turned on, and the magnetic energy accumulated in the inductor L0 'of the smoothing circuit 21' must be discharged as a current. For this purpose, the timing at which the transistor Q0 is turned on / off must coincide with the timing at which the transistor Q20 is turned on / off. However, the level shift circuit 62 on the high side shifts the level of the comparison signal Cmp of the comparator 61 and outputs the signal Ls, but the output timing of the signal Ls is delayed for a certain time as described with reference to FIG. Therefore, a level shift circuit 111 is provided between the comparator 61 and the drive pulse generation circuit 112 so that the output timing of the drive pulse Dp of the high side drive pulse generation circuit 63 and the drive of the low side drive pulse generation circuit 112 are driven. The output timing of the pulse Ton1 is matched. In this way, the level shift circuit 111 is caused to function as a delay circuit.

  As a result, as shown from time T40 to time T41 and from time T41 to time T42, the timing at which the transistor Q10 is turned on / off coincides with the timing at which the transistor Q20 is turned on / off. Although the drive pulse Ton1 passes through the inverter 113, the inverter 113 usually has a simple configuration including one PMOS transistor and one NMOS transistor, so that the delay due to the inverter 113 can be ignored. By doing so, the transistor Q0 is turned off and at the same time the transistor Q20 is turned on, and the magnetic energy accumulated in the inductor L0 'of the smoothing circuit 21' is released as a current. Other operations are the same as those in FIG.

  As described above, the power loss due to the forward voltage drop of the diode is eliminated by replacing the switching element from the diode to the transistor.

  The above is summarized as follows.

(Appendix 1)
A first transistor connected to a high potential power source;
A switching element provided between the first transistor and a reference power supply, wherein the conduction state changes according to the conduction state of the first transistor;
A comparator that compares a voltage obtained by feeding back an output voltage at a connection point between the first transistor and the switching element with a reference voltage to generate a comparison signal;
A level shift circuit for increasing the voltage level of the comparison signal and outputting a high voltage comparison signal;
A switching regulator having a driving pulse generating circuit for generating a driving pulse for driving the gate of the first transistor based on the high voltage comparison signal;

(Appendix 2)
In Appendix 1,
When the high voltage comparison signal is input from the level shift circuit, the drive pulse generation circuit generates a drive pulse that makes the first transistor conductive for a first period.

(Appendix 3)
In Appendix 1 or 2,
Furthermore, the switching regulator which has the said smoothing circuit provided between the said connection point and load.

(Appendix 4)
In any one of appendices 1-3
And a voltage dividing circuit provided between a smoothing circuit for smoothing the output voltage and a load connected to the output of the smoothing circuit. The voltage dividing circuit is smoothed by the smoothing circuit. A switching regulator that divides the generated voltage and outputs the divided voltage as feedback to the comparator.

(Appendix 5)
In any one of appendices 1-4
The switching regulator is a switching regulator that is turned off when the first transistor is turned on and turned on when the first transistor is turned off.

(Appendix 6)
In Appendix 5,
The switching element is a switching regulator in which a cathode is a diode connected to the connection point.

(Appendix 7)
In Appendix 5, the switching element is a second transistor,
Furthermore, a switching regulator having a drive pulse generation circuit that generates a drive pulse for driving the gate of the second transistor based on the comparison signal output from the comparator.

(Appendix 8)
In Appendix 7,
Furthermore, a switching regulator having a delay circuit between the comparator and the drive pulse generation circuit.

1, 6, 9 ... power supply circuit,
10, 60, 110 ... switching regulator,
11, 61, 82, 83 ... comparator (CMP),
12, 63, 112... Drive pulse generation circuit (DPG),
13, 62, 111... Level shift circuit (LS),
21 ... smoothing circuit,
22 ... voltage divider circuit,
23 ... Load,
81, 87, 113 ... inverter (INV),
84. OR circuit (OR),
85, 86 ... NAND circuit (NAND),
L0, L0 '... inductor,
C0, C0 ′, C1, C2... Capacitors
D0, D1 ... diodes,
Q0 to Q8, Q10, Q20 ... transistor,
R 0 , R 1 ... resistance,
Ix ... Current

Claims (5)

A first transistor connected to a high potential power source;
A switching element provided between the first transistor and a reference power supply, wherein the conduction state changes according to the conduction state of the first transistor;
A comparator that compares a voltage obtained by feeding back an output voltage based on a voltage at a connection point between the first transistor and the switching element and a reference voltage to generate a comparison signal;
Based on the comparison signal, a level shift circuit for outputting a high voltage comparison signal varying between the voltage value of the high potential power supply and the first voltage value higher than the voltage value of the high potential power supply,
As a trigger a rise of the high voltage comparison signal, the first voltage value to generate a first drive pulse varies between the voltage value of the high potential power supply, said first said first drive pulse And a first drive pulse generation circuit that outputs to the gate of the transistor . In claim 1,
The first drive pulse generating circuit, when the high voltage comparison signal from the level shift circuit is inputted, switching for generating the first drive pulse to said first transistor in the first period conductive state regulator. In claim 1 or 2,
And a voltage dividing circuit provided between a smoothing circuit for smoothing the output voltage and a load connected to the output of the smoothing circuit. The voltage dividing circuit is smoothed by the smoothing circuit. A switching regulator that divides the generated voltage and outputs the divided voltage as feedback to the comparator. In any one of Claims 1-3,
The switching regulator is a switching regulator that is turned off when the first transistor is turned on and turned on when the first transistor is turned off. In Claim 4, The said switching element is a 2nd transistor,
Furthermore, the rise of the pre-Symbol ratio No.較信as a trigger to generate a second driving pulse, switching with a second drive pulse generating circuit for outputting the second driving pulse to the gate of said second transistor regulator.

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