JP5682096B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having high speed, low loss, and soft switching characteristics, and a method for manufacturing the same.

  As power semiconductor devices, there are diodes of a withstand voltage class such as 600V, 1200V or 1700V, IGBTs (insulated gate bipolar transistors), and the like. Recently, the characteristics of these devices have been improved. Power semiconductor devices are used in high-efficiency and power-saving power converters such as converters and inverters, and are indispensable for controlling rotary motors and servo motors. Such power control devices are required to have characteristics such as low loss and power saving, high speed and high efficiency, and environmental friendliness, that is, no adverse effects on the surroundings.

  In response to such a demand, a trench gate type IGBT having a trench gate structure has been developed (see, for example, Patent Document 1). In the trench gate type IGBT, carriers accumulated in the high-resistance base layer can be increased when the trench gate type IGBT is turned on, so that the on-voltage can be lowered. In addition, as a method for manufacturing an IGBT, a conventional semiconductor substrate (for example, a silicon wafer) is thinned by grinding or the like, and then an element is ion-implanted at a predetermined concentration from the ground surface side, and a heat treatment is performed. A method for manufacturing an IGBT with low static loss is known (see, for example, Patent Document 2). In recent years, the development and manufacture of devices by such low-cost methods are becoming mainstream.

  In addition, in a planar gate type IGBT, a configuration in which a gate electrode is embedded in a semiconductor substrate and a SIMOX (Separation by IMplanted Oxygen) configuration in which an oxide film is embedded in a semiconductor substrate are proposed (for example, see Patent Document 3). ). In the planar gate type IGBT having such a configuration, the loss is reduced by accumulating carriers on the emitter electrode side. Further, an IGBT has been proposed in which a trench structure and a structure in which a gate electrode is embedded in a semiconductor substrate are combined, and a channel region is formed on the upper surface of the trench in which the gate electrode is embedded (see, for example, Patent Document 4). .

  Further, after forming an opening by patterning an oxide film on a semiconductor substrate, a single crystal semiconductor layer is grown from the opening to the oxide film by epitaxial growth, and then the single crystal semiconductor layer is planarized A chemical mechanical polishing (Chemical Mechanical Polish, hereinafter abbreviated as CMP) is performed to obtain a predetermined thickness, a base region and a source region are formed in the single crystal semiconductor layer, and an oxide film is interposed on the single crystal semiconductor layer. A manufacturing method for forming a gate electrode has been filed as Japanese Patent Application No. 2007-103387.

  On the other hand, a method has been proposed in which impurity ions are implanted into the back surface of the substrate and activated by combining laser annealing using a pulse laser, or laser annealing and electric furnace annealing (for example, Patent Document 5). reference.). Regarding laser annealing, the first laser beam and the second laser beam having a different wavelength are used to control at least one of the irradiation intensity and the irradiation time on the substrate, so that the substrate or the film on the substrate can be controlled. A method for controlling the temperature distribution in the depth direction has been proposed (see, for example, Patent Document 6). The thin film layer of polycrystalline silicon on the glass substrate is modified to be crystalline by irradiating the two-stage pulse laser so that the energy density of the second pulse is smaller than that of the first pulse. Has been proposed (see, for example, Patent Document 7).

JP-A-5-243561 (paragraphs [0005] to [0009]) Japanese translation of PCT publication No. 2002-52085 (paragraphs [0060] to [0063]) JP 2006-237553 A (paragraphs [0067] to [0070], [0117] to [0122]) JP 2007-43028 A (paragraphs [0031] to [0034]) JP 2003-59856 A (paragraph [0006]) International Publication No. 2007/015388 Pamphlet (Summary Section) JP 2005-327865 A

  However, in the configuration in which the gate electrode is embedded in the semiconductor substrate disclosed in Patent Document 3, it is necessary to form a trench reaching the gate electrode and fill the trench with polycrystalline silicon in order to draw the gate electrode to the surface of the device. Therefore, there is a problem that the manufacturing process is complicated and the manufacturing cost is increased. In addition, since the contact resistance between the gate electrode embedded in the semiconductor substrate and the polycrystalline silicon for extracting the gate electrode varies, there is a problem that the yield of gate breakdown voltage is not improved. Furthermore, since it is necessary to form an inversion layer along the three sides of the gate electrode, there is a problem that electrons are not easily injected into the drift layer.

In addition, there is a silicon layer on which a base layer and an emitter layer are formed above the buried gate electrode, and the silicon layer is formed of polycrystalline silicon. Immediately after the growth of the polycrystalline silicon, an oxidation process for forming a gate oxide film is performed. Due to the crystal grain boundaries and defects of this polycrystalline silicon, interface defects and levels are formed between the gate oxide film and the mobility of the inversion layer is reduced to 1/5 (about 200 cm ² / (Vs)). In some cases, it is difficult to obtain a desired low loss property.

  Further, in the configuration disclosed in Patent Document 4, since it is necessary to form a trench structure, the manufacturing cost is increased accordingly. Patent Document 4 describes that a technique for recovering the carrier mobility of polycrystalline silicon by laser annealing has been developed, but does not disclose the laser light irradiation conditions. Further, Patent Document 5 and Patent Document 6 do not describe recovery of crystallinity and characteristics of polycrystalline silicon grown on the substrate surface by laser irradiation.

  Further, the planarization by CMP polishing of the single crystal semiconductor layer by epitaxial growth described in the prior application has a fear of affecting the electric characteristics. This is because the allowable range of the thickness after planarization of the single crystal semiconductor layer is an extremely thin and narrow range of 0.8 μm ± 0.1 μm, and thus an extremely high planarization technique is required. For example, in the case where the thickness after flattening is 0.75 μm ± 0.23 μm and an element having a withstand voltage of 1200 V is created, the variation in withstand voltage is extremely wide as 540 V to 1410 V. In addition, the gate threshold value may be as wide as 6.1 V to 7.9 V, and a short-circuit withstand value of 15 μs or less may occur.

  Further, when the method disclosed in Patent Document 7 is applied to a configuration in which a polycrystalline silicon thin film layer is formed on a silicon substrate, the crystallinity of the polycrystalline silicon does not sufficiently recover to the interface with the silicon substrate. It was found that not only a sufficient carrier mobility could not be obtained, but also the leakage current at the time of off increased. Therefore, when the energy density of the pulse laser is simply increased in order to sufficiently recover the crystallinity of the polycrystalline silicon, ablation occurs, thereby deteriorating the characteristics of a device such as a thin film transistor.

  An object of the present invention is to provide an inexpensive semiconductor device having high speed, low loss, and soft switching characteristics in order to solve the above-described problems caused by the prior art. Another object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture a semiconductor device having high speed, low loss, and soft switching characteristics at low cost.

In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes an insulating layer selectively embedded below a first main surface of a first conductivity type semiconductor substrate, and an insulating layer formed on the insulating layer. A second conductivity type base region provided between and in contact with the first main surface; a first conductivity type source region selectively provided in the second conductivity type base region; and the first conductivity A gate insulating film covering a surface of the second conductive type base region sandwiched between the type source region and the first conductive type semiconductor substrate, a gate electrode provided on the gate insulating film, and the second conductive type An emitter electrode in contact with the base region and the first conductivity type source region, a second conductivity type collector layer provided on the second main surface of the first conductivity type semiconductor substrate, and in contact with the second conductivity type collector layer A collector electrode, and the emitter electrode However, only the gate insulating film and the interlayer insulating film that covers the gate electrode are present as insulating films in portions that are in contact with the second conductive type base region and the first conductive type source region, and the insulating layer is provided. The first main surface in the formed portion protrudes outside the first main surface in the portion sandwiched between the adjacent insulating layers, and the width of the protruding portion is larger than the width of the insulating layer. It is narrow, and the gate insulating film, the gate electrode, and the interlayer insulating film are uneven . In the semiconductor device according to the present invention as set forth in the invention described above, the thickness of the second conductivity type base region is 0.8 ± 0.1 μm.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: an insulating layer selectively embedded below a first main surface of a first conductivity type semiconductor substrate; and the first main surface in contact with the insulating layer. A second conductive type base region provided between the first conductive type source region, a first conductive type source region selectively provided in the second conductive type base region, the first conductive type source region, and the first conductive type. An uneven gate insulating film covering the surface of the second conductivity type base region sandwiched between the type semiconductor substrates, an uneven gate electrode provided on the gate insulating film, and the second conductivity type base region And an emitter electrode in contact with the first conductivity type source region, a second conductivity type collector layer provided on the second main surface of the first conductivity type semiconductor substrate, and a collector electrode in contact with the second conductivity type collector layer A semiconductor device for manufacturing the semiconductor device In the device manufacturing method, an insulating layer forming step of selectively forming the insulating layer on a main surface of a starting substrate made of a first conductivity type semiconductor, and an opening portion of the insulating layer formed by the insulating layer forming step A single crystal growth step of epitaxially growing a single crystal semiconductor layer that covers an opening of the insulating layer and that extends on an end of the insulating layer on the exposed main surface of the starting substrate; and the on the exposed part after single crystal growth process, the the upper surface of the single crystal semiconductor layer is protruded outwardly, the polycrystalline semiconductor as the width of the projecting portion is narrower than the width of said insulating layer A polycrystalline growth step for growing a layer; defects introduced into the single crystal semiconductor layer grown in the single crystal growth step; defects introduced into the polycrystalline semiconductor layer grown in the polycrystalline growth step; As well as the above A recovery step of recovering defects between the crystal semiconductor layer, the single crystal semiconductor layer, and the starting substrate, and the insulating layer forming step, the single crystal growth step, the polycrystal growth step, and the recovery step in order Then, the first conductive semiconductor substrate in which the insulating layer is selectively embedded under the first main surface is manufactured, and the semiconductor device having the above structure is manufactured using the first conductive semiconductor substrate. It is characterized by manufacturing.

A method of manufacturing a semiconductor device according to this invention is the invention described above, the in the recovery step is carried out at a temperature of 600 ° C. or higher 1000 ° C. or less, and performing the following heat treatment for 30 minutes or more 10 hours.

A method of manufacturing a semiconductor device according to this invention is the invention described above, the in the recovery step, wherein the single crystal semiconductor layer grown in a single crystal growth process, and said polycrystalline grown polycrystalline growth step The semiconductor layer is irradiated with laser light.

A method of manufacturing a semiconductor device according to this invention is the invention described above, by using a plurality of laser irradiation device for irradiating a pulsed laser, continuously irradiating a plurality of pulsed laser beam for each illumination area It is characterized by that.

  According to the semiconductor device of the present invention, in the planar gate type semiconductor device, the portion where the emitter electrode is in contact with the second conductivity type base region and the first conductivity type source region is subjected to CMP (Chemical Mechanical Polishing) or the like. There is no insulating film to be a polishing stopper film when polishing. This is because the semiconductor layer to be the second conductivity type base region grows in a flat surface state on the insulating layer buried under the first main surface of the first conductivity type semiconductor substrate. This is because it is not necessary to perform polishing for planarizing the surface after the growth of the layer. Further, according to the method for manufacturing a semiconductor device according to the present invention, since the polycrystalline semiconductor layer grows flat on the insulating layer on the starting substrate, polishing for flattening the surface of the polycrystalline semiconductor is not performed. That's it. Further, by performing the recovery step, the crystallinity of the semiconductor is recovered and defects are reduced or eliminated, so that sufficiently high carrier mobility can be obtained.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to obtain an inexpensive semiconductor device having high speed, low loss, and soft switching characteristics.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Configuration of semiconductor device)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the central portion of the semiconductor device is an active portion 1 through which a drift current flows, and the periphery of the active portion 1 is an edge portion 2 for securing a withstand voltage. The configuration of the active portion 1 on the first main surface side of the n semiconductor substrate 11 is as follows. The buried insulating layer 12 is selectively buried under the first main surface of the n semiconductor substrate 11. The p base region 13 is provided between the buried insulating layer 12 and the first main surface of the n semiconductor substrate 11 in contact with the buried insulating layer 12.

The n ⁺ source region 14 is selectively provided in the p base region 13. The gate insulating film 15 covers the surface of the portion of the p base region 13 sandwiched between the n ⁺ source region 14 and the n semiconductor substrate 11. The gate electrode 16 is provided on the gate insulating film 15. The gate electrode 16 and the gate insulating film 15 are covered with an interlayer insulating film 17. Emitter electrode 18 is provided on interlayer insulating film 17, and is in contact with p base region 13 and n ⁺ source region 14 in a contact hole penetrating interlayer insulating film 17.

  The configuration of the edge portion 2 on the first main surface side of the n semiconductor substrate 11 is as follows. The p guard ring region 19 is selectively provided in the surface layer of the n semiconductor substrate 11. The surfaces of the p guard ring region 19 and the n semiconductor substrate 11 are covered with an interlayer insulating film 17. The field plate 20 is provided on the interlayer insulating film 17 and is in contact with the p guard ring region 19 in a contact hole penetrating the interlayer insulating film 17. The edge portion 2 is covered with a passivation film (not shown).

The configuration on the second main surface side of the n semiconductor substrate 11 is common to the active portion 1 and the edge portion 2 and is as follows. The n ⁺ field stop layer 21 is provided at a position deeper from the second main surface of the n semiconductor substrate 11 than the p collector layer 22 and away from the above-described configuration on the first main surface side. The p collector layer 22 is provided on the surface layer of the second main surface of the n semiconductor substrate 11. The collector electrode 23 is provided on the second main surface of the n semiconductor substrate 11 in contact with the p collector layer 22.

In the above configuration, only the gate insulating film 15 and the interlayer insulating film 17 exist as insulating films in a range where the emitter electrode 18 is partially in contact with the p base region 13 and the n ⁺ source region 14. Further, only the interlayer insulating film 17 exists as an insulating film within a range where the field plate 20 is partially in contact with the p guard ring region 19. That is, in this semiconductor device, there is no insulating film serving as a polishing stopper film when the surface of the semiconductor layer on the buried insulating layer 12 where the p base region 13 is formed is polished and planarized.

(Example 1 of manufacturing method)
2 to 21 are cross-sectional views sequentially explaining Example 1 of the semiconductor device manufacturing method according to the embodiment of the present invention. Although not particularly limited, an example in which the withstand voltage class is 1200 V is shown here (the same applies to Example 2). As shown in FIG. 2, first, for example, an n-type FZ silicon substrate having a specific resistance of 60 Ωcm is prepared as the starting substrate 31. The FZ substrate is a wafer cut out from an ingot produced by a floating zone method. In place of the FZ substrate, a CZ substrate cut out from an ingot produced by the Czochralski method may be used. A screen oxide film 32 having a thickness of, for example, 1000 mm is grown on the surface of the prepared starting substrate 31.

  Next, as shown in FIG. 3, a part of the screen oxide film 32 is removed by well-known photolithography and etching. At this time, the silicon of the starting substrate 31 is exposed in the active portion with a width of about 1 μm, for example, and the silicon of the starting substrate 31 is exposed in a region other than the active portion. The area other than the active part is, for example, an area such as the edge part, the gate pad part, and the dicing line. Regarding the etching, since the opening width of the screen oxide film 32 is about 1 μm, wet etching with a chemical solution mainly containing hydrofluoric acid is desirable because it does not damage the underlying silicon. Instead of wet etching, dry etching using plasma may be performed. In that case, the etching damage surface may be recovered at a temperature of about 1000 ° C. after the etching. This is the insulating layer forming step.

Next, as shown in FIG. 4, dichlorosilane or trichlorosilane is used as the source gas, phosphine gas is used as the doping gas, and phosphorous doped with a thickness of, for example, 1000 Å or more is used to close the opening of the screen oxide film 32. The single crystal silicon layer 33 is epitaxially grown. At that time, silicon exposed to the opening of the screen oxide film 32 becomes a single crystal seed for epitaxial growth. Further, the flow rate of the phosphine gas is controlled so that the impurity concentration of phosphorus doped in the single crystal silicon layer 33 becomes 1 × 10 ¹⁶ cm ⁻³ .

  In the case of using trichlorosilane, the single crystal silicon layer 33 closes the opening of the screen oxide film 32 and then grows laterally on the screen oxide film 32 so that the surface of the single crystal silicon layer 33 becomes flat. Therefore, it is preferable. It is sufficient that the single crystal silicon layer 33 is grown on the screen oxide film 32 in the lateral direction by about 1 μm from the opening of the screen oxide film 32. This is the single crystal growth process.

Next, as shown in FIG. 5, dichlorosilane or trichlorosilane is used as the source gas, phosphine gas is used as the doping gas, and the phosphorous-doped polycrystalline silicon layer 34 has a thickness of 0.8 μm, for example, at 600 ° C. Grow. At this time, the flow rate of the phosphine gas is controlled so that the impurity concentration of phosphorus doped in the polycrystalline silicon layer 34 is 1 × 10 ¹⁶ cm ⁻³ . Since the growth rate of the polycrystalline silicon on the oxide film is 10 times or more the growth rate of the polycrystalline silicon on the single crystal silicon, the polycrystalline silicon layer 34 is substantially grown only on the screen oxide film 32. To do. Polycrystalline silicon grows extremely flat. When the inventors actually measured the thickness of the polycrystalline silicon layer 34, it was 0.80 ± 0.05 μm.

As the polycrystalline silicon layer 34 contacts the single crystal silicon layer 33 and overlaps the single crystal silicon layer 33, the screen oxide film 32 is completely embedded in the semiconductor layer. When the single crystal silicon layer 33 or the polycrystalline silicon layer 34 is grown, these semiconductor layers are made non-doped layers without supplying phosphine gas, and phosphorus ions are subsequently added to the non-doped semiconductor layers, for example, 8 × 10 8. ^The phosphorus concentration described above may be achieved by implanting at a dose of about ¹¹ cm ⁻² . This is the polycrystalline growth process.

  Next, as shown in FIG. 6, heat treatment is performed at a temperature of 600 ° C. to 1000 ° C. for 30 minutes to 10 hours. In this heat treatment, when the temperature of the heat treatment furnace reaches, for example, 700 ° C., a wafer is put in the furnace, and the temperature in the furnace is increased at a temperature increase rate of, for example, 5 ° C./min. At that time, oxygen is first mixed to grow an oxide film having a thickness of, for example, 150 mm on the wafer surface. Thereafter, for example, a nitrogen atmosphere is maintained at a predetermined temperature, for example, 900 ° C. for a predetermined time, for example, 1 hour. Thereafter, for example, the temperature in the furnace is cooled to 700 ° C. at a temperature lowering rate of 2 ° C./min, and the wafer is taken out of the furnace. In the case of heat treatment at 600 ° C. to 700 ° C., for example, the furnace may be put in and out at room temperature.

  By this heat treatment, the starting substrate, the epitaxially grown single crystal silicon layer, and the polycrystalline silicon layer on the screen oxide film are integrated. Further, the crystal grain boundaries and defects of the polycrystalline silicon layer on the screen oxide film are recovered, and the polycrystalline silicon layer becomes single crystalline silicon. Therefore, the screen oxide film is buried in the single crystal silicon, and becomes the buried insulating layer 12. Further, the starting substrate is an n semiconductor substrate 11 in which the buried insulating layer 12 is selectively buried under the first main surface. This is the recovery process. Subsequently, using this n semiconductor substrate 11, a MOS gate structure is fabricated by a known method, for example, the following procedure.

As shown in FIG. 7, an initial oxide film 41 having a thickness of, for example, 8000 mm is grown on the first main surface of the n semiconductor substrate 11 (the main surface on the side where the buried insulating layer 12 is provided). Next, as shown in FIG. 8, a part of the initial oxide film 41 is removed by well-known photolithography and etching. At this time, silicon in the guard ring formation region of the n semiconductor substrate 11 is exposed at the edge portion, and the initial oxide film 41 is left in the active portion. Then, as shown in FIG. 9, boron ion implantation is performed with a dose of 1 × 10 ¹⁵ cm ⁻² , for example, using the initial oxide film 41 remaining on the first main surface of the n semiconductor substrate 11 as a mask.

  Next, as shown in FIG. 10, for example, drive heat treatment is performed at 1150 ° C. for 3 hours, for example, to form a p guard ring region 19 for edge termination at the edge portion. Thereafter, gate oxidation is performed to generate an oxide film 42 having a thickness of 600 to 1000 mm, for example. Next, as shown in FIG. 11, a polycrystalline silicon layer 43 for a gate electrode is grown on the entire surface. Then, as shown in FIG. 12, the oxide film 42 and part of the polycrystalline silicon layer 43 are removed by well-known photolithography and etching to form the gate insulating film 15 and the gate electrode 16.

Next, as shown in FIG. 13, using the initial oxide film 41 and the gate electrode 16 remaining on the first main surface of the n semiconductor substrate 11 as a mask, for example, boron ion implantation is performed at a dose of 2 × 10 ¹⁴ cm ^−2. I do. Next, as shown in FIG. 14, for example, drive heat treatment is performed at 1150 ° C. for 5 hours, for example, and boron is diffused to form the p base region 13. Thereby, the gate threshold is adjusted to, for example, about 7.5V.

Next, as shown in FIG. 15, arsenic ions are implanted using a resist mask, and after the resist is removed, a drive heat treatment is performed, for example, at 1100 ° C. for 30 minutes to form the n ⁺ source region 14. Next, as shown in FIG. 16, a BPSG film is formed as an interlayer insulating film 17 on the entire surface, and a part thereof is removed to open a contact hole. Thus far, the basic structure of the MOS gate and edge termination is completed.

Next, a resist is applied to the entire surface of the n semiconductor substrate 11 on the first main surface side, and a baking process is performed to protect the surface structure of the element. Then, the second main surface of the n semiconductor substrate 11 is ground by a process such as back grinding and wet etching to finish the thickness of the substrate to, for example, 140 μm. Next, as shown in FIG. 17, selenium ions are implanted from the second main surface side of the n semiconductor substrate 11 at a dose of 1 × 10 ¹⁴ cm ⁻² , for example. Then, as shown in FIG. 18, for example, drive heat treatment is performed at 950 ° C. for 1 hour, for example, to form the n ⁺ field stop layer 21 from the second main surface of the n semiconductor substrate 11 to a depth of about 20 μm, for example. 17 and 18, the protective resist film on the first main surface side of the n semiconductor substrate 11 is omitted.

  Next, as shown in FIG. 19, after removing the protective resist film, an Al—Si film, for example, with a thickness of, for example, 5 μm is formed on the entire first main surface of the n semiconductor substrate 11 by, eg, sputtering. . Then, after making the Al—Si film into a desired pattern by well-known photolithography and etching, a sintering process is performed at, for example, 380 ° C. for one hour. Thereby, the emitter electrode 18 and the field plate 20 are formed.

  Next, for example, polyimide is applied to the entire surface on the first main surface side of the n semiconductor substrate 11 to remove the polyimide in the active portion, and a passivation film is formed so that the polyimide film remains on the edge portion. If no passivation film is needed, this step is omitted. Next, as shown in FIG. 20, for example, boron ion implantation is performed from the second main surface side of the n semiconductor substrate 11. Then, as shown in FIG. 21, for example, annealing is performed at 380 ° C. for 1 hour, for example, to form the p collector layer 22 on the surface layer of the second main surface of the n semiconductor substrate 11.

  Next, for example, by sputtering, the second main surface of the n semiconductor substrate 11 is coated with, for example, 2 μm thick Al—Si, for example 0.08 μm thick Ti, for example 0.7 μm thick Ni, and for example 0 A semiconductor device having the structure shown in FIG. 1 is completed by sequentially depositing Au having a thickness of 2 μm to form the collector electrode 23. Finally, dicing is performed along dicing lines (not shown) to complete individual IGBT chips.

  In Example 1, since the polycrystalline silicon layer 34 is laminated on the screen oxide film 32 as described above, the carrier mobility of the polycrystalline silicon layer 34 is lower than the carrier mobility of single crystal silicon. Is concerned. As a result of intensive studies by the present inventors, it was found that sufficiently high carrier mobility can be obtained depending on the temperature of the heat treatment performed in the recovery step, as shown in FIG. FIG. 22 is a characteristic diagram showing the relationship between the heat treatment temperature and the carrier mobility in the recovery process.

As is apparent from FIG. 22, when the heat treatment temperature is 700 ° C. or lower, the carrier mobility becomes lower than the electron mobility (1495 cm ² / Vs) in the silicon crystal at room temperature. However, it can be seen that when the heat treatment temperature is 600 ° C. or higher, the carrier mobility is almost recovered. Therefore, the heat treatment temperature may be 600 ° C. or higher. On the other hand, when the heat treatment temperature is 1100 ° C. or higher, the carrier mobility decreases again, and becomes much lower than the electron mobility in the silicon crystal at room temperature. This is because when the heat treatment temperature is 1100 ° C. or higher, the crystal grain boundaries in the polycrystalline silicon are fixed by the generated stress, and point defects and dislocations are created, so that the crystallinity is not sufficiently recovered. It is.

  Therefore, a desirable heat treatment temperature range is 600 ° C. or higher and 1000 ° C. or lower. The desirable heat treatment time is 30 minutes or more and 10 hours or less. For example, when heat treatment at 800 ° C. is performed in a 700 ° C. furnace, 20 minutes are required to raise the temperature at 5 ° C./min. It was found that when this was performed at 10 ° C./min for 10 minutes or less, defects remained due to a rapid temperature rise. In addition, if the heat retention time is 30 minutes or less, defects remain. Therefore, in order to remove defects sufficiently, the heat treatment time must be 30 minutes or longer in order to keep the heat treatment time longer than the temperature rise time and maintain a sufficient temperature rise rate. On the other hand, when the heat retention time exceeds 10 hours at 600 ° C., no defects remain. However, in order to increase the throughput of the process process, it is better that the heat retention time is short. Therefore, if the temperature is set to 600 ° C. or higher, no defects remain even if it is 10 hours or shorter. Here, the carrier mobility is such that after a thermal oxide film having a thickness of 1000 mm is grown on a bare wafer, a polycrystalline silicon layer having a thickness of 1 μm is formed thereon under the same conditions as in the polycrystalline growth process described above. It is a value calculated from the results obtained by performing a heat treatment at each temperature in increments of 100 ° C. in the range of ℃ to 1200 ° C., measuring the Hall coefficient.

  FIG. 23 shows the configuration of the Hall coefficient measurement system. This measurement system assumes a square with a side of 1 cm on the surface of the polycrystalline silicon layer, applies a voltage to two diagonal points of the four vertices of the square, and two other diagonal points. The voltage is measured.

  By the way, in the patent application filed earlier (Japanese Patent Application No. 2007-103387), the present applicant forms an oxide film on the surface of the starting substrate and grows a silicon layer so as to fill the oxide film. A method for manufacturing a semiconductor device in which the surface of a silicon layer is polished and planarized is disclosed. A semiconductor device manufactured by the manufacturing method disclosed in this Japanese Patent Application No. 2007-103387 is used as a comparative example. Hereinafter, a semiconductor device manufactured by the method of the comparative example and the above-described first embodiment (simply referred to as an embodiment). 1), the result of the comparison of characteristics will be described.

  FIG. 24 is a diagram comparing the thickness of a semiconductor layer (hereinafter referred to as a partial SOI layer, SOI: Silicon on Insulator) on the buried insulating layer between Example 1 and the comparative example. In the first embodiment, the thickness of the partial SOI layer is determined by the thickness of the polycrystalline silicon layer 34 when the polycrystalline silicon layer 34 is grown on the screen oxide film 32. In the comparative example, the thickness of the partial SOI layer is a silicon layer filling the oxide film. It depends on the amount of polishing. It is said that the allowable range of the thickness of the partial SOI layer that provides a sufficiently low loss is, for example, 0.8 ± 0.1 μm. Therefore, here, the target value of the thickness of the partial SOI layer is set to 0.8 μm.

  As shown in FIG. 24, in Example 1, since the thickness of the partial SOI layer can be suppressed to 0.81 ± 0.01 μm, a sufficiently low loss property can be obtained in all manufactured semiconductor devices. On the other hand, the thickness of the partial SOI layer of the comparative example is 0.83 ± 0.17 μm, which deviates from the allowable range. Therefore, in the comparative example, a semiconductor device with a high loss is also produced.

  FIG. 25 is a diagram in which the breakdown voltage is compared between Example 1 and the comparative example. As shown in FIG. 25, in Example 1, the breakdown voltage can be suppressed to 1410 ± 50V. This is because the thickness of the partial SOI layer in Example 1 is suppressed to the above-described 0.81 ± 0.01 μm. On the other hand, the withstand voltage of the comparative example is about 600V to 1450V. The reason why the breakdown voltage of the comparative example greatly varies is that the partial SOI layer of the comparative example has a thickness that is thinner than the target value. When the thickness of the partial SOI layer is thinner than the target value (0.8 μm), the electric field strength in the partial SOI layer becomes high, and as a result, the breakdown voltage becomes low.

  FIG. 26 is a diagram comparing threshold values in Example 1 and the comparative example. As shown in FIG. 26, in Example 1, the threshold value can be suppressed to 7.4 ± 0.1V. On the other hand, the threshold value of the comparative example is 7.2 ± 0.8V. The threshold value of the MOS gate is determined by the concentration of the p base region formed in the partial SOI layer and the capacitance of the gate insulating film. In Example 1, since the variation in the thickness of the partial SOI layer is small, there is almost no variation in the concentration of the p base region, and the variation in the gate threshold is small. In the comparative example, since the variation in the thickness of the partial SOI layer is large, the concentration in the p base region varies, and as a result, the variation in the gate threshold value increases.

  FIG. 27 is a diagram comparing the trade-off characteristics between the on-state voltage and the turn-off loss in Example 1 and the comparative example. As shown in FIG. 27, in Example 1, the on-voltage is 0.1 V lower than that of the comparative example, and the trade-off characteristics are greatly improved. This is because in Example 1, since the surface of the partial SOI layer is not polished, there is no polishing stopper film. Without the polishing stopper film, the unit cell width can be reduced by about 10%, and the cell density is increased accordingly. In the comparative example, since the surface of the partial SOI layer needs to be polished and flattened, a polishing stopper film exists.

(Example 2 of manufacturing method)
FIG. 28 is a cross-sectional view for explaining Example 2 of the semiconductor device manufacturing method according to the embodiment of the present invention. As shown in FIG. 28, Example 2 is one in which laser annealing is performed instead of heat treatment in the recovery process. The steps shown in FIGS. 2 to 5 and FIGS. 7 to 21 are the same as those in the first embodiment, and thus the duplicate description is omitted. Only the recovery process by laser annealing will be described below.

In the recovery process, for example, laser annealing is performed using two laser irradiation apparatuses of a second harmonic (YAG 2ω laser, wavelength: 532 nm) of a YAG (Yttrium Aluminum Garnet) laser. The laser irradiation conditions are not particularly limited, but are as follows, for example. For example, the irradiation energy densities of the first laser (1st pulse) and the second laser (2nd pulse) are both ² J / cm ² , so that the total laser irradiation energy density is 4 J / cm ² . For example, the delay time of the 2nd pulse with respect to the 1st pulse is set to 500 ns. Also, for example, the pulse overlap rate is set to 90% for each of the first and second units.

  By this laser annealing treatment, the starting substrate, the epitaxially grown single crystal silicon layer, and the polycrystalline silicon layer on the screen oxide film are integrated. Further, the crystal grain boundaries and defects of the polycrystalline silicon layer on the screen oxide film are recovered, and the polycrystalline silicon layer becomes single crystalline silicon. Therefore, the screen oxide film is buried in the single crystal silicon, and becomes the buried insulating layer 12. Further, the starting substrate is an n semiconductor substrate 11 in which the buried insulating layer 12 is selectively buried under the first main surface. When the laser beam is irradiated under the conditions as described above, the crystal quality can be recovered without causing ablation at the laser irradiation site.

  These laser irradiation conditions are appropriately selected so that desired characteristics can be obtained. Irradiation with a pulsed laser can be realized by blinking the light source itself, or by illuminating the laser for a desired time by opening and closing the shutter or the like, and irradiating the laser for a desired time. . Here, either may be realized. Also, instead of the YAG2ω laser, an excimer laser such as a third harmonic of a YAG laser (YAG3ω laser), YLF2ω, YVO4 (2ω), YAG3ω, YLF3ω or YVO4 (3ω), XeCl, KrF or XeF Alternatively, a semiconductor laser may be used.

  A result of comparison of characteristics between the semiconductor device manufactured by the method of Example 2 described above (simply referred to as Example 2) and the comparative example will be described. The thickness of the partial SOI layer of Example 2 is also shown in FIG. Also in Example 2, the target value of the thickness of the partial SOI layer was set to 0.8 μm. In Example 2, since the thickness of the partial SOI layer can be suppressed to 0.79 ± 0.01 μm, sufficient low loss can be obtained in all manufactured semiconductor devices.

  The breakdown voltage of Example 2 is also shown in FIG. In Example 2, the breakdown voltage can be suppressed to 1400 ± 30V. Moreover, the threshold value of Example 2 is also shown in FIG. In the second embodiment, the threshold value can be suppressed to 7.1 ± 0.1V. FIG. 29 is a graph comparing the trade-off characteristics between the on-state voltage and the turn-off loss in Example 2 and the comparative example. As shown in FIG. 29, in the second embodiment, for the same reason as in the first embodiment, the on-voltage is 0.1 V lower than that in the comparative example, and the trade-off characteristics are greatly improved. Note that FIG. 29 and FIG. 27 differ in the trade-off characteristics of the comparative example, because this is because the measurement conditions of the on-voltage and the turn-off loss are different, and there is no essential difference.

  As described above, according to the embodiment, a partial SOI layer having a desired thickness can be obtained with high accuracy. As described above, an IGBT with stable breakdown voltage and gate threshold can be obtained. In addition, the trade-off characteristics between on-voltage and turn-off loss are improved. Further, by performing the recovery process, the crystallinity of the semiconductor is recovered and defects are reduced or eliminated, so that sufficiently high carrier mobility can be obtained. Therefore, an inexpensive IGBT having high speed, low loss, and soft switching characteristics can be obtained. By using this IGBT, it is possible to obtain an IGBT module or IPM (Intelligent Power Module) taking into consideration environmental problems with low electrical loss and radiated electromagnetic noise.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions, concentrations, manufacturing conditions, and the like described in the embodiments are examples, and the present invention is not limited to these values. Further, a substrate made of a polysilicon raw material may be used as a starting substrate. Further, the withstand voltage class may be 600V, 1700V, 3300V or higher. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a power semiconductor device used for a power conversion device and the like, and are particularly suitable for an IGBT.

It is sectional drawing which shows the structure of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining Example 1 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a characteristic view which shows the relationship between the heat processing temperature and carrier mobility in a recovery process about Example 1. FIG. It is a figure which shows the structure of the measurement system of a Hall coefficient. It is the figure which compared the thickness of the semiconductor layer on a buried insulating layer by Example 1 and 2 and a comparative example. It is the figure which compared withstand pressure | voltage with Examples 1 and 2 and a comparative example. It is the figure which compared the threshold value in Example 1 and 2 and a comparative example. It is the figure which compared the trade-off characteristic of ON voltage and turn-off loss by Example 1 and a comparative example. It is sectional drawing explaining Example 2 of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is the figure which compared the trade-off characteristic of ON voltage and turn-off loss by Example 2 and a comparative example.

Explanation of symbols

11 n semiconductor substrate 12 buried insulating layer 13 p base region 14 n ⁺ source region 15 gate insulating film 16 gate electrode 17 interlayer insulating film 18 emitter electrode 22 p collector layer 23 collector electrode 31 starting substrate 32 oxide film 33 single crystal silicon layer 34 Polycrystalline silicon layer

Claims (6)

An insulating layer selectively embedded below the first main surface of the first conductivity type semiconductor substrate;
A second conductivity type base region provided between the first main surface in contact with the insulating layer;
A first conductivity type source region selectively provided in the second conductivity type base region;
A gate insulating film covering a surface of the second conductivity type base region sandwiched between the first conductivity type source region and the first conductivity type semiconductor substrate;
A gate electrode provided on the gate insulating film;
An emitter electrode in contact with the second conductivity type base region and the first conductivity type source region;
A second conductivity type collector layer provided on a second main surface of the first conductivity type semiconductor substrate;
A collector electrode in contact with the second conductivity type collector layer;
And only the gate insulating film and the interlayer insulating film covering the gate electrode are present as insulating films at portions where the emitter electrode is in contact with the second conductive type base region and the first conductive type source region. ,
The first main surface in a portion where the insulating layer is provided protrudes outward from the first main surface in a portion sandwiched between adjacent insulating layers, and the width of the protruding portion is the insulating width. A semiconductor device characterized in that the gate insulating film, the gate electrode, and the interlayer insulating film are concavo-convex, narrower than the width of the layer .   2. The semiconductor device according to claim 1, wherein a thickness of the second conductivity type base region is 0.8 ± 0.1 μm. A second conductive type base region provided between the insulating layer selectively buried below the first main surface of the first conductive type semiconductor substrate and the first main surface in contact with the insulating layer A first conductivity type source region selectively provided in the second conductivity type base region; and the second conductivity type base region sandwiched between the first conductivity type source region and the first conductivity type semiconductor substrate. A concavo-convex gate insulating film covering the surface of the gate electrode, a concavo-convex gate electrode provided on the gate insulating film, an emitter electrode in contact with the second conductive type base region and the first conductive type source region; Manufacturing of a semiconductor device for manufacturing a semiconductor device, comprising: a second conductivity type collector layer provided on a second main surface of the first conductivity type semiconductor substrate; and a collector electrode in contact with the second conductivity type collector layer. In the method
An insulating layer forming step of selectively forming the insulating layer on a main surface of a starting substrate made of a first conductivity type semiconductor;
The main surface of the starting substrate exposed in the opening portion of the insulating layer formed by the insulating layer forming step covers the opening portion of the insulating layer and extends above the end portion of the insulating layer. A single crystal growth step of epitaxially growing a crystalline semiconductor layer;
Said insulating layer, said on a portion exposed after single crystal growth process, the the upper surface of the single crystal semiconductor layer is protruded outwardly, so that the width of the projecting portion is narrower than the width of said insulating layer A polycrystalline growth step for growing a polycrystalline semiconductor layer on the substrate;
Defects introduced into the single crystal semiconductor layer grown in the single crystal growth step, defects introduced into the polycrystalline semiconductor layer grown in the polycrystalline growth step, and the polycrystalline semiconductor layer, single crystal A recovery step of recovering defects between the semiconductor layer and the starting substrate;
Including
The first conductivity in which the insulating layer is selectively embedded under the first main surface by sequentially performing the insulating layer forming step, the single crystal growth step, the polycrystalline growth step, and the recovery step. A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor substrate having a structure described above, and manufacturing the semiconductor device having the configuration described above using the first conductive semiconductor substrate.   4. The method of manufacturing a semiconductor device according to claim 3, wherein in the recovery step, heat treatment is performed at a temperature of 600 ° C. to 1000 ° C. for 30 minutes to 10 hours.   The laser beam is applied to the single crystal semiconductor layer grown in the single crystal growth step and the polycrystalline semiconductor layer grown in the polycrystal growth step in the recovery step. A method for manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 5, wherein a plurality of pulsed laser beams are continuously irradiated for each irradiation area using a plurality of laser irradiation apparatuses that irradiate a pulse laser.

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