JP5428151B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a wiring made of a conductive material containing copper and a method for manufacturing the same.

  In recent years, with the high integration of semiconductor elements and the reduction in chip size, miniaturization of wiring and multilayer wiring have been accelerated. In a logic device having such multilayer wiring, wiring delay is becoming one of the dominant factors of device signal delay. The signal delay of the device is proportional to the product of the wiring resistance value and the wiring capacitance. Therefore, to improve the wiring delay, it is important to reduce the wiring resistance value and the wiring capacitance.

  Therefore, in order to reduce the wiring resistance, it has been studied to form a wiring using copper (Cu). Hereinafter, the wiring is referred to as Cu wiring. This Cu wiring is a wiring made of a conductive material containing, for example, 90% or more of Cu, and is not limited to a wiring made purely of Cu.

The Cu wiring has difficulty in moisture resistance, and is not suitable for application to the uppermost layer wiring. Therefore, as the upper wiring of the Cu wiring, wiring (Al wiring) using a material containing aluminum (Al) having relatively excellent moisture resistance is preferable.
In order to connect the Cu wiring and the upper Al wiring, a conductive connection plug is formed between the two. This connection plug uses tungsten (W), which is a refractory metal, in consideration of wiring reliability and heat resistance.

  In order to form the connection plug (W plug), an opening, in this case, a via hole is formed in the interlayer insulating film in which the Cu wiring is embedded to expose a part of the surface of the Cu wiring. Next, a base film made of titanium nitride (TiN) or the like is formed as an adhesion layer, W is deposited through the base film, and the via hole is filled with W. Then, the W on the surface is flattened to form a W plug.

Here, when depositing W, for example, a thermal CVD method is employed. For example, the processing temperature is about 450 ° C., and the supply gas contains H ₂ gas and silane-based (SiH ₄ , Si ₂ H _6, etc.) gas in addition to WF ₆ gas for supplying W by thermal decomposition reaction What to do is used. By the silane-based gas to feed gas is added together with H ₂ gas, Si of the silane-based gas can react with WF ₆ gas, to promote the thermal decomposition reaction of WF ₆ gas.

  Instead of forming a W plug for connecting the Cu wiring and its upper layer wiring, a groove (W fuse) is formed by forming a groove as an opening in an interlayer insulating film embedding the Cu wiring and filling the groove with W. Also in the case of forming, the thermal CVD method using the same supply gas as described above is adopted.

JP 2002-43418 A

  When a W plug is formed in a connection hole on a Cu wiring, for example, a TiN film is often formed as a base film for the W plug. When the base film is formed thick, the contact resistance between the Cu wiring, the W plug and the upper layer wiring increases. Therefore, it is necessary to form the base film thin to some extent.

  However, if a thin base film is formed, sufficient step coverage cannot be obtained on the inner wall surface of the connection hole. Therefore, a step is generated on the inner wall surface of the connection hole. When W is deposited by CVD so as to fill the connection hole due to the formation of the step, the supply gas may permeate the step portion of the base film and erode the Cu surface exposed on the bottom surface of the connection hole. . This erosion is considered to be mainly caused by the silane-based gas in the supply gas. The silane-based gas has an active reaction with Cu, and Cu erosion by the silane-based gas is promoted. As Cu erosion progresses, there is a problem that the contact resistance between the Cu wiring and the W plug increases, and the electrical characteristics deteriorate.

Patent Document 1 discloses that in a W plug of Cu wiring formed by a damascene method, a base film is formed in a massive polycrystalline structure to prevent Cu diffusion. However, in this case, it is necessary to form the base film in a desired special state by increasing the nitrogen concentration. Further, for example, paragraph [0037] of the specification of Patent Document 1 states that the supply gas for forming the W plug by the CVD method is a mixed gas of WF ₆ gas and SiH ₄ gas that is a silane-based gas. It is clearly stated that the occurrence of the above problems due to the use of silane-based gas is considered inevitable.

  The present case has been made in view of the above-described problem, and a process that can be easily formed can be selected as the formation process of the base film of the connection portion using W as a material. By suppressing Cu erosion of the wiring, it is possible to suppress the contact resistance between the first wiring and the connection portion and to increase the uniformity thereof, thereby realizing a highly reliable semiconductor device. An object is to provide an apparatus and a method for manufacturing the same.

In the method of manufacturing a semiconductor device of the present case, a step of forming a first wiring containing copper above a semiconductor substrate, a step of forming an interlayer insulating film on the first wiring, and the interlayer insulating film, forming said forming an opening for exposing a portion of the surface of the first wiring, the base film made of TiN or WN on the inner wall surface of the opening, and WF _6, B ₂ H ₆ and NH ₃ Forming a first W-containing film on the base film using a first supply gas containing at least one of the above and H ₂ and not containing a silane-based gas.

  According to the present case, a process that can be easily formed can be selected as the formation process of the base film of the connection portion using W as a material, and by suppressing Cu erosion of the first wiring that is the lower-layer Cu wiring In addition, the contact resistance between the first wiring and the connection portion can be kept low, and the uniformity thereof can be enhanced, thereby realizing a highly reliable semiconductor device.

―Basic outline of the present invention―
The present inventor has recognized that the Cu erosion of the Cu wiring that occurs when forming the connection portion made of W as a material is a unique problem caused by using Cu as the wiring material.

In the present invention, at least one of B ₂ H ₆ and NH ₃ is used in place of at least a part of the silane-based gas in the supply gas of the CVD method.
B ₂ H ₆ and NH ₃ have the property of accelerating the thermal decomposition reaction of WF ₆ gas, like silane-based gases. On the other hand, unlike the silane-based gas, the reactivity with Cu is poor. Therefore, when depositing W so as to embed an opening such as a connection hole by using a supply gas containing at least one of B ₂ H ₆ and NH ₃ by a CVD method, a base film is formed thinly, Even when a step is generated on the wall surface, the supply gas is prevented from eroding the Cu surface exposed on the bottom surface of the opening. Therefore, when W is deposited so as to fill the opening, Cu movement of the Cu wiring does not occur in the deposited W, and even in a thin base film, W is distinguished from Cu of the Cu wiring by the base film. A connecting portion such as a W plug is formed.

-Specific embodiments to which the present invention is applied-
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the following embodiments, a MOS transistor is exemplified as a semiconductor device, and the configuration thereof will be described together with a manufacturing method. The semiconductor device to which the present invention is applied can be applied to any semiconductor device requiring fine wiring, such as various semiconductor memories and bipolar transistors, other than MOS transistors.

(First embodiment)
1 to 9 are schematic cross-sectional views showing the method of manufacturing the MOS transistor according to the first embodiment in the order of steps.
First, as shown in FIG. 1A, a gate electrode 4 is formed through a gate insulating film 3 in an active region determined by the element isolation structure 2 of the silicon substrate 1.
Specifically, first, an isolation groove 2a is formed in an element isolation region in the silicon substrate 1, and an insulating film, here a silicon oxide film, is formed so as to fill the isolation groove 2a. Then, the silicon oxide film is planarized by a chemical mechanical polishing (CMP) method. As described above, the STI (Shallow Trench Isolation) element isolation structure 2 filling the isolation groove 2 a is formed, and the active region is defined on the silicon substrate 1 by the element isolation structure 2.

  Next, a silicon oxide film having a thickness of about 2 nm is formed on the active region of the silicon substrate 1. Then, a polycrystalline silicon film is deposited to a thickness of about 150 nm on the silicon oxide film by a CVD method or the like. Thereafter, the polycrystalline silicon film and the silicon oxide film are processed by lithography and dry etching. Thus, the gate electrode 4 is formed on the silicon substrate 1 with the gate insulating film 3 interposed therebetween.

Subsequently, as shown in FIG. 1B, source / drain regions 5 are formed.
Specifically, an n-type impurity, here, phosphorus (P ⁺ ) is ion-implanted into the active region at a dose of about 1 × 10 ¹⁶ / cm ² and an acceleration energy of about 10 keV. Here, in the case of a p-type impurity, for example, boron (B ⁺ ) is ion-implanted with a dose amount of about 5 × 10 ¹⁵ / cm ² and an acceleration energy of about 5 keV. Thereafter, the silicon substrate 1 is annealed to activate the impurities. Thus, source / drain regions 5 are formed on both sides of the gate electrode 4 in the active region.

Subsequently, as shown in FIG. 1B, an interlayer insulating film 6 is formed, and a W plug 7 is formed in the interlayer insulating film 6.
Specifically, first, an insulating film, here a silicon oxide film, is deposited on the entire surface of the silicon substrate 1 by a CVD method or the like so as to cover the gate electrode 4 to form an interlayer insulating film 6.
Next, the interlayer insulating film 6 is processed by lithography and dry etching to form a contact hole 7a exposing a part of the surface of the source / drain region 5 (and the gate electrode 4: not shown). Then, TiN or the like is deposited by a sputtering method so as to cover the inner wall surface of the contact hole 7a, thereby forming a base film 7b serving as an adhesion layer.
Thereafter, tungsten (W) is deposited on the interlayer insulating film 6 by a CVD method or the like so as to fill the contact hole 7a through the base film 7b, and the surface of the deposited W is polished and planarized by the CMP method. . As a result, the W plug 7 filling the contact hole 7a through the base film 7b is formed.

Subsequently, as shown in FIG. 2A, an interlayer insulating film 8 is formed, and a Cu wiring 9 is formed in the interlayer insulating film 8 by a damascene method, here, a single damascene method. 2A to 9 , for convenience of illustration, only the upper structure from the interlayer insulating film 8 is illustrated, and the lower structure from the interlayer insulating film 6 and the W plug 7 is not illustrated.

More specifically, first, an insulating film, such as a silicon oxide film, is deposited to a thickness of, for example, about 500 nm by a CVD method or the like over the entire surface of the interlayer insulating film 6 so as to cover the W plug 7 for planarization. Then, the interlayer insulating film 8 is formed.
Next, an antireflection film (not shown) is formed to prevent reflection from the base. Thereafter, a photoresist is applied to the antireflection film, and this is processed by photolithography to form a wiring groove-shaped resist pattern (not shown).
Next, the antireflection film and the interlayer insulating film 8 are etched using the resist pattern as a mask, thereby forming a wiring groove 9 a that exposes the surface of the W plug 7. Thereafter, unnecessary resist patterns and antireflection films are removed.

Next, a TiN film, a Ta film or a TaN film is formed to a thickness of, for example, about 15 nm as a base film 9b serving as an adhesion layer so as to cover the inner wall surface of the wiring trench 9a, and then on the base film 9b. A plating electrode film (not shown) is formed to a thickness of about 130 nm, for example.
Next, after forming a Cu film (Cu or an alloy film thereof; the same applies hereinafter) by electroplating, the Cu film and the base film 9b are polished by CMP. As described above, the Cu wiring 9 is formed which is filled with Cu (Cu or an alloy thereof; the same shall apply hereinafter) in the wiring groove 9a through the base film 9b and is electrically connected to the W plug 7.

Subsequently, as shown in FIGS. 2B to 6A, an etching stopper film 11 and an interlayer insulating film 12 are formed, and the etching stopper film 11 and the interlayer insulating film 12 are formed by a damascene method, here, a dual damascene method. A Cu wiring portion 13 is formed on the substrate.
Specifically, first, as shown in FIG. 2B, an insulating film on the interlayer insulating film 8, here a silicon nitride film is deposited to a thickness of about 50 nm by a CVD method or the like so as to cover the Cu wiring 9, An etching stopper film 11 is formed.
Next, an insulating film, here a silicon oxide film doped with carbon (C), is deposited to a thickness of, for example, about 500 nm over the entire surface of the etching stopper film 11 to form an interlayer insulating film 12.
Next, a SiN film 31 serving as an etching mask when forming the Cu wiring portion 13 is formed to a thickness of, for example, about 100 nm by plasma CVD.

Next, as shown in FIG. 3A, after forming an antireflection film 32 on the SiN film 31, a photoresist is applied on the antireflection film 32, and this is processed by photolithography to form a wiring groove. A resist pattern 33 having a shape is formed.
Next, as shown in FIG. 3B, the antireflection film 32 and the SiN film 31 are plasma etched using the resist pattern 33 as a mask to form a wiring groove pattern 31 a in the SiN film 31. Thereafter, unnecessary resist pattern 33 and antireflection film 32 are removed.

Next, as shown in FIG. 4A, after forming an antireflection film 34 to a thickness of, for example, about 110 nm so as to embed the wiring groove pattern 31a on the SiN film 31, a photoresist is formed on the antireflection film 34. And is processed by photolithography to form a resist pattern 35 having a via hole pattern 35a.
Next, as shown in FIG. 4B, the antireflection film 34 and the SiN film 31 are plasma etched using the resist pattern 35 as a mask.

Next, as shown in FIG. 5A, the interlayer insulating film 12 is etched using the resist pattern 35 as a mask and the etching stopper film 11 as a stopper. At this time, a via hole 13a is formed in the interlayer insulating film 12, and a part of the surface of the etching stopper film 11 is exposed. Here, in a state where a part of the etching stopper film 11 is exposed but not opened (a part of the surface of the Cu wiring 9 is not exposed), the resist pattern 35 and the antireflection film 34 are lost by the etching. The resist pattern 35 and the antireflection film 34 remaining in the state may be removed.
Next, as part of a series of steps following the above etching, the interlayer insulating film 12 is etched until the etching stopper film 11 is etched and a part of the surface of the Cu wiring 9 is exposed using the SiN film 31 as a mask. A wiring trench 13 b is formed in the interlayer insulating film 12. By the series of steps, a composite groove 13c in which the wiring groove 13b and the via hole 13a are integrally formed continuously is formed.

Next, as shown in FIG. 5B, a TiN film, a Ta film, or a TaN film (for example, a film thickness of about 15 nm) is sputtered as a base film 13d serving as an adhesion layer so as to cover the inner wall surface of the composite groove 13c. Then, a plating electrode film (not shown) (for example, a film thickness of about 130 nm) is formed on the base film 13d, and a Cu film 13e is formed by electroplating.
Then, as shown in FIG. 6A, the Cu film 13e and the base film 13d are polished by the CMP method. As described above, the Cu wiring portion 13 is formed which is filled with Cu through the base film 13 d in the composite groove 13 c and is electrically connected to the Cu wiring 9. Here, the remaining SiN film 31 functions as a CMP stopper and is removed.

Subsequently, as shown in FIG. 6B, an etching stopper film 14 and an interlayer insulating film 15 are formed.
Specifically, first, an insulating film, here, a silicon nitride film is deposited on the interlayer insulating film 12 to a thickness of about 50 nm by a CVD method or the like so as to cover the Cu wiring portion 13, thereby forming an etching stopper film 14.
Next, an insulating film is deposited on the entire surface of the etching stopper film 14 by a CVD method or the like, here a silicon oxide film is deposited to a thickness of, for example, about 800 nm by a PECVD method, thereby forming an interlayer insulating film 15.

Subsequently, as shown in FIG. 7A, a via hole 16 is formed.
Specifically, using the etching stopper film 14 as a stopper, the interlayer insulating film 15 is etched until a part of the surface of the Cu wiring portion 13 is exposed. Thus, the via hole 16 is formed in the etching stopper film 14 and the interlayer insulating film 15.
Here, a part of the surface of the Cu wiring portion 13 exposed at the bottom surface of the via hole 16 is exposed to the atmosphere, and some surface oxidation occurs. This surface oxide film is removed by plasma treatment using, for example, H ₂ .

Subsequently, as shown in FIG. 7B, a base film 17 is formed.
Specifically, a TiN film is formed on the interlayer insulating film 15 so as to cover the inner wall surface of the via hole 16 as a base film 17 serving as an adhesion layer by, for example, reactive sputtering. In the present embodiment, the step coverage of the TiN film does not significantly affect the electrical characteristics, and therefore does not require control with high accuracy. Therefore, as the TiN film, it is usually necessary to secure a step coverage with a uniform film thickness of about 15 nm to 20 nm in order to prevent Cu diffusion, whereas in the present embodiment, the TiN film is not uniform as shown in the figure. The base film 17 may be formed in a film thickness. Here, the lower limit value of the film thickness is set from the viewpoint of achieving the adhesion function, and the base film 17 is formed with a film thickness of about 2 nm to 10 nm, more specifically about 3 nm to 5 nm, for example, about 5 nm. For example, a WN film may be formed as the base film 17 instead of the TiN film.

Subsequently, as shown in FIG. 8A, a tungsten (W) film 18 is deposited.
Specifically, the W film 18 is deposited as follows by, for example, a two-stage thermal CVD method.
First, as a first stage (initial stage), a first supply gas containing WF ₆ , H ₂ and B ₂ H ₆ and not containing a silane-based gas is used. The content ratio of the B ₂ H ₆ gas at the flow rate of the first supply gas is set to a lower limit from the viewpoint of ensuring sufficient acceleration efficiency of the thermal decomposition reaction of the WF ₆ gas, and from the viewpoint of suppressing abnormal uneven growth of tungsten. An upper limit may be set, for example, about 0.05% to 10%. Here, the flow rate of the first supply gas is set to about 50 sccm / 3000 sccm / 10 sccm for WF ₆ / H ₂ / B ₂ H ₆ . In addition, N2 gas is introduced as a dilution gas. The film forming temperature (substrate temperature: first temperature) is set to about 300 ° C. to 360 ° C., here about 330 ° C.
With the above requirements, a W film 18a having a film thickness of about 2 nm to 20 nm, here about 5 nm, is formed so as to cover the inner wall surface of the via hole 16 and the interlayer insulating film 15 with the base film 17.

Next, the second supply gas containing WF ₆ and H ₂ is used, and the flow rate of the second supply gas is set to about 100 sccm / 3000 sccm for WF ₆ / H ₂ . Further, the film formation temperature (substrate temperature: second temperature) is set to about 350 ° C. to 450 ° C., which is higher than the first temperature, here, about 400 ° C.
Under the above requirements, the W film 18b having a thickness of about 100 nm to 500 nm, here, about 200 nm is formed so as to embed the via hole 16 integrally with the W film 18a. As described above, the W film 18a is formed by integrating the W film 18a and the W film 18b. In FIG. 8A, for convenience, the boundary between the W film 18a and the W film 18b is indicated by a broken line.

Subsequently, as shown in FIG. 8B, a W plug 19 is formed.
Specifically, the W film 18 and the base film 17 are polished and planarized by CMP using the interlayer insulating film 15 as a stopper. Thus, the W plug 19 is formed by filling the via hole 16 with the W film 18 through the base film 17.

Here, the W plug 19 contains boron (B) of B ₂ H ₆ gas in the W film 18 a, and as a result, when viewed as a whole of the W film 18, at least with the base film 17 of the W film 18. The interface portion (W film 18a portion) contains B.

Subsequently, as shown in FIG. 9, the upper layer wiring 21 is formed.
More specifically, first, a Ti film or a TiN film is deposited as an adhesion film 21a to a thickness of, for example, about 50 nm on the interlayer insulating film 15 so as to cover the surface of the W plug 19 by sputtering.
Next, an Al film (Al or an alloy film thereof) 21b is formed on the adhesion film 21a by sputtering, for example, with a film thickness of about 1000 nm.
Next, a Ti film, a TiN film, or the like is formed as an adhesion film 21c on the Al film 21b by sputtering, for example, to a film thickness of about 50 nm.
Then, the adhesion film 21c, the Al film 21b, and the adhesion film 21a are etched into a wiring shape. Thus, the upper layer wiring 21 that is electrically connected to the W plug 19 and extends on the interlayer insulating film 15 is formed.

  Thereafter, the MOS transistor according to the present embodiment is completed through formation of a protective film, formation of a connection pad with the upper layer wiring 21, and the like.

In the present embodiment, when forming the W plug 19, first, the W film 18 a is deposited using a first supply gas containing B ₂ H ₆ so as to embed an opening such as a connection hole. With this configuration, even when the base film 17 is formed thin and a step is generated on the inner wall surface of the via hole 17, the supply gas is prevented from eroding the Cu surface exposed on the bottom surface of the via hole 17. Therefore, when the W film 18 is deposited so as to embed the via hole 17, the Cu movement of the Cu wiring portion 13 does not occur in the deposited W film 18. A W plug 19 is formed in a state of being distinct from Cu of the wiring portion 13.

  Therefore, according to the present embodiment, a process that can be easily formed can be selected as the formation process of the base film 17 of the W plug 19, and Cu wiring is suppressed by suppressing Cu erosion of the underlying Cu wiring portion 13. The contact resistance between the portion 13 and the W plug 19 can be kept low, and the uniformity thereof can be enhanced, thereby realizing a highly reliable MOS transistor.

(Second Embodiment)
In this embodiment, a method for manufacturing a MOS transistor is disclosed as in the first embodiment, but the process of forming a W plug for connecting an upper wiring and a Cu wiring portion below it is slightly different.
FIG. 10 is a schematic cross-sectional view showing only main steps of the MOS transistor manufacturing method according to the second embodiment.

First, the same steps as those in FIGS. 1A to 7B of the first embodiment are sequentially performed.
Subsequently, as shown in FIG. 10A, a tungsten (W) film 18 is deposited.
Specifically, as in the first embodiment, the W film 22 is deposited as follows by a two-stage thermal CVD method.
First, as a first stage (initial stage), a first supply gas containing WF ₆ , H ₂ and NH ₃ and not containing a silane-based gas is used. The NH ₃ gas content ratio in the flow rate of the first supply gas is a lower limit from the viewpoint of ensuring sufficient acceleration efficiency of the thermal decomposition reaction of the WF ₆ gas, and an upper limit from the viewpoint of suppressing a reduction in the film deposition coverage. A value may be set, for example, about 2% to 30%. Here, the flow rate of the first supply gas is set to about 50 sccm / 3000 sccm / 200 sccm for WF ₆ / H ₂ / NH ₃ . Further, N ₂ gas is introduced as a dilution gas. The film forming temperature (substrate temperature: first temperature) is set to about 300 ° C. to 360 ° C., here about 330 ° C. In some cases, WF ₆ and NH ₃ are not simultaneously introduced into the reaction chamber, but are introduced alternately, thereby suppressing the rapid reaction of WF ₆ decomposition and performing thin film growth.
With the above requirements, a W film 22a having a film thickness of about 2 nm to 10 nm, here about 5 nm, is formed so as to cover the inner wall surface of the via hole 16 and the interlayer insulating film 15 via the base film 17.

Next, the second supply gas containing WF ₆ and H ₂ is used, and the flow rate of the second supply gas is set to about 100 sccm / 3000 sccm for WF ₆ / H ₂ . Further, the film formation temperature (substrate temperature: second temperature) is set to about 350 ° C. to 450 ° C., which is higher than the first temperature, here, about 400 ° C.
With the above requirements, the W film 22b having a thickness of about 100 nm to 500 nm, here, about 200 nm is formed so as to be embedded in the W hole 22a and burying the via hole 16. As described above, the W film 22a is formed by integrating the W film 22a and the W film 22b. In the illustrated example, the boundary between the W film 22a and the W film 22b is indicated by a broken line for convenience.

  Subsequently, after the W plug 23 is formed by filling the via hole 16 with the W film 22 through the base film 17 by CMP as in FIG. 8B, the same process as in FIG. 9 is performed. As a result, as shown in FIG. 10B, the upper layer wiring 21 that is electrically connected to the W plug 23 and extends on the interlayer insulating film 15 is formed.

Here, the W plug 23 contains NH ₃ gas nitrogen (N) in the W film 22 a, and as a result, when viewed as a whole of the W film 22, at least the interface portion of the W film 22 with the base film 17. It becomes the structure which contains N in (the part of W film | membrane 22a).

  Thereafter, the MOS transistor according to the present embodiment is completed through formation of a protective film, formation of a connection pad with the upper layer wiring 21, and the like.

In this embodiment, when the W plug 23 is formed, first, a W film 22a is deposited using a first supply gas containing NH ₃ so as to fill an opening such as a connection hole. With this configuration, even when the base film 17 is formed thin and a step is generated on the inner wall surface of the via hole 17, the supply gas is prevented from eroding the Cu surface exposed on the bottom surface of the via hole 17. Therefore, when the W film 22 is deposited so as to fill the via hole 17, the Cu movement of the Cu wiring portion 13 does not occur in the deposited W film 22, and even if the base film 17 is thin, W is Cu by the base film 17. A W plug 23 is formed in a state of being distinct from Cu of the wiring portion 13.

  Therefore, according to the present embodiment, a process that can be easily formed can be selected as the formation process of the base film 17 of the W plug 23, and Cu wiring is suppressed by suppressing Cu erosion of the underlying Cu wiring portion 13. The contact resistance between the portion 13 and the W plug 23 can be kept low and the uniformity thereof can be improved, thereby realizing a highly reliable MOS transistor.

As described above, when the W film 18a of the W plug 19 is formed in the first embodiment, a material containing B ₂ H ₆ is used as the first supply gas, and in the first embodiment, W ₂ is used. When the W film 22a of the plug 23 is formed, the case where NH ₃ is used as the first supply gas is exemplified. The present invention is not limited to these. For example, it is also conceivable to use a gas containing both B ₂ H ₆ and NH ₃ as the first supply gas.

  In the first and second embodiments, the case where the object to be formed using the first supply gas is a W plug is exemplified. The present invention is not limited to these, and also when a groove is formed as an opening in the interlayer insulating film 15 in which the Cu wiring portion 13 is embedded, and a fuse (W fuse) is formed by filling the groove with a W film. The thermal CVD method using the first supply gas similar to the above is employed.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) Forming a first wiring containing copper above the semiconductor substrate;
Forming an interlayer insulating film on the first wiring;
Forming an opening in the interlayer insulating film to expose a part of the surface of the first wiring;
Forming a connection portion containing W in the opening using a first supply gas containing WF ₆ and at least one of B ₂ H ₆ and NH ₃ . Production method.

(Supplementary Note 2) The step of forming the connecting portion includes:
Forming a first W-containing film that covers an inner wall surface of the opening using the first supply gas;
The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a second W-containing film that fills the opening using a second supply gas containing WF ₆ and H ₂ .

(Appendix 3) In the step of forming the first W-containing film, the film forming temperature is set to a first temperature of 300 ° C. or higher and 360 ° C. or lower,
3. The method of manufacturing a semiconductor device according to appendix 2, wherein in the step of forming the second W-containing film, a film forming temperature is set to a second temperature higher than the first temperature.

  (Appendix 4) Any one of appendices 1 to 3, further comprising a step of forming a second wiring containing Al on the interlayer insulating film so as to be electrically connected to the connection portion. 2. A method for manufacturing a semiconductor device according to item 1.

  (Additional remark 5) After the process of forming the said opening part, before the process of forming the said connection part, the process of forming a base film in the inner wall of the said opening part is further included, The additional notes 1-4 characterized by the above-mentioned A manufacturing method of a semiconductor device given in any 1 paragraph.

  (Additional remark 6) The said base film contains TiN or WN, The manufacturing method of the semiconductor device of any one of Additional remark 1-5 characterized by the above-mentioned.

  (Additional remark 7) The said base film is the manufacturing method of the semiconductor device of any one of Additional remark 1-6 characterized by the thickness of the thickest part being 2 nm or more and 10 nm or less.

  (Additional remark 8) The said 1st supply gas does not contain silane type gas, The manufacturing method of the semiconductor device of any one of Additional remark 1-7 characterized by the above-mentioned.

(Appendix 9) a semiconductor substrate;
A first wiring containing copper formed above the semiconductor substrate;
An interlayer insulating film formed on the first wiring and having an opening formed so as to expose a part of the first wiring;
A connection portion containing W formed in the opening,
The semiconductor device according to claim 1, wherein the connection portion contains B or N.

  (Supplementary note 10) The semiconductor device according to supplementary note 9, further comprising: a second wiring containing Al formed on the interlayer insulating film so as to be electrically connected to the connection portion. .

  (Supplementary note 11) The semiconductor device according to supplementary note 9 or 10, further comprising a base film formed between an inner wall surface of the opening and the connection part, wherein the base film contains TiN or WN. .

  (Supplementary note 12) The semiconductor device according to any one of supplementary notes 9 to 11, wherein the base film has a thickness of a thickest portion of 2 nm to 10 nm.

It is a schematic sectional drawing which shows the manufacturing method of the MOS transistor by 1st Embodiment in order of a process. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1 illustrating the MOS transistor manufacturing method according to the first embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view illustrating the method of manufacturing the MOS transistor according to the first embodiment in order of processes subsequent to FIG. 2. FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the MOS transistor according to the first embodiment in order of processes following FIG. 3. FIG. 5 is a schematic cross-sectional view showing the method of manufacturing the MOS transistor according to the first embodiment in order of processes following FIG. 4. FIG. 6 is a schematic cross-sectional view showing the MOS transistor manufacturing method according to the first embodiment in the order of steps, following FIG. 5; FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 showing the MOS transistor manufacturing method according to the first embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view showing the method of manufacturing the MOS transistor according to the first embodiment in order of processes subsequent to FIG. 7. FIG. 9 is a schematic cross-sectional view showing the method of manufacturing the MOS transistor according to the first embodiment in order of processes following FIG. 8. It is a schematic sectional drawing which shows only the main processes of the manufacturing method of the MOS transistor by 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation structure 2a Isolation groove 3 Gate insulating film 4 Gate electrode 5 Source / drain region 6, 8, 12, 15 Interlayer insulating film 7 W plug 7a Contact hole 7b, 9b, 13d, 17 Base film 9 Cu wiring 9a, 13b Wiring groove 11, 14 Etching stopper film 13 Cu wiring part 13a, 16 Via hole 13c Composite groove 13e Cu film 18, 18a, 18b, 22, 22a, 22b W film 19, 23 W plug 21 Upper layer wiring 21a, 21c Adhesion film 21b Al film 31 SiN film 31a Wiring groove pattern 32, 34 Antireflection film 33, 35 Resist pattern 35a Via hole pattern

Claims (4)

Forming a first wiring containing copper above the semiconductor substrate;
Forming an interlayer insulating film on the first wiring;
Forming an opening in the interlayer insulating film to expose a part of the surface of the first wiring;
Forming a base film made of TiN or WN on the inner wall surface of the opening,
A first W-containing film is formed on the base film using a first supply gas containing WF ₆ , at least one of B ₂ H ₆ and NH ₃ , and H ₂ and not containing a silane-based gas. And a step of forming the semiconductor device. After the formation of the first W-containing film, a second W-containing film that fills the opening using a second supply gas that contains WF ₆ and H ₂ and does not contain B ₂ H ₆ and NH ₃ The method of manufacturing a semiconductor device according to claim 1, further comprising: In the step of forming the first W-containing film, the film forming temperature is set to a first temperature of 300 ° C. or higher and 360 ° C. or lower,
3. The method of manufacturing a semiconductor device according to claim 2, wherein, in the step of forming the second W-containing film, a film formation temperature is set to a second temperature higher than the first temperature.   4. The method according to claim 2, further comprising a step of forming a second wiring containing Al on the interlayer insulating film so as to be electrically connected to the second W-containing film. Semiconductor device manufacturing method.

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