JP5394025B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a trench gate type VDMOSFET and a method for manufacturing the semiconductor device.

As a structure effective for miniaturization of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure is generally known.
FIG. 9 is a schematic cross-sectional view of a semiconductor device having a conventional trench gate type VDMOSFET.

The semiconductor device 100 includes an N ⁺ type substrate 101. An N ⁻ type epitaxial layer 102 is laminated on the N ⁺ type substrate 101. The base layer portion of the N ⁻ -type epitaxial layer 102 is an N ⁻ -type region 103, and the P ⁻ -type body region 104 is formed adjacent to the N ⁻ -type region 103 in the surface layer portion of the N ⁻ -type epitaxial layer 102. Has been.
A gate trench 105 is dug from the surface of the N ⁻ type epitaxial layer 102. Gate trench 105 penetrates P ⁻ type body region 104, and the deepest part reaches N ⁻ type region 103. A gate electrode 107 made of polysilicon doped with an N-type impurity at a high concentration is buried in the gate trench 105 via a gate insulating film 106 made of SiO ₂ (silicon oxide).

An N ⁺ type source region 108 is formed along the gate trench 105 in the surface layer portion of the P ⁻ type body region 104. In the N ⁺ type source region 108, a P ⁺ type contact region 109 is formed so as to penetrate the N ⁺ type source region 108 in the center portion in plan view.
An interlayer insulating film 110 is stacked on the N ⁻ type epitaxial layer 102. A source wiring 111 is formed on the interlayer insulating film 110. The source wiring 111 is grounded. The source wiring 111 is in contact (electrically connected) to the N ⁺ type source region 108 and the P ⁺ type contact region 109 through a contact hole 112 formed in the interlayer insulating film 110. Further, the gate wiring 113 is electrically connected to the gate electrode 107 through a contact hole (not shown) formed in the interlayer insulating film 110.

A drain electrode 114 is formed on the back surface of the N ⁺ type substrate 101.
By controlling the potential of the gate electrode 107 while applying an appropriate positive voltage to the drain electrode 114, a channel is formed in the vicinity of the interface with the gate insulating film 106 in the P ⁻ type body region 104 (channel formation region 116). , And a current can flow between the N ⁺ type source region 108 and the drain electrode 114. Thereby, the switching operation of the VDMOSFET is achieved.
JP 11-274484 A

As an index representing the switching performance of the VDMOSFET, for example, the product R _on · Q _g the resistance R _on the gate charge quantity Q _g of VDMOSFET is used, the more the product R _on · Q _g is small, faster switching Operation can be achieved.
In the semiconductor device 100 of FIG. 9, the on-resistance R _on3 of the _VDMOSFET is a resistance between the source wiring 111 and the drain electrode 114. For example, the combined resistance of the channel resistance R _ch2 in the channel formation region 116 and the epi resistance R _epi2 in the N ⁻ -type region 103.

On the other hand, the gate charge amount Q _g3 of the VDMOSFET is a gate capacitance C _g3 formed between the gate electrode 107 and the portion of the N ⁻ type region 103 on the bottom surface of the gate trench 105 and the side surface of the gate trench 105. A capacitance C _ox4 of the gate insulating film 106 sandwiched between the gate electrode 107 and the N ⁺ -type source region 108, a capacitance C _ox5 of the gate insulating film 106 sandwiched between the N ⁻ -type region 103 and the P ⁻ -type body region. 104 is a charge amount accumulated in the capacitor C _dep3 of the depletion layer 115 extending from the interface with the capacitor 104. In the semiconductor device 100, if the product R _on3 · Q _g3 can be reduced, the high-speed switching operation of the VDMOSFET can be achieved.

However, as shown in FIG. 10, the on-resistance R _on3 and the gate charge amount Q _g3 are in a so-called trade-off relationship that when one is reduced, the other is increased. Therefore, to reduce the product R _on3 · Q _g3 , it is necessary to reduce one of the on-resistance R _on3 and the gate charge amount Q _g3 and to prevent the other from increasing.
Further, with respect to the on-resistance R _on3 of the semiconductor device 100, by reducing either the resistance of the channel resistance R _ch2 or epi resistor R _epi2, it is possible to reduce the on-resistance R _on3.

As a measure for reducing the on-resistance R _on3 , for example, a measure for reducing the thickness of the gate insulating film 106 can be considered. However, when the gate insulating film 106 is thin, when a voltage is applied to the drain electrode 114, a voltage higher than the withstand voltage of the gate insulating film 106 is applied between the gate and the drain, and the gate insulating film 106 106 may cause dielectric breakdown. In order to prevent such breakdown, it is necessary to secure a certain thickness of the gate insulating film 106, which hinders reduction of the on-resistance R _on3 in the semiconductor device 100. Therefore, it has been difficult to manufacture a semiconductor device with a low voltage specification that can be driven with a low voltage.

An object of the present invention is to provide a semiconductor device capable of reducing the amount of gate charge without causing an increase in on-resistance and a method for manufacturing the same.
Another object of the present invention is to provide a semiconductor device capable of reducing on-resistance and a method for manufacturing the same.

According to a first aspect of the present invention for achieving the above object, an insulating layer having a predetermined pattern is formed on one surface of a first semiconductor layer of a first conductivity type, and the first semiconductor layer is exposed. A step of growing the first conductive type second semiconductor layer on the surface; a step of growing a second conductive type body layer on the second semiconductor layer; and the insulating layer from the surface of the body layer. And introducing the first conductivity type impurity around the substrate to form the first conductivity type source region, and forming the insulating layer on the same plane as the upper surface of the second semiconductor layer. Removing the insulating layer to form a trench, and leaving the bottom of the insulating layer as a part of the gate insulating film; oxidizing the surface of the body layer including the side surface of the trench; A gate insulating film is formed with the bottom of Forming an oxide film that, on the gate insulating film, and forming a gate electrode so as to fill the trench, a method of manufacturing a semiconductor device.
According to a fifth aspect of the present invention, there is provided the step of forming an insulating layer having a predetermined pattern on one surface of the first conductive type first semiconductor layer, and the exposed surface of the first semiconductor layer on the exposed surface. Growing a first conductive type second semiconductor layer; growing a second conductive type body layer on the second semiconductor layer; and surrounding the insulating layer from the surface of the body layer, Introducing a first conductivity type impurity to form the first conductivity type source region; removing the insulating layer; penetrating the body layer; and a deepest portion reaching the first semiconductor layer Forming a gate trench; introducing a second conductivity type impurity into the first semiconductor layer from the bottom of the gate trench; oxidizing the bottom and side surfaces of the gate trench and the top surface of the body layer; In the gate trench And forming a gate insulating film having an upper surface located on the same plane as the upper surface of the second semiconductor layer; and forming a gate electrode on the gate insulating film so as to fill the gate trench; A method for manufacturing a semiconductor device including:
According to the first and fifth aspects of the present invention, the first conductivity type layer of the first conductivity type, the second conductivity type body layer formed on the first conductivity type layer, the body layer, and the deepest A gate trench that reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench in a surface layer portion of the body layer, and a bottom surface and a side surface of the gate trench. And a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the top surface of the first conductivity type layer are located on the same plane. A semiconductor device can be obtained .

According to this configuration, the gate insulating film is formed on the bottom and side surfaces of the gate trench where the deepest portion reaches the first conductivity type layer. A gate electrode is embedded in the gate trench through a gate insulating film. The bottom surface of the gate electrode is located on the same plane as the top surface of the first conductivity type layer.
Since the bottom surface of the gate electrode and the top surface of the first conductivity type layer are located on the same plane, the gate electrode sandwiches only the gate insulating film on the bottom surface of the gate trench with respect to the first conductivity type layer. Opposite, not across the gate insulating film on the side surface of the gate trench. Therefore, compared with the configuration in which the gate electrode faces the first conductivity type region with the gate insulating film on the bottom and side surfaces of the gate trench interposed therebetween (see FIG. 9), the facing area between the gate electrode and the first conductivity type layer is smaller. Can be small.

Therefore, the parasitic capacitance generated between the gate electrode and the first conductivity type layer can be reduced. As a result, the gate capacitance can be reduced, and the gate charge amount can be reduced.
Further, the on-resistance of the semiconductor device does not increase due to the configuration in which the bottom surface of the gate electrode and the top surface of the first conductivity type layer are located on the same plane. That is, according to the above configuration, the amount of gate charge can be reduced without increasing the on-resistance.

  According to a second aspect of the present invention, in the step of forming the gate insulating film, the oxide film is formed to be thinner than the insulating layer remaining as a part of the gate insulating film, thereby forming the trench. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a gate insulating film having a film thickness of a portion covering the bottom surface of the first electrode, greater than a film thickness of a portion facing the body layer on the side surface of the trench. is there.
  According to a sixth aspect of the present invention, in the step of introducing the second conductivity type impurity from the bottom surface of the gate trench, the second conductivity type impurity region formed by the introduction of the impurity is more than the body region. The step of introducing an impurity so as to obtain a high impurity concentration, and the step of forming the gate insulating film utilizes a difference in oxidation rate based on a difference in impurity concentration between the second conductivity type impurity region and the body region. The method further comprises: forming a gate insulating film in which the film thickness of the portion covering the bottom surface of the gate trench is thicker than the film thickness of the portion facing the body layer on the side surface of the gate trench. This is a method for manufacturing the semiconductor device.

That is, in the semiconductor device, a gate insulating film, the film thickness of the portion covering the bottom surface of the pre-Symbol gate trench is preferably thicker than the thickness of the portion opposed to the body layer in a side surface of the gate trench.
In a trench gate type semiconductor device, a predetermined voltage (gate threshold voltage) is applied to a gate electrode, and a channel is formed in the vicinity of the interface with the insulating film of the body layer on the side surface of the gate trench (channel formation region). Operate the device.

For example, it is conceivable to increase the distance between the gate electrode and the bottom surface of the gate trench by uniformly increasing the thickness of the gate insulating film and to reduce the parasitic capacitance generated between them. However, when the thickness of the gate insulating film facing the channel formation region is increased, the on-resistance may increase.
On the other hand, by setting the thickness of the portion of the gate trench facing the body layer to an appropriate thickness and increasing only the thickness of the portion of the gate insulating film that covers the bottom surface of the gate trench, the on-resistance of the semiconductor device is increased. Without increasing, the parasitic capacitance generated between the gate electrode and the bottom surface (first conductive layer) of the gate trench can be reduced. Therefore, the gate capacitance can be further reduced, and the gate charge amount can be further reduced. As a result, a much faster switching operation can be achieved.

According to a third aspect of the present invention, the step of forming the source region includes a step of forming the source region with an impurity concentration higher than that of the body region, and the step of forming the gate insulating film includes the step of forming the source region. Using the difference in oxidation rate based on the difference in impurity concentration between the region and the body region, the film thickness of the portion adjacent to the source region on the side surface of the trench is the body excluding the source region in the body layer. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a gate insulating film thicker than a film thickness of a portion facing the region.
According to a seventh aspect of the present invention, the step of forming the source region includes a step of forming the source region with an impurity concentration higher than that of the body region, and the step of forming the gate insulating film includes the step of forming the source region. Using the difference in oxidation rate based on the difference in impurity concentration between the region and the body region, the thickness of the portion adjacent to the source region on the side surface of the gate trench excludes the source region in the body layer 7. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of forming a gate insulating film thicker than a film thickness of a portion facing the body region.
That is, in the semiconductor device, a gate insulating film, the side surface of the front Symbol gate trench, the thickness of the portion adjacent to the source region, the thickness of the portion opposed to the body region excluding the source region in the body layer It is preferable that it is thicker.
If the thickness of the portion of the gate insulating film adjacent to the source region on the side surface of the gate trench is thicker than the thickness of the portion facing the body region, the gate without increasing the on-resistance of the semiconductor device. Parasitic capacitance generated between the electrode and the source region can be reduced. Therefore, the gate capacitance can be further reduced, and the gate charge amount can be further reduced. As a result, a much faster switching operation can be achieved.

Moreover, according to the semiconductor device obtained by the invention of claim 5 , since the second conductivity type impurity is contained in the portion from the bottom surface of the gate trench to the middle portion in the thickness direction of the first conductivity type layer, The thickness of the depletion layer extending from the interface between the first conductivity type layer and the body layer and below the gate trench (extension in the thickness direction of the first conductivity type layer) can be increased. Therefore, the parasitic capacitance of the depletion layer can be reduced and the breakdown voltage of the semiconductor device can be improved.

  According to a fourth aspect of the present invention, the step of forming the insulating layer includes a step of forming an insulating layer having a two-layer structure in which a lower layer film made of silicon oxide and an upper layer film made of silicon nitride are sequentially laminated. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the insulating layer includes a step of removing the insulating layer so that at least the two-layer structure remains. is there.

In other words, the semiconductor device obtained by the first aspect of the present invention, the gate insulating film, a bottom portion in contact with the first conductive layer on the bottom surface and the side surface of the gate trench before Symbol gate trench, made of silicon oxide underlayer It is preferable to form a two-layer structure in which a film and an upper film made of silicon nitride are sequentially stacked .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention.
The semiconductor device 1 has an array structure in which unit cells having trench gate type VDMOSFETs are arranged in a matrix.
On N ⁺ type substrate 2 forming the base of the semiconductor device 1, N-type impurities than N ⁺ -type substrate 2 (for example, P (phosphorus)) doped with a low concentration (e.g., 10 ¹⁵ / cm ³⁾ An N ⁻ type layer 4 made of Si (silicon) is laminated. A P ⁻ -type body layer 5 is laminated on the N ⁻ -type layer 4.

In the semiconductor device 1, a gate trench 6 is formed by being dug down from the surface of the body layer 5. Gate trench 6 penetrates body layer 5, and the deepest part reaches N ⁻ -type layer 4. A plurality of gate trenches 6 are formed at regular intervals in the left-right direction in FIG. 1, and each extend in a direction (direction along the gate width) perpendicular to the paper surface of FIG. A gate insulating film 7 is formed on the inner surface of the gate trench 6 and the upper surface of the body layer 5 so as to cover the whole area.

The gate insulating film 7 has a bottom portion 71 and an upper portion 72.
The bottom 71 is in contact with the N ⁻ -type layer 4 on the bottom surface of the gate trench 6 and the side surface of the gate trench 6, and includes a lower layer film 73 made of SiO ₂ (silicon oxide) and an upper layer film 74 made of SiN (silicon nitride). It has a two-layer structure laminated in order. The film thickness T ₁ of the lower layer film 73 is, for example, ₁ μm to ₁₀ μm, and the film thickness T ₂ of the upper layer film 74 is, for example, 0.05 μm to 0.2 μm. The upper surface of the upper film 74 (upper surface of the bottom portion 71), N ^- are positioned on the same plane as the ^- (interface between the mold layer 4 and the body layer 5 N) upper surface 4A type layer 4.

The upper portion 72 has a source region facing portion 75 that faces a source region 9 described later, and a body region facing portion 76 that faces the body region 3 excluding the source region 9 in the body layer 5. The film thickness T ₃ of the source region facing portion 75 is, for example, 0.06 μm to 0.1 μm, and the film thickness T ₄ of the body region facing portion 76 is, for example, 0.04 μm to 0.06 μm.
Then, the inside of the gate insulating film 7 in the gate trench 6 is filled with polysilicon doped with an N-type impurity (for example, P (phosphorus)) at a high concentration, whereby the gate electrode 8 is formed in the gate trench 6. Buried. The bottom surface 8A of the gate electrode 8 is in contact with the upper surface of the upper layer film 74 (the upper surface of the bottom portion 71). That is, the bottom surface 8 A of the gate electrode 8 is located on the same plane as the top surface 4 A of the N ⁻ -type layer 4.

In the surface layer portion of the body layer 5, an N-type impurity concentration (N-type impurity concentration higher than the N-type impurity concentration of the N ⁻ -type layer 4) on both sides of the gate trench 6 in the direction orthogonal to the gate width (left-right direction in FIG. 1). For example, an N ⁺ type source region 9 having 10 ¹⁹ / cm ³ to 10 ²¹ / cm ³ ) is formed.
The source region 9 extends along the gate width along the gate trench 6, and the bottom thereof is in contact with the body region 3 in the body layer 5. A P ⁺ -type source contact region 10 is formed through the source region 9 at the center of the source region 9 in the direction orthogonal to the gate width.

  That is, the gate trenches 6 and the source regions 9 are alternately provided in a direction orthogonal to the gate width, and each extend in a direction along the gate width. A boundary between adjacent unit cells is set on the source region 9 along the source region 9 in a direction orthogonal to the gate width. At least one source contact region 10 is provided across two unit cells adjacent in a direction orthogonal to the gate width. The boundary between unit cells adjacent in the direction along the gate width is set so that the gate electrode 8 included in each unit cell has a constant gate width.

  On the body layer 5, an interlayer insulating film 13 is laminated via a gate insulating film 7. A source wiring 14 is formed on the interlayer insulating film 13. The source wiring 14 is grounded. The source wiring 14 is in contact (electrically connected) to the source region 9 and the source contact region 10 through a source plug 18 provided through the interlayer insulating film 13 and the gate insulating film 7.

A gate wiring 16 is formed on the interlayer insulating film 13. The gate wiring 16 is in contact (electrically connected) to the gate electrode 8 through a gate plug 12 provided through the interlayer insulating film 13 and the gate insulating film 7.
A drain electrode 27 is formed on the back surface of the N ⁺ type substrate 2.
A channel is formed in the vicinity of the interface with the gate insulating film 7 in the body region 3 (channel formation region 29) by controlling the potential of the gate electrode 8 while applying an appropriate positive voltage to the drain electrode 27. Thus, a current can flow between the source region 9 and the drain electrode 27.

In the semiconductor device 1, the bottom surface 8 </ b> A of the gate electrode 8 and the top surface 4 </ b> A of the N ⁻ -type layer 4 are located on the same plane. Therefore, the gate electrode 8 is opposed to the N ⁻ type layer 4 with only the bottom 71 of the gate insulating film 7 interposed therebetween, and is opposed to the gate insulating film 7 (upper portion 72) on the side surface of the gate trench 6. Not.
Therefore, as in the semiconductor device 100 shown in FIG. 9, the gate electrode 107 has a gate electrode 8 that is opposed to the N ⁻ -type region 103 with the gate insulating film 106 on the bottom and side surfaces of the gate trench 105 interposed therebetween. And the N ⁻ -type layer 4 can be made to have a smaller facing area. Therefore, the parasitic capacitance C _ox1 generated between the gate electrode 8 and the N ⁻ -type layer 4 can be reduced.

The gate capacitance C _g1 of the semiconductor device 1 is, for example, a parasitic capacitance C _ox1, N ^- Synthesis of the parasitic capacitance C _dep1 the depletion layer 28 has extending from the interface between the mold layer 4 and the body region 3, and C _ox2 described later Expressed in capacity. Therefore, the gate capacitance C _g1 can be reduced by reducing the parasitic capacitance C _ox1, and as a result, the gate charge amount Q _g1 can be reduced.
Further, the configuration in which the bottom surface 8A of the gate electrode 8 and the top surface 4A of the N ⁻ -type layer 4 are located on the same plane does not increase the on-resistance R _on1 of the semiconductor device 1. That is, in the structure of the semiconductor device 1, the gate charge amount Q _g1 can be reduced without increasing the on-resistance R _on1 .

Further, in this semiconductor device 1, the thickness T ₁ + T ₂ of the bottom 71 in the gate insulating film 7 is, for example, 1.05 μm to 10.2 μm, and the film thickness T ₄ (for example, 0) of the body region facing portion 76. .04 μm to 0.06 μm).
In the trench gate type semiconductor device such as the semiconductor device 1, as described above, a predetermined voltage (gate threshold voltage) is applied to the gate electrode 8, and a channel is formed in the channel formation region 29 to operate the semiconductor device 1. Let

For example, it is considered to increase the distance between the gate electrode 8 and the bottom surface of the gate trench 6 by uniformly increasing the thickness of the gate insulating film 7 and to reduce the parasitic capacitance generated therebetween. It is done. However, if the film thickness of the gate insulating film 7 (body region facing portion 76) facing the channel formation region 29 is increased, the on-resistance R _on1 may increase.
However, in the semiconductor device 1, by setting the film thickness T ₄ of the body region facing portion 76 to an appropriate thickness and increasing only the film thickness T ₁ + T _{2 of} the bottom portion 71, the gate without increasing the on-resistance R _on1. The parasitic capacitance C _ox1 generated between the electrode 8 and the N ⁻ -type layer 4 can be further reduced. As a result, the gate capacitance C _g1 can be further reduced, and the gate charge amount Q _g1 can be further reduced.

Moreover, in the semiconductor device 1, the film thickness T ₃ of the source region facing portion 75 is also thicker than the film thickness T ₄ of the body region facing portion 76. Therefore, by increasing only the thickness T ₃ of the source region facing portion 75, without increasing the on-resistance R _on1, that parasitic capacitance C _ox2 generated between the gate electrode 8 and the source region 9 is also reduced In addition, the gate charge amount Q _g1 can be further reduced.

As a result, a much faster switching operation can be achieved.
2A to 2J are cross-sectional views illustrating the method for manufacturing the semiconductor device 1 in the order of steps.
First, as shown in FIG. 2A, an N ⁻ type layer 17 (first semiconductor layer) is formed on the N ⁺ type substrate 2 by an epitaxial growth method.
Then, this on the N ^- -type layer 17, the SiO ₂ layer (e.g., layer thickness 1 m to 10 m), SiN layer (e.g., layer thickness 0.05Myuemu～0.2Myuemu) and SiO ₂ layer (e.g., layer thickness 1μm~ 1.5 μm) are formed in sequence, and these layers are patterned. Thus, as shown in FIG. 2B, N ^- on the upper surface 17A of the mold layer 17 (one surface of the first semiconductor layer), a predetermined pattern ^- the (N pattern the upper surface 17A of the mold layer 17 is partially exposed) An insulating layer 50 including the first insulating layer 32, the second insulating layer 33, and the third insulating layer 34 is formed (step of forming an insulating layer).

Then, N ^- on the upper surface 17A of the mold layer 17, N ^- type semiconductor layer is epitaxially grown. The N ⁻ type semiconductor layer is grown to a height where the upper surface thereof is located on the same plane as the upper surface of the second insulating layer 33. Thus, as shown in FIG. 2C, N ^- on the upper surface 17A of the mold layer 17, the N ^- -type layer 19 is formed (step of growing a second semiconductor layer), the N ^- -type layer 17 and the N ^- -type layer composed of the 19 N ^- -type layer 4 is formed.

After the N ⁻ type layer 4 is formed, a P ⁻ type semiconductor layer is grown on the N ⁻ type layer 4. This P ⁻ -type semiconductor layer is grown, for example, to a height where the upper surface is located slightly below the upper surface of the insulating layer 50 (the upper surface of the third insulating layer 34). Thereby, as shown in FIG. 2C, body layer 5 is formed on N ⁻ type layer 4 (step of growing the body layer).
Thereafter, as shown in FIG. 2D, a mask 25 having an opening in a portion facing the portion where the source region 9 is to be formed is formed on the body layer 5. Then, ions of N-type impurities (for example, P (phosphorus)) are implanted into the surface layer portion of the body layer 5 through the opening of the mask 25. After this ion implantation, the mask 25 is removed.

Further, as shown in FIG. 2E, a mask 26 having an opening in a portion facing the portion where the source contact region 10 is to be formed is formed on the body layer 5. Then, ions of P-type impurities (for example, B (boron)) are implanted into the surface layer portion of the body layer 5 through the opening of the mask 26. After this ion implantation, the mask 26 is removed.
Thereafter, an annealing process is performed. By this annealing treatment, ions of N-type impurities and P-type impurities implanted into the surface layer portion of the body layer 5 are activated, and the source region 9 and the source contact are formed on the surface layer portion of the body layer 5 as shown in FIG. 2F. Region 10 is formed (step of forming a source region). Further, the portion of the body layer 5 other than the source region 9 and the source contact region 10 becomes the body region 3 as it is after the epitaxial growth.

Subsequently, the insulating layer 50 is removed by dry etching or wet etching using HF (hydrofluoric acid) until the upper surface thereof is located on the same plane as the upper surface 4A of the N ⁻ -type layer 4. That is, as shown in FIG. 2G, the third insulating layer 34 in the insulating layer 50 is removed, and the trench 21 having the upper surface of the second insulating layer 33 as the bottom surface is formed in the body layer 5. The first insulating layer 32 and the second insulating layer 33 are left as part of the gate insulating film 7.

Next, as shown in FIG. 2H, the surface of the body layer 5 including the side surface of the trench 21 is oxidized by the thermal oxidation process to form an oxide film 42 (step of forming an oxide film).
The source region 9 in the body layer 5 has a higher impurity concentration than the body region 3 and is oxidized at an oxidation rate higher than that of the body region 3. Therefore, the oxide film 42 has a source region facing portion 43 that faces the source region 9 and has a relatively large thickness, and a body region facing portion 44 that faces the body region 3 and has a relatively small thickness. It is formed. Thus, as shown in FIG. 2H, the gate insulating film 7 composed of the bottom of the insulating layer 50 including the first insulating layer 32 and the second insulating layer 33 and the oxide film 42 is formed. The first insulating layer 32 and the second insulating layer 33 become the lower layer film 73 and the upper layer film 74 in the gate insulating film 7, respectively. On the other hand, the source region facing portion 43 and the body region facing portion 44 in the oxide film 42 become the source region facing portion 75 and the body region facing portion 76 in the gate insulating film 7, respectively. The portion surrounded by the side surface of the trench 21 and the contact interface with the bottom 71 in the N ⁻ -type layer 4 constitutes the gate trench 6.

  Then, a polysilicon deposition layer doped with an N-type impurity (for example, P (phosphorus)) at a high concentration is formed on the gate insulating film 7 by the CVD method. The inside of the gate trench 6 is filled with a polysilicon deposition layer. Then, a portion of the polysilicon deposition layer existing outside the gate trench 6 is removed by etching. As a result, as shown in FIG. 2I, the gate electrode 8 embedded in the gate trench 6 is obtained (step of forming the gate electrode).

After the above steps, an interlayer insulating film 13 is formed on the gate insulating film 7 by CVD as shown in FIG. 2J. Thereafter, a gate plug 12 is provided through the gate insulating film 7 and the interlayer insulating film 13, and a gate wiring 16 is formed on the gate plug 12. A source plug 18 is provided through the gate insulating film 7 and the interlayer insulating film 13, and a source wiring 14 is formed on the source plug 18. A drain electrode 27 is formed on the back surface of the N ⁺ type substrate 2. Thereby, the semiconductor device 1 shown in FIG. 1 is obtained.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 3, portions corresponding to the respective portions shown in FIG. 1 are denoted by the same reference numerals as those respective portions. Further, in the following, detailed description of the parts denoted by the same reference numerals is omitted.
In the semiconductor device 31, on the N ⁺ -type substrate 2, N ⁺ N-type impurity than the -type substrate 2 is made of a low concentration (e.g., 10 ¹⁵ / cm ³⁾ to the doped a Si (silicon) N ^- -type Layer 22 is laminated. A P ⁻ -type body layer 5 is laminated on the N ⁻ -type layer 22.

In the semiconductor device 31, the gate trench 6 is formed by being dug down from the surface of the body layer 5. Gate trench 6 penetrates body layer 5, and the deepest part reaches N ⁻ -type layer 22. A gate insulating film 35 made of SiO ₂ is formed on the inner surface of the gate trench 6 and the upper surface of the body layer 5 so as to cover the entire area.
The gate insulating film 35 has a bottom portion 36 and an upper portion 37.

Bottom 36, the bottom surface and the side surface of the gate trench 6 in the gate trench 6 N ^- is in contact -type layer 22, the upper surface, N ^- top 22A of the mold layer 22 (N ^- the mold layer 4 and the body layer 5 Located on the same plane as the interface. The film thickness T ₅ of the bottom 36 is, for example, 0.06 μm to 0.08 μm.
The upper portion 37 has a source region facing portion 38 facing the source region 9 and a body region facing portion 39 facing the body region 3. The film thickness T ₆ of the source region facing portion 38 is, for example, 0.06 μm to 0.1 μm, and the film thickness T ₇ of the body region facing portion 39 is, for example, 0.04 μm to 0.06 μm.

Then, the inside of the gate insulating film 35 in the gate trench 6 is filled with polysilicon doped with an N-type impurity (for example, P (phosphorus)) at a high concentration, whereby the gate electrode 8 is formed in the gate trench 6. Buried. The bottom surface 8 </ b> A of the gate electrode 8 is in contact with the top surface of the bottom portion 36. That is, the bottom surface 8 A of the gate electrode 8 is located on the same plane as the top surface 22 A of the N ⁻ -type layer 22.

Further, the N ⁻ -type layer 22 contains a P-type impurity in a portion extending from the bottom surface of the gate trench 6 to the bottom of the N ⁻ -type layer 22 (a position away from the upper surface of the N ⁺ -type substrate 2 by a predetermined distance). Region 24 is formed. The P-type impurity-containing region 24 is a region where the N ^- type layer 22 contains P-type impurities. The P-type impurity-containing region 24 has, for example, a thickness T _{8 of 1} μm to 10 μm. Further, the P-type impurity concentration of the P-type impurity-containing region 24 is higher than the P-type impurity concentration of the body region 3 at the upper portion of the region (near the interface with the bottom portion 36), and decreases as it approaches the lower portion of the region. .

Also in this semiconductor device 31, since the bottom surface 8A of the gate electrode 8 and the top surface 22A of the N ⁻ type layer 22 are located on the same plane, the facing area between the gate electrode 8 and the N ⁻ type layer 4 is reduced. be able to. Therefore, the parasitic capacitance C _ox3 generated between the gate electrode 8 and the N ⁻ -type layer 22 can be reduced. As a result, the gate capacitance C _g2 can be reduced, and the gate charge amount Q _g2 can be reduced.

Further, the configuration in which the bottom surface 8A of the gate electrode 8 and the top surface 22A of the N ⁻ -type layer 22 are located on the same plane does not increase the on-resistance R _on2 of the semiconductor device 31. That is, in the structure of the semiconductor device 31, the gate charge amount can be reduced without increasing the on-resistance R _on2 .
Further, in this semiconductor device 31, the P-type impurity-containing region 24 is formed in a portion extending from the bottom surface of the gate trench 6 to the bottom portion of the N ⁻ -type layer 22 (a position away from the top surface of the N ⁺ -type substrate 2 by a predetermined distance). Is formed. Therefore, the thickness of the depletion layer 30 (extending in the thickness direction of the N ⁻ -type layer 22) extending below the gate trench 6 from the interface between the N ⁻ -type layer 22 and the body layer 5 (body region 3) is increased. Can do. Therefore, the parasitic capacitance C _dep2 of the depletion layer 30 can be reduced and the breakdown voltage of the semiconductor device 31 can be improved.

4A to 4K are cross-sectional views illustrating the method of manufacturing the semiconductor device 31 in the order of steps.
First, as shown in FIG. 4A, an N ⁻ type layer 23 (first semiconductor layer) is formed on the N ⁺ type substrate 2 by an epitaxial growth method.
Next, an SiO ₂ layer (for example, a layer thickness of 1 μm to 1.5 μm) is formed on the N ⁻ type layer 23, and this layer is patterned. Thus, as shown in FIG. 4B, N ^- on the upper surface 23A of the mold layer 23 (one surface of the first semiconductor layer), a predetermined pattern ^- the (N pattern the upper surface 23A of the mold layer 23 is partially exposed) The insulating layer 40 is formed (step of forming an insulating layer).

Then, N ^- on the upper surface 23A of the mold layer 23, N ^- type semiconductor layer is epitaxially grown. This N ⁻ -type semiconductor layer is grown from the upper surface 23A of the N ⁻ -type layer 23 until the upper surface is located at a height of 0.03 μm to 0.04 μm, for example. Thus, as shown in FIG. 4C, the N ⁻ type layer 41 is formed on the upper surface 23A of the N ⁻ type layer 23 (step of growing the second semiconductor layer), and the N ⁻ type layer 23 and the N ⁻ type layer are formed. The N ⁻ -type layer 22 composed of 41 is formed.

After the N ⁻ type layer 22 is formed, a P ⁻ type semiconductor layer is grown on the N ⁻ type layer 22. This P ⁻ -type semiconductor layer is grown, for example, to a height at which the upper surface is located slightly below the upper surface of the insulating layer 40. As a result, as shown in FIG. 4C, body layer 5 is formed on N ⁻ type layer 22 (step of growing the body layer).
Thereafter, as shown in FIG. 4D, a mask 25 having an opening in a portion facing the portion where the source region 9 is to be formed is formed on the body layer 5. Then, ions of N-type impurities (for example, P (phosphorus)) are implanted into the surface layer portion of the body layer 5 through the opening of the mask 25. After this ion implantation, the mask 25 is removed.

Further, as shown in FIG. 4E, a mask 26 having an opening in a portion facing the portion where the source contact region 10 is to be formed is formed on the body layer 5. Then, ions of P-type impurities (for example, B (boron)) are implanted into the surface layer portion of the body layer 5 through the opening of the mask 26. After this ion implantation, the mask 26 is removed.
Thereafter, an annealing process is performed. By this annealing treatment, ions of N-type impurities and P-type impurities implanted in the surface layer portion of the body layer 5 are activated, and the source region 9 and the source contact are formed on the surface layer portion of the body layer 5 as shown in FIG. 4F. Region 10 is formed (step of forming a source region). Further, the portion of the body layer 5 other than the source region 9 and the source contact region 10 becomes the body region 3 as it is after the epitaxial growth.

Subsequently, the insulating layer 40 is removed by dry etching or wet etching using HF. In this way, as shown in FIG. 4G, a gate trench 6 that penetrates through the body layer 5 and whose deepest portion reaches the N ⁻ -type layer 22 is formed.
Next, ions of a P-type impurity (for example, B (boron)) are implanted into the N ⁻ -type layer 22 from the bottom surface of the gate trench 6 (step of introducing a second conductivity type impurity). P-type impurity ion implantation is performed in two steps. First, in order that the P-type impurity ions reach the region where the P-type impurity-containing region 24 is to be formed, a low implantation amount (for example, 10 ¹² ion / cm ² to 10 ¹³ ion / at several hundred keV or more). cm ² ). Next, P-type impurity ions are implanted at a low acceleration and a high implantation amount (for example, several keV to several several keV, 10 ¹³ ions / cm ² ) so that the ions are mainly introduced near the bottom surface of the gate trench 6. . As a result, as shown in FIG. 4H, a P ⁻ -type impurity is formed in a portion extending from the bottom surface of the gate trench 6 to the bottom of the N ⁻ -type layer 22 (a position away from the upper surface of the N ⁺ -type substrate 2 by a predetermined distance). A containing region 24 is formed.

Subsequently, as shown in FIG. 4I, the bottom and side surfaces of the gate trench 6 and the top surface of the body layer 5 are oxidized by thermal oxidation, and a gate insulating film 35 is formed (step of forming a gate insulating film). The source region 9 in the body layer 5 has a higher impurity concentration than the body region 3 and is oxidized at an oxidation rate higher than that of the body region 3. The P-type impurity concentration of the P-type impurity-containing region 24 near the bottom surface of the gate trench 6 is higher than that of the body region 3 and is oxidized at an oxidation rate higher than that of the body region 3. In the gate insulating film 35, a bottom portion 36, a source region facing portion 38, and a body region facing portion 39 are formed. As shown in FIG. 4I, the bottom portion 36 is formed so that the upper surface thereof is located on the same plane as the upper surface 22A of the N ⁻ type layer 22.

  Then, a polysilicon deposition layer doped with an N-type impurity (for example, P (phosphorus)) at a high concentration is formed on the gate insulating film 35 by the CVD method. The inside of the gate trench 6 is filled with a polysilicon deposition layer. Then, a portion of the polysilicon deposition layer existing outside the gate trench 6 is removed by etching. As a result, as shown in FIG. 4J, the gate electrode 8 embedded in the gate trench 6 is obtained (step of forming the gate electrode).

After the above steps, the interlayer insulating film 13 is formed on the gate insulating film 35 by the CVD method as shown in FIG. 4K. Thereafter, the gate plug 12 is provided through the gate insulating film 35 and the interlayer insulating film 13, and the gate wiring 16 is formed on the gate plug 12. A source plug 18 is provided through the gate insulating film 35 and the interlayer insulating film 13, and the source wiring 14 is formed on the source plug 18. A drain electrode 27 is formed on the back surface of the N ⁺ type substrate 2. Thereby, the semiconductor device 31 shown in FIG. 3 is obtained.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to the first reference example of the present invention.
The semiconductor device 51 has an array structure in which unit cells having trench gate type VDMOSFETs are arranged in a matrix.
On the N ⁺ type substrate 52 that forms the base of the semiconductor device 51, Si doped with an N type impurity at a lower concentration (for example, 1 × 10 ¹⁵ to 4 × 10 ¹⁵ / cm ³ ) than the N ⁺ type substrate 52. An N ⁻ type epitaxial layer 53 made of (silicon) is laminated. The base layer portion of the epitaxial layer 53 is an N ⁻ type region 54 as the first conductivity type region in a state as it is after the epitaxial growth. In addition, the epitaxial layer 53, N ^- on type region 54, P-type body region 55 the N ^- formed in contact with the mold region 54.

A gate trench 56 is dug from the surface of the epitaxial layer 53. Gate trench 56 penetrates body region 55, and the deepest portion reaches N ⁻ type region 54. A plurality of gate trenches 56 are formed at regular intervals in the left-right direction in FIG. 5, and each extend in a direction (direction along the gate width) perpendicular to the paper surface of FIG. 5. Each gate trench 56 is formed with a width W ₁ in the left-right direction (direction perpendicular to the gate width) in FIG. 5 of, for example, 0.5 μm.

A gate insulating film 57 made of SiO ₂ (silicon oxide) is formed in the gate trench 56 so as to cover the entire inner surface. The gate electrode 58 is buried in the gate trench 56 by filling the inside of the gate insulating film 57 with polysilicon doped with N-type impurities at a high concentration.
Further, the N ⁻ type region 54 of the epitaxial layer 53 has a portion extending from the bottom surface of the gate trench 56 to the bottom of the N ⁻ type region 54 (a position away from the upper surface of the N ⁺ type substrate 52 by a predetermined distance). An intrinsic semiconductor region 67 (low concentration region) is formed. The intrinsic semiconductor region 67 is a region made of an intrinsic semiconductor that does not contain impurities. That is, the N ⁻ -type region 54 is a region having an N-type impurity concentration lower than the remaining portion other than the intrinsic semiconductor region 67. The intrinsic semiconductor region 67 has, for example, a width W ₂ equal to the width W ₁ of the gate trench 56 and a thickness Ta _{1 of 1} μm to 5 μm.

In the surface layer portion of the epitaxial layer 53, N-type impurities higher than the N-type impurity concentration of the N ⁻ -type region 54 are formed on both sides of the gate trench 56 in the direction orthogonal to the gate width (left-right direction in FIG. 5). An N ⁺ type source region 59 having a concentration (for example, 10 ¹⁹ / cm ³ ) is formed. The source region 59 extends along the gate width along the gate trench 56, and the bottom thereof is in contact with the body region 55. A P ⁺ -type source contact region 60 is formed through the source region 59 at the center of the source region 59 in the direction orthogonal to the gate width.

  That is, the gate trenches 56 and the source regions 59 are alternately provided in a direction orthogonal to the gate width, and extend in a direction along the gate width. A boundary between adjacent unit cells is set on the source region 59 along the source region 59 in a direction orthogonal to the gate width. At least one source contact region 60 is provided across two unit cells adjacent in the direction orthogonal to the gate width. The boundary between unit cells adjacent in the direction along the gate width is set so that the gate electrode 58 included in each unit cell has a constant gate width.

  An interlayer insulating film 63 is stacked on the epitaxial layer 53. A source wiring 64 is formed on the interlayer insulating film 63. The source wiring 64 is grounded. The source wiring 64 is in contact (electrically connected) to the source region 59 and the source contact region 60 through a source plug 68 embedded in a contact hole 65 formed in the interlayer insulating film 63. A gate wiring 66 is formed on the interlayer insulating film 63. The gate wiring 66 is in contact (electrically connected) to the gate electrode 58 through a gate plug 62 embedded in a contact hole 61 formed in the interlayer insulating film 63.

A drain electrode 87 is formed on the back surface of the N ⁺ type substrate 52.
A channel is formed in the vicinity of the interface with the gate insulating film 57 in the body region 55 (channel formation region 92) by controlling the potential of the gate electrode 58 while applying an appropriate positive voltage to the drain electrode 87. Thus, a current can flow between the source region 59 and the drain electrode 87.

In this semiconductor device 51, an intrinsic semiconductor region 67 is formed in the epitaxial layer 53 at a portion from the bottom surface of the gate trench 56 to the bottom portion of the N ⁻ -type region 54. Therefore, for example, as in the semiconductor device 100 shown in FIG. 9, N ⁻ type region 54 and body region 55 are compared with the conventional configuration in which N ⁻ type region 103 having a uniform N type impurity concentration is formed. The thickness of the depletion layer 88 extending from the interface of the gate trench 56 from the bottom surface can be increased. Therefore, the gate-drain voltage applied to the gate insulating film 57 when a voltage is applied to the drain electrode 87 can be reduced. As a result, the thickness of the gate insulating film 57 can be reduced, so that the channel resistance R _ch4 in the channel formation region 92 can be reduced and the on-resistance R _on4 of the semiconductor device 51 can be reduced.

For example, comparing the on-resistance R _on4 on-resistance R _on3 the semiconductor device 51 of the semiconductor device 100 shown in FIG. The symbols used in this comparison are defined as follows.
Voltage V _d: drain electrode 114 and the drain voltage a voltage is applied to the drain electrode 87 V _ox1: Voltage V Voltage Voltage is applied to the gate insulating film 57 by the application of _d V _ox2: gate insulating by applying a voltage V _d film 106 Width T _dep1 : The thickness of the depletion layer 88 that spreads in the semiconductor device 51 by applying the voltage V _d Width T _dep2 : The thickness of the depletion layer 115 that spreads in the semiconductor device 100 by applying the voltage V _d Capacitance C _ox1 : Parasitic capacitance generated between the gate electrode 58 facing the gate insulating film 57 and the bottom surface of the gate trench 56 Capacitance C _ox2 : Bottom surface of the gate electrode 107 and the gate trench 105 facing the gate insulating film 106 Capacitance C _dep1 : parasitic capacitance of the depletion layer 88 capacitance C _dep2 : parasitic capacitance of the depletion layer 115 in the semiconductor device 100 The voltage V _ox2 is expressed by V _ox2 = C _dep2 · V _d / (C _dep2 + C _ox2 ). On the other hand, in the semiconductor device 51, the voltage V _ox1 is expressed by V _ox1 = C _dep1 · V _d / (C _dep1 + C _ox1 ).

When C _ox2 = C _dep2 = C _ox1 and T _dep1 = 4T _dep2 and C _dep1 = C _dep2 / 4 due to the formation of the intrinsic semiconductor region 67, the voltage V _ox2 in the semiconductor device 100 is V _ox2 = V _d / 2.
On the other hand, the voltage V _ox1 = V _d / 5 in the semiconductor device 51 is obtained. Thus, it can be seen that the voltage V _ox1 is smaller between V _ox1 applied to the gate insulating film 57 and the voltage V _ox2 applied to the gate insulating film 106.

That is, since the intrinsic semiconductor region 67 is formed, the gate-drain voltage applied to the gate insulating film 57 when a voltage is applied to the drain electrode 87 can be reduced. As a result, the thickness of the gate insulating film 57 can be reduced, so that the channel resistance R _ch4 in the channel formation region 92 can be reduced and the on-resistance R _on4 can be reduced.

6A to 6M are cross-sectional views illustrating the method of manufacturing the semiconductor device 51 in the order of steps.
First, as shown in FIG. 6A, an epitaxial layer 53 is formed on an N ⁺ type substrate 52 by an epitaxial growth method. Next, as shown in FIG. 6B, a sacrificial oxide film 81 made of SiO ₂ is formed on the surface of the epitaxial layer 53 by thermal oxidation. Thereafter, a SiN (silicon nitride) layer is formed on the sacrificial oxide film 81 by a P-CVD (Plasma Chemical Vapor Deposition) method or an LP-CVD (Low Pressure Chemical Vapor Deposition) method. The SiN layer is patterned to form a hard mask 82 having an opening in a portion facing the portion where the trench 89 is to be formed. Then, by using the hard mask 82, the sacrificial oxide film 81 and the epitaxial layer 53 are etched to form a trench 89 (step of forming a trench).

  Next, as shown in FIG. 6C, Si containing no impurities is deposited on the epitaxial layer 53 by the CVD method. Si is deposited until the trench 89 is filled and the epitaxial layer 53 is covered. As a result, a low-concentration material deposition layer 69 that does not contain impurities (N-type impurity concentration is lower than that of the epitaxial layer 53) is formed in the trench 89 and on the epitaxial layer 53.

  After the low-concentration material deposition layer 69 is formed, as shown in FIG. 6D, a portion existing outside the trench 89 of the low-concentration material deposition layer 69 is removed by CMP (Chemical Mechanical Polishing). The Next, the low-concentration material deposition layer 69 embedded in the trench 89 is partially removed by dry etching using the sacrificial oxide film 81 and the hard mask 82 as a mask.

  As a result, as shown in FIG. 6E, an intrinsic semiconductor region 67 that forms part of the epitaxial layer 53 is formed at the bottom of the trench 89 (step of embedding a semiconductor material). Further, due to the formation of the intrinsic semiconductor region 67, the portion above the intrinsic semiconductor region 67 in the trench 89 becomes the gate trench 56. After the intrinsic semiconductor region 67 is formed, the sacrificial oxide film 81 and the hard mask 82 are removed.

Next, as shown in FIG. 6F, by performing a thermal oxidation process, an oxide film 83 made of SiO ₂ is formed over the entire surface of the epitaxial layer 53 including the inner surface of the gate trench 56 (an oxide film is formed). Forming step).
Next, a polysilicon deposition layer doped with N-type impurities at a high concentration is formed on the oxide film 83 by CVD. The inside of the gate trench 56 is filled with a deposited layer of polysilicon. Then, the portion of the polysilicon deposition layer existing outside the gate trench 56 is removed by etching. Thereby, as shown in FIG. 6G, the gate electrode 58 embedded in the gate trench 56 is obtained (step of forming the gate electrode).

Thereafter, ions of P-type impurities are implanted from the surface of the oxide film 83 toward the inside of the epitaxial layer 53. Next, drive-in diffusion processing is performed. By this drive-in diffusion treatment, ions of the P-type impurity implanted into the epitaxial layer 53 are diffused, and as shown in FIG. 6H, a body region 55 is formed in the epitaxial layer 53 (step of forming a body region). . Further, the portion other than the body region 55 in the epitaxial layer 53 becomes the N ⁻ -type region 54 as it is after the epitaxial growth.

After the drive-in diffusion process, as shown in FIG. 6I, a mask 85 having an opening in a portion facing the portion where the source region 59 is to be formed is formed on the oxide film 83. Then, ions of N-type impurities are implanted into the surface layer portion of the epitaxial layer 53 through the opening of the mask 85. After this ion implantation, the mask 85 is removed.
Further, as shown in FIG. 6J, a mask 86 having an opening in a portion facing the portion where the source contact region 60 is to be formed is formed on the oxide film 83. Then, ions of P-type impurities are implanted into the surface layer portion of the epitaxial layer 53 through the opening of the mask 86. After this ion implantation, the mask 86 is removed.

Thereafter, an annealing process is performed. By this annealing treatment, ions of N-type impurities and P-type impurities implanted into the surface layer portion of the epitaxial layer 53 are activated, and the source region 59 and the source contact are formed on the surface layer portion of the epitaxial layer 53 as shown in FIG. 6K. Region 60 is formed (step of forming a source region).
After the above steps, the portion of the oxide film 83 that is outside the gate trench 56 is removed, and the oxide film 83 is left only on the inner surface of the gate trench 56, whereby the gate insulating film 57 is obtained.

Thereafter, SiO ₂ is deposited on the epitaxial layer 53 by the CVD method. Next, on the deposited SiO ₂ , a mask 70 having an opening at a portion facing the portion where the contact hole 61 and the contact hole 65 are to be formed is formed, and the SiO ₂ is dry etched using the mask 70. . Thereby, as shown in FIG. 6L, an interlayer insulating film 63 in which the contact hole 61 and the contact hole 65 are formed is formed.

As shown in FIG. 6M, a gate plug 62 is embedded in the contact hole 61, a gate wiring 66 is formed on the gate plug 62, and a source plug 68 is embedded in the contact hole 65. A source wiring 64 is formed thereon. A drain electrode 87 is formed on the back surface of the N ⁺ type substrate 52. Thereby, the semiconductor device 51 shown in FIG. 5 is obtained.

FIG. 7 is a schematic cross-sectional view of a semiconductor device according to a second reference example of the present invention. In FIG. 7, portions corresponding to the respective portions shown in FIG. 5 are denoted by the same reference numerals as those of the respective portions. Further, in the following, detailed description of the parts denoted by the same reference numerals is omitted.
In this semiconductor device 91, the N ⁻ -type region 54 of the epitaxial layer 53 is located at the bottom of the N ⁻ -type region 54 from the bottom surface of the gate trench 56 (position away from the top surface of the N ⁺ -type substrate 52 by a predetermined distance). A P ⁻ -type P ⁻ -type impurity-containing region 84 (low concentration region) is formed in the entire portion. The P ⁻ -type impurity-containing region 84 is a region where the N ⁻ -type region 54 contains a P-type impurity. That is, the N ⁻ type region 54 is a region having a lower N type impurity concentration than the remaining portion other than the P ⁻ type impurity containing region 84.

Further, the P ⁻ type impurity containing region 84 has, for example, a width W ₃ equal to the width W ₁ of the gate trench 56. The impurity concentration and thickness T _a2 of the P ⁻ -type impurity-containing region 84 are, for example, an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ and a thickness Ta _{2 of} 1 μm to 10 μm. The impurity concentration is preferably 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ and the thickness Ta ₂ is preferably 1 μm to 5 μm. More specifically, it is preferable that the impurity concentration is 1 × 10 ¹⁶ cm ⁻³ and the thickness T _a is 4 μm, and the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ and the thickness T _a2 is 1 μm. .

Also with this configuration, in the epitaxial layer 53, the P ⁻ -type impurity containing region 84 is formed in the portion from the bottom surface of the gate trench 56 to the bottom of the N ⁻ -type region 54, so that the N-type impurity concentration is uniform. Compared to the conventional configuration in which the N ⁻ -type region 103 is formed, the thickness T _dep3 of the depletion layer 90 extending from the interface between the N ⁻ -type region 54 and the body region 55 can be increased. As a result, the gate-drain voltage applied to the gate insulating film 57 when a voltage is applied to the drain electrode 87 can be reduced. As a result, the thickness of the gate insulating film 57 can be reduced, so that the channel resistance R _ch5 in the channel formation region 92 can be reduced and the on-resistance R _on5 of the semiconductor device 91 can be reduced.

The semiconductor device 91 can be manufactured by a method similar to the method described with reference to FIGS. 6A to 6M. In the manufacture of the semiconductor device 91, in the step shown in FIG. 6C, Si is deposited on the epitaxial layer 53 while adding (doping) the P-type impurity, and the low-concentration material deposition layer containing the P-type impurity is contained. 69 may be formed.
Although a plurality of embodiments and reference examples of the present invention have been described above, the present invention and reference examples can also be implemented in other forms.

For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1, the semiconductor device 31, and the semiconductor device 51 is reversed may be employed. That is, in the semiconductor device 1, the semiconductor device 31, and the semiconductor device 51, the P-type portion may be N-type and the N-type portion may be P-type.
In the semiconductor device 31, the bottom 36 of the gate insulating film 35 may have a two-layer structure including a lower layer film made of SiO ₂ and an upper layer film made of SiN. In this case, the lower layer film and the upper layer film can be manufactured by a method similar to the method for manufacturing the semiconductor device 1.

In the semiconductor device 51, for example, a region formed in a portion extending from the bottom surface of the gate trench 56 to the bottom portion of the N ⁻ -type region 54 (a position away from the top surface of the N ⁺ -type substrate 52 by a predetermined distance) An N 2 ⁻ type semiconductor region may be used as long as the N-type impurity concentration is lower than the remaining portion other than the region. In order to form the N 2 ⁻ type semiconductor region, for example, Si having an N type impurity concentration lower than that of the epitaxial layer 53 may be deposited on the epitaxial layer 53 in the step shown in FIG. 6C.

  In the semiconductor device 51, the gate insulating film 57 is opposed to the body region facing portion 96 facing the body region 55 in the epitaxial layer 53 and the source region 59, as shown in FIG. A source region facing portion 95 having a film thickness thicker than the portion 96 may be included. In such a gate insulating film 57, for example, as shown in the first embodiment, the source region 59 and the body region 55 may be formed in the epitaxial layer 53 before the gate insulating film 57 is formed.

Source region 59 has a higher impurity concentration than body region 55 and is oxidized at a higher oxidation rate than body region 55. Therefore, the gate insulating film 57 having the source region facing portion 95 and the body region facing portion 96 having different thicknesses as described above can be formed.
In addition to the invention described in the claims, the following features can be extracted from the description of the specification and the drawings.
Item 1. A semiconductor layer, a first conductivity type impurity containing a first conductivity type impurity and formed in a base layer portion of the semiconductor layer; a first conductivity type region formed in the semiconductor layer; and in contact with the first conductivity type region A body region of a second conductivity type, a trench formed in the semiconductor layer, penetrating through the body region, and having a deepest portion reaching the first conductivity type region, and formed around the trench in a surface layer portion of the semiconductor layer A first conductivity type source region in contact with the body region, a gate insulating film formed on a bottom surface and a side surface of the trench, and a gate electrode embedded in the trench through the gate insulating film. In the first conductivity type region, the portion from the bottom surface of the trench to the middle part in the thickness direction of the first conductivity type region has a lower first conductivity type impurity concentration than the remaining portion other than the portion. concentration It is a band, the semiconductor device.
According to this configuration, the semiconductor layer is formed with a trench that penetrates the body region and has the deepest portion reaching the first conductivity type region. A gate insulating film is formed on the bottom and side surfaces of the trench, and the gate electrode is embedded in the trench through the gate insulating film.
In the first conductivity type region, the portion from the bottom surface of the trench to the middle portion in the thickness direction of the first conductivity type region is a low concentration region having a lower first conductivity type impurity concentration than the remaining portion of the portion. .
Therefore, the first conductivity type region is compared with the conventional configuration (for example, see FIG. 9) in which the first conductivity type region having a uniform first conductivity type (for example, N type) impurity concentration is formed below the trench. The thickness in the thickness direction of the first conductivity type region of the depletion layer extending below the trench from the interface between the first region and the body region can be increased.
By increasing the thickness of the depletion layer, the gate-drain voltage applied to the gate insulating film can be reduced. As a result, the thickness of the gate insulating film can be reduced, so that the on-resistance of the semiconductor device can be reduced.
The low concentration region is, for example, an intrinsic semiconductor region that does not contain the first conductivity type impurity if the first conductivity type impurity concentration is lower than the remaining portion of the first conductivity type region other than the low concentration region. Alternatively, the second conductivity type impurity may be included. In particular, the structure containing the second conductivity type impurity is preferable because a depletion layer is formed at the junction interface between the first conductivity type region and the low concentration region.
The semiconductor device having the structure as described in item 1 includes a step of forming a trench in the first conductivity type semiconductor layer, and a first conductivity lower than the first conductivity type impurity concentration of the semiconductor layer at the bottom of the trench. A step of embedding a semiconductor material having a type impurity concentration, a step of oxidizing the surface of the semiconductor layer including the side surface of the trench and the surface of the semiconductor material to form an oxide film, and the trench on the oxide film Forming a gate electrode, introducing a second conductivity type impurity from the surface of the semiconductor layer to form a body region of the second conductivity type, and a surface of the semiconductor layer Introducing the first conductivity type impurity into the periphery of the trench to form the first conductivity type source region in contact with the body region, and a portion of the oxide film outside the trench It was removed, on the bottom and sides of the trench, and forming a gate insulating film can be obtained by the method of manufacturing a semiconductor device.
In the semiconductor device according to item 1, it is preferable that the gate insulating film has a thickness of a portion adjacent to the source region on a side surface of the trench larger than a thickness of a portion facing the body region.
If the thickness of the portion of the gate insulating film adjacent to the source region on the side surface of the trench is thicker than the thickness of the portion facing the body region, the gate electrode is increased without increasing the on-resistance of the semiconductor device. And parasitic capacitance generated between the source region and the source region can be reduced. Therefore, the gate capacitance can be further reduced, and the gate charge amount can be further reduced. As a result, a much faster switching operation can be achieved.
In addition, various design changes can be made within the scope of matters described in the claims.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device of FIG. It is sectional drawing which shows the next process of FIG. 2A. It is sectional drawing which shows the next process of FIG. 2B. It is sectional drawing which shows the process following FIG. 2C. It is sectional drawing which shows the next process of FIG. 2D. It is sectional drawing which shows the process following FIG. 2E. It is sectional drawing which shows the next process of FIG. 2F. It is sectional drawing which shows the next process of FIG. 2G. It is sectional drawing which shows the next process of FIG. 2H. FIG. 2D is a cross-sectional view showing a step subsequent to FIG. 2I. It is typical sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 4 is a cross-sectional view showing a method of manufacturing the semiconductor device of FIG. FIG. 4B is a cross-sectional view showing a step subsequent to FIG. 4A. FIG. 4B is a cross-sectional view showing a step subsequent to FIG. 4B. FIG. 4D is a cross-sectional view showing a step subsequent to FIG. 4C. FIG. 4D is a cross-sectional view showing a step subsequent to FIG. 4D. It is sectional drawing which shows the process following FIG. 4E. FIG. 4D is a cross-sectional view showing a step subsequent to FIG. 4F. FIG. 4D is a cross-sectional view showing a step subsequent to FIG. 4G. It is sectional drawing which shows the process following FIG. 4H. FIG. 4D is a cross-sectional view showing a step subsequent to FIG. 4I. FIG. 4D is a cross-sectional view showing a step subsequent to FIG. 4J. It is a typical sectional view of a semiconductor device concerning the 1st reference example of the present invention. FIG. 6 is a cross-sectional view showing a method of manufacturing the semiconductor device of FIG. 5 in the order of steps. FIG. 6B is a cross-sectional view showing a step subsequent to FIG. 6A. FIG. 6B is a cross-sectional view showing a step subsequent to FIG. 6B. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6C. It is sectional drawing which shows the process of FIG. 6D. FIG. 6E is a cross-sectional view showing a step subsequent to FIG. 6E. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6F. FIG. 6G is a cross-sectional view showing a step subsequent to FIG. 6G. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6H. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6I. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6J. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6K. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6L. It is a typical sectional view of a semiconductor device concerning the 2nd reference example of the present invention. FIG. 6 is a schematic cross-sectional view showing a modification of the semiconductor device in FIG. 5. It is typical sectional drawing of the semiconductor device which has the conventional trench gate type VDMOSFET. 10 is a graph showing the relationship between the on-resistance R _on3 and the gate charge amount Q _g3 of the _VDMOSFET shown in FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Body region 4 N < ^- > type layer 5 Body layer 6 Gate trench 7 Gate insulating film 8 Gate electrode 9 Source region 10 Contact region 17 N < ^- > type layer 19 N < ^- > type layer 21 Trench 22 N < ^- > type layer 23 N < ^- > Type layer 24 P-type impurity containing region 31 Semiconductor device 32 First insulating layer 33 Second insulating layer 34 Third insulating layer 35 Gate insulating film 36 Bottom portion 37 Top portion 38 Source region facing portion 39 Body region facing portion 40 Insulating layer 41 N ⁻ Type layer 42 Oxide film 43 Source region facing portion 44 Body region facing portion 50 Insulating layer 51 Semiconductor device 53 Epitaxial layer 54 N ⁻ type region 55 Body region 56 Trench 57 Gate insulating film 58 Gate electrode 59 Source region 60 Source contact region 67 Intrinsic Semiconductor region 69 Low-concentration material deposition layer 71 Bottom portion 72 Upper portion 73 Lower layer 74 upper film 75 source region opposed portion 76 the body region opposed portion 84 P ^- -type impurity-containing region 91 the semiconductor device 95 source region opposed portion 96 the body region opposed portion 4A top 8A bottom 17A exposed surface 22A upper surface 23A exposed surface

Claims (7)

Forming an insulating layer having a predetermined pattern on one surface of the first semiconductor layer of the first conductivity type;
Growing a second semiconductor layer of the first conductivity type on an exposed surface of the first semiconductor layer;
Growing a second conductivity type body layer on the second semiconductor layer;
Introducing the first conductivity type impurity from the surface of the body layer to the periphery of the insulating layer to form the first conductivity type source region;
Removing the insulating layer until the upper surface thereof is flush with the upper surface of the second semiconductor layer to form a trench, and leaving the bottom of the insulating layer as a part of the gate insulating film; ,
Oxidizing the surface of the body layer including the side surface of the trench to form an oxide film constituting a gate insulating film together with the bottom of the insulating layer;
Forming a gate electrode on the gate insulating film so as to fill the trench.   In the step of forming the gate insulating film, the oxide film is formed to be thinner than the insulating layer remaining as a part of the gate insulating film, so that the film thickness of the portion covering the bottom surface of the trench is 2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a gate insulating film thicker than a film thickness of a portion facing the body layer on a side surface of the trench.   The step of forming the source region includes the step of forming the source region with an impurity concentration higher than that of the body region,
  The step of forming the gate insulating film uses a difference in oxidation rate based on a difference in impurity concentration between the source region and the body region to form a film thickness of a portion adjacent to the source region on the side surface of the trench. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a gate insulating film thicker than a film thickness of a portion of the body layer that faces the body region excluding the source region.   The step of forming the insulating layer includes a step of forming an insulating layer having a two-layer structure in which a lower layer film made of silicon oxide and an upper layer film made of silicon nitride are sequentially stacked,
  The method for manufacturing a semiconductor device according to claim 1, wherein the step of removing the insulating layer includes a step of removing the insulating layer so that at least the two-layer structure remains. Forming an insulating layer having a predetermined pattern on one surface of the first semiconductor layer of the first conductivity type;
Growing a second semiconductor layer of the first conductivity type on an exposed surface of the first semiconductor layer;
Growing a second conductivity type body layer on the second semiconductor layer;
Introducing the first conductivity type impurity from the surface of the body layer to the periphery of the insulating layer to form the first conductivity type source region;
Removing the insulating layer, forming a gate trench penetrating the body layer and having a deepest portion reaching the first semiconductor layer;
Introducing the second conductivity type impurity into the first semiconductor layer from the bottom surface of the gate trench;
Oxidizing the bottom and side surfaces of the gate trench and the upper surface of the body layer to form a gate insulating film having an upper surface located on the same plane as the upper surface of the second semiconductor layer in the gate trench;
Forming a gate electrode on the gate insulating film so as to fill the gate trench.   The step of introducing the second conductivity type impurity from the bottom surface of the gate trench introduces the impurity such that the second conductivity type impurity region formed by the introduction of the impurity has a higher impurity concentration than the body region. Including the steps of:
  The step of forming the gate insulating film uses a difference in oxidation rate based on a difference in impurity concentration between the second conductivity type impurity region and the body region to form a film thickness of a portion covering the bottom surface of the gate trench. The method of manufacturing a semiconductor device according to claim 5, further comprising forming a gate insulating film thicker than a thickness of a portion facing the body layer on a side surface of the gate trench.   The step of forming the source region includes the step of forming the source region with an impurity concentration higher than that of the body region,
  The step of forming the gate insulating film uses a difference in oxidation rate based on a difference in impurity concentration between the source region and the body region to form a film adjacent to the source region on the side surface of the gate trench. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of forming a gate insulating film having a thickness larger than a thickness of a portion of the body layer that faces the body region excluding the source region.

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