JP5374505B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a SGT (Surrounding Gate Transistor), which is a vertical MOS transistor having a columnar semiconductor layer, a side wall of which is a channel region, and a gate electrode surrounding the channel region. The present invention relates to a structure and a manufacturing method thereof.

In order to realize high integration and high performance of LSI, a columnar semiconductor layer is formed on the surface of a semiconductor substrate, and an SGT (vertical gate transistor having a gate formed so as to surround the columnar semiconductor layer on a sidewall thereof. (Surrounding Gate Transistor) has been proposed (for example, Patent Document 1: JP-A-2-188966). In the SGT, since the drain, gate, and source are arranged in the vertical direction, the occupied area of the transistor can be greatly reduced as compared with the conventional planar type transistor.

FIG. 37 shows a bird's-eye view (a) and a cross-sectional structure (b) of the SGT of Patent Document 1. The SGT will be described with reference to these drawings. A columnar silicon layer 501 is formed on a silicon substrate, a gate insulating film 502 is formed so as to surround the columnar silicon layer 501, and a gate electrode 503 is formed so as to surround the gate insulating film 502. The side surface of the columnar silicon layer 501 with the gate electrode formed around it becomes a channel of the transistor. A lower diffusion layer 504 and an upper diffusion layer 505 which are source / drain regions are formed above and below the columnar silicon layer 501. Upper diffusion layer 505 is connected to the wiring layer through a contact.

JP 2-188966

However, when the SGT of Patent Document 1 shown in FIG. 37 is applied to a highly integrated and high-performance logic device such as a CPU, a silicide layer is formed in a self-aligned manner in the source / drain region in order to improve transistor performance. However, it is necessary to reduce the parasitic resistance of the source / drain region. On the other hand, it is important that the occupied area of the SGT does not increase by improving the transistor performance.

The present invention has been made in view of the above circumstances, and by reducing the thickness of the silicon nitride film on the outer periphery of the gate electrode of the SGT, the circuit occupation area formed by the SGT and the SGT, particularly the SGT as in the SRAM, An object is to reduce the occupied area in a circuit in which contacts are arranged at a minimum interval.

In order to solve the above problems, the present invention has the following configuration. According to one feature of the present invention, a semiconductor device configured using a MOS transistor,
The MOS transistor has a structure in which a drain, a gate, and a source are arranged in a direction perpendicular to a substrate, and the gate surrounds a columnar semiconductor layer,
A silicide layer formed in a self-aligned manner on each of the diffusion layers disposed above and below the columnar semiconductor layer for protecting the sidewall of the columnar semiconductor layer when the silicide layer is formed. And a silicide layer formed after forming the first insulating film on the side wall of the columnar semiconductor layer;
After forming the silicide layer and removing the first insulating film, a source or drain region formed below the columnar semiconductor layer and a gate electrode formed on the sidewall of the columnar semiconductor layer and an upper portion of the columnar semiconductor layer A second insulating film formed to cover the source or drain region formed in
There is provided a semiconductor device including a third insulating film that covers the second insulating film as an interlayer film.
In a preferred aspect of the present invention, in the semiconductor device, the thickness Ts of the first portion in the second insulating film covering the sidewall and the gate electrode of the columnar semiconductor layer and the first and lower portions of the columnar semiconductor layer are covered. the thickness Tt of the second portion of the second insulating film is substantially the same, have a relationship of 0.8Tt <Ts <1.2T t.
In another preferable aspect of the present invention, in the semiconductor device, the thickness Ts of the first portion in the second insulating film covering the sidewall and the gate electrode of the columnar semiconductor layer and the upper and lower portions of the columnar semiconductor layer are the thickness Tt of the second portion in the second insulating film covering has a relationship 0.5Tt <Ts <1.0T t.
In another preferable aspect of the present invention, in the semiconductor device, the thickness Ts of the first portion in the second insulating film covering the sidewall and the gate electrode of the columnar semiconductor layer and the upper and lower portions of the columnar semiconductor layer are the thickness Tt of the second portion in the second insulating film covering has a relationship 0.25Tt <Ts <0.5T t.
In another preferable aspect of the present invention, in the semiconductor device, the second insulating film is a silicon nitride film, and the third insulating film is a silicon oxide film.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a MOS transistor having a structure in which a drain, a gate, and a source are arranged in a vertical direction, and the gate surrounds a columnar semiconductor layer. And
Etching the silicon substrate to form a columnar semiconductor layer;
Forming a gate insulating film on the surface of each diffusion layer of the source region or drain region formed above and below the columnar semiconductor layer and the side wall of the columnar semiconductor layer;
Forming a gate conductive film on the surface of the gate insulating film;
Etching each of the gate insulating film and the gate conductive film to form a gate electrode;
A first insulating film is formed on the side wall of the columnar semiconductor layer to protect the side wall of the columnar semiconductor layer when a silicide layer is formed in a self-aligned manner on the diffusion layers disposed above and below the columnar semiconductor layer. And a process of
Forming a silicide layer on each of the diffusion layers disposed above and below the columnar semiconductor layer in a self-aligning manner;
Removing the first insulating film after the silicide layer is formed;
Forming a second insulating film on the columnar semiconductor layer and the gate electrode as a contact stopper;
And a step of forming a third insulating film as an interlayer film on the second insulating film.
In a preferred aspect of the present invention, in the method of manufacturing the semiconductor device, the first and second insulating films are silicon nitride films, and the third insulating film is a silicon oxide film.

Examples of the present invention using a single SGT are shown below.

1A is a plan view of the SGT, and FIG. 1B is a cross-sectional view. The SGT of this embodiment will be described with reference to these drawings. A columnar semiconductor layer 101 is formed on a silicon substrate, a gate insulating film 102 is formed so as to surround the columnar semiconductor layer 101, and a gate electrode 103 is formed so as to surround the gate insulating film 102. A side surface of the columnar semiconductor layer 101 around which the gate electrode is formed becomes a channel portion of the transistor. A lower diffusion layer 104 and an upper diffusion layer 105 which are source / drain regions are formed above and below the columnar semiconductor layer 101, a silicide layer 107 is formed on the lower diffusion layer, and a silicide layer 108 is formed on the upper diffusion layer. It is formed. A contact stopper nitride film 109 is formed so as to cover the columnar semiconductor layer and the gate, and the upper diffusion layer 105 is connected to the contact 110.
In the SGT of the present embodiment, the spacer made of a nitride film covering the gate necessary for forming the silicide is removed, and the nitride film covering the gate is only the contact stopper nitride film 109, so the area of one SGT is The size is kept to the minimum necessary size.

The manufacturing method for forming SGT of a present Example is shown below.

As shown in FIG. 2, the columnar semiconductor layer 101 is formed by etching the silicon substrate.

As shown in FIG. 3, a gate insulating film 102 and a gate conductive film 103 are formed.

As shown in FIG. 4, after forming a gate conductive film on the surface of the gate insulating film, each of the gate insulating film and the gate conductive film is etched to form the gate electrode 103.

As shown in FIG. 5, the lower diffusion layer 104 and the upper diffusion layer 105 are formed by ion implantation.

As shown in FIG. 6, a silicon nitride film is formed and etched back. By covering the side wall portion and gate electrode of the columnar semiconductor layer with the silicon nitride film 106, silicide can be formed on the source / drain diffusion layer in a self-aligned manner, silicidation from the side wall of the columnar semiconductor layer, and the gate electrode. In addition, a short circuit through silicide between the diffusion layers can be suppressed.
Note that the insulating film formed in this step is preferably a silicon nitride film that does not dissolve in hydrofluoric acid used as a silicide pretreatment.

As shown in FIG. 7, after sputtering a metal such as Co or Ni, heat treatment is performed to remove the unreacted metal, thereby forming silicide layers (107, 107 only on the lower diffusion layer 104 and the upper diffusion layer 105). 108) in a self-aligning manner.

As shown in FIG. 8, the silicon nitride film spacer 106 formed before silicidation is removed by wet etching. In this step, the area occupied by the SGT can be reduced by removing the silicon nitride film spacer 106 formed on the gate electrode.

As shown in FIG. 9, a silicon nitride film 109 for contact stopper is formed. Subsequently, a silicon oxide film as an interlayer film is formed.

As shown in FIG. 10, a contact 110 is formed.

As described in the description of the manufacturing process, the present invention is characterized in that after the silicide layer is formed on the source / drain diffusion layer, the silicon nitride film spacer formed on the gate electrode is removed to remove the area occupied by the SGT. The distance between SGTs and the distance between SGTs and contacts can be reduced. In the conventional SGT, unlike the planar transistor manufacturing process, the area occupied by the SGT is increased by the film thickness of the insulating film covering the gate after the gate is formed. As a result, the circuit occupied area is increased. In the present invention, attention is paid to this point, and the structure is such that the insulating film finally formed on the outer periphery of the gate electrode is only the silicon nitride film for the contact stopper.

FIG. 11 shows a plan view (a) and a sectional view (b) of the SGT when the present invention is used, and a plan view (c) and a section (d) of the SGT when the conventional technique is used. When the present invention is not used, the nitride film spacer 126 is not removed and exists inside the silicon nitride film 129 for contact stopper. For this reason, the occupation area of SGT becomes large.

For example, when the nitride film spacer film thickness is 30 nm, the interval between the SGT and the contact can be reduced by 30 nm by using the present invention. Usually, in the logic circuit portion, in order to reduce the area, many contacts are arranged with a minimum distance from the SGT. Therefore, by using the present invention, the area of the logic circuit can be reduced.

This embodiment is an embodiment for reducing the occupied area of the SGT by adjusting the film formation method and structure of the contact stopper nitride film.
FIG. 12A shows a plan view of a single SGT in this embodiment, and FIG. 12B shows a cross-sectional view.
In this embodiment, the difference from Embodiment 1 is that, in the present invention, regarding the shape of the contact stopper nitride film, the upper and lower portions of the columnar semiconductor layer actually used as the contact stopper are lower than the film thickness formed on the gate electrode. The point is that the film thickness formed on the diffusion layer is thick. By forming the contact stopper nitride film as described above, it is possible to provide a function as a contact stopper without increasing the occupied area of the SGT.

In a conventional planar transistor, the contact stopper nitride film is often formed under film forming conditions with good coverage. However, when a film with good coverage is used in SGT, there is a problem that the area in the lateral direction increases. In the present invention, the film thickness in the vertical direction can be sufficiently ensured by suppressing the film thickness in the horizontal direction as described above. Such a structure of the nitride film can be realized by film formation by sputtering, film formation by reaction rate control using CVD, or film formation by a combination of sputtering and CVD.

When the thickness of the contact stopper nitride film formed around the gate electrode is Ts and the thickness of the contact stopper nitride film formed on the upper silicide layer is Tt, normally 0.8Tt <Ts <1.2Tt It holds. In order to suppress an increase in the area occupied by the SGT, it is desirable to adjust the film formation conditions of the contact stopper nitride film so that the nitride film has a shape satisfying the relationship of 0.5Tt <Ts <1.0Tt. In this case, an increase in area can be suppressed while maintaining the nitride film thickness Tt on the upper silicide layer. When the relationship of 0.25 Tt <Ts <0.5 Tt is established, an increase in area can be further suppressed.

In the following, an embodiment of an SRAM cell in which the effects of using the present invention can be easily evaluated quantitatively will be shown. In particular, in this embodiment, the effects of the present invention will be shown by taking as an example a CMOS type 6T-SRAM using SGT formed on an SOI substrate.
First, FIG. 13 shows an equivalent circuit diagram of the memory cell of the CMOS type 6T-SRAM used in this embodiment. In FIG. 13, BL1 and BLB1 are bit lines, WL1 is a word line, Vcc1 is a power supply potential, Vss1 is a ground potential, Qn11 and Qn21 are access transistors for accessing the memory cells, and Qn31 and Qn41 are drivers for driving the memory cells. Transistors, Qp11 and Qp21 are load transistors for supplying charges to the memory cells, and Qa and Qb are storage nodes for storing data.

As an example of the operation of the memory cell in FIG. 13, a read operation in the case where “L” data is stored in the storage node Qa and “H” data is stored in the storage node Qb will be described below. When reading is performed, the bit lines BL1 and BLB1 are precharged to the “H” potential. When the word line WL1 becomes “H” after the precharge is completed, the access transistors Qn11 and Qn21 are turned on, and the potential of the bit line BL1 which is “H” is a value at which the storage node Qb is close to the “H” potential. Therefore, the driver transistor Qn31 is turned on and discharged from the access transistor Qn11 through the storage node Qa and the driver transistor Qn31, and approaches the “L” potential. On the other hand, the potential of the bit line BLB1 is “H” because the storage node Qa is close to the “L” potential, so that the driver transistor Qn41 is off and is not discharged, but conversely, the charge is supplied from the load transistor Qp21. “It remains close to the potential. When the potential difference between BL1 and BLB1 reaches a level that can be amplified by the sense amplifier, the sense amplifier connected to the bit line is activated, but the data in the memory cell is amplified and output. The

FIG. 14 shows a layout diagram of an SRAM memory cell as an embodiment of the present invention. FIG. 14B is a diagram in which the wiring layer is deleted from FIG. 14A for easy viewing. The unit cells shown in FIG. 14 are repeatedly arranged in the SRAM cell array. FIGS. 15A to 15D show cross-sectional structures along cut lines A-A ′ to D-D ′ in the layout diagram of FIG. 14.

The layout of the present embodiment will be described below with reference to FIGS.
Planar silicon layers (302a, 302b) are formed on the buried oxide film layer (BOX) 301. The planar silicon layers (302a, 302b) are formed by N + diffusion layers (303a, 303b, 305a, 305b) by impurity implantation or the like. ) And P + diffusion layers (304a, 304b), and the N + diffusion layer and the P + diffusion layer formed on the same planar silicon layer are silicide layers (302a, 302b) formed on the surface of the planar silicon layer (302a, 302b). 313a and 313b). The planar silicon layers (302a, 302b) function as storage nodes (Qa, Qb), respectively. Qn11 and Qn21 are access transistors for accessing the memory cell that is NMOS, Qn31 and Qn41 are driver transistors that drive the memory cell that is NMOS, and Qp11 and Qp21 are load transistors that supply charges to the memory cell that is PMOS. . Contact 310a formed on planar silicon layer 302a is connected to contact 311b formed on the gate wiring extending from the gate electrodes of driver transistor Qn41 and load transistor Qp21 by node connection wiring Na1, and planar silicon layer 302b. Contact 310b formed above is connected to contact 311a formed on the gate wiring extending from the gate electrodes of driver transistor Qn31 and load transistor Qp11 by node connection wiring Nb1. Contact 306a formed on access transistor Qn11 is connected to bit line BL1, and contact 306b formed on access transistor Qn21 is connected to bit line BLB1. Contact 307a formed on the gate wiring extending from the gate electrode of access transistor Qn11 and contact 307b formed on the gate wiring extending from the gate electrode of access transistor Qn21 are connected to word line WL1. The contacts (308a, 308b) formed on the driver transistors (Qn31, Qn41) are respectively connected to the wiring layers (Vss1a, Vss1b) having the ground potential, and the contacts (309a) formed on the load transistors (Qp11, Qp21). , 309b) is connected to the wiring layer Vcc1 which is the power supply potential.

FIG. 14 shows an N + implantation region (324a, 324b) and a P + implantation region 325. In the SRAM cell array region of this embodiment, the pattern for forming the N + implantation regions (324a, 324b) and the P + implantation region 325 is formed by simple lines and spaces. In addition, since the above SRAM cell has only a rectangular shape of the storage node and the gate wiring, it is easy to correct the pattern shape by OPC (Optical Proximity Correction) and is suitable for realizing a small SRAM cell area. Layout.

In the present invention, the source and drain of each transistor constituting the SRAM are defined as follows. For the driver transistors (Qn31, Qn41), a diffusion layer formed above the columnar semiconductor layer connected to the ground voltage is defined as a source diffusion layer, and a diffusion layer formed below the columnar semiconductor layer is defined as a drain diffusion layer. . For the load transistors (Qp11, Qp21), the diffusion layer formed above the columnar semiconductor layer connected to the power supply voltage is defined as the source diffusion layer, and the diffusion layer formed below the columnar semiconductor layer is defined as the drain diffusion layer. . For the access transistors (Qn11, Qn21), depending on the operating state, both the diffusion layer formed on the upper part of the columnar semiconductor layer and the diffusion layer formed on the lower part serve as the source or drain. The diffusion layer formed in (1) is defined as the source diffusion layer, and the diffusion layer formed under the columnar semiconductor layer is defined as the drain diffusion layer.

Next, the structure of the SRAM of the present invention will be described with reference to the cross-sectional structure of FIG.
As shown in FIG. 15A, planar silicon layers (302a, 302b) as storage nodes are formed on a buried oxide film layer (BOX) 301, and the planar silicon layers (302a, 302b) are formed on the planar silicon layers (302a, 302b). N + drain diffusion layers (303a, 305b) are formed by impurity implantation or the like. The element isolation for separating the planar silicon layers (302a, 302b) can be formed only by separating the planar silicon layer by etching. Therefore, the number of processes required to form the element isolation is small and the minimum Element separation of a processing dimension can be formed. Silicide layers (313a, 313b) are formed on the N + drain diffusion layers (303a, 305b). A columnar silicon layer 321a constituting the access transistor Qn11 is formed on the N + drain diffusion layer 303a, and a columnar silicon layer 322b constituting the driver transistor Qn41 is formed on the N + drain diffusion layer 305b. A gate insulating film 317 and a gate electrode 318 are formed around each columnar silicon layer. An N + source diffusion layer 314 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 315 is formed on the surface of the source diffusion layer. Contact 306a formed on access transistor Qn11 is connected to bit line BL1, and contact 307a formed on gate wiring 318a extending from the gate of access transistor Qn11 is connected to word line WL1, and on driver transistor Qn41. The formed contact 308b is connected to the ground potential wiring Vss1b.

As shown in FIG. 15B, planar silicon layers (302a, 302b) as storage nodes are formed on the buried oxide film layer (BOX) 301, and the planar silicon layers (302a, 302b) are formed on the planar silicon layers (302a, 302b). N + drain diffusion layers (303a, 305b) are formed by impurity implantation or the like. Silicide layers (313a, 313b) are formed on the N + drain diffusion layer. Contact 310a formed on drain diffusion layer 303a is formed on the boundary between N + drain diffusion layer 303a and P + drain diffusion layer 304a, and extends from the gate electrodes of driver transistor Qn41 and load transistor Qp21 through storage node connection wiring Na1. It is connected to a contact 311b formed on the gate wiring 318d.

As shown in FIG. 15C, planar silicon layers (302a, 302b) as storage nodes are formed on the buried oxide film layer (BOX) 301, and the planar silicon layers (302a, 302b) are formed on the planar silicon layers (302a, 302b). P + source diffusion layers (304a, 304b) are formed by impurity implantation or the like, and silicide layers (313a, 313b) are formed on the surface of the P + drain diffusion layers (304a, 304b). A columnar silicon layer 323a constituting the load transistor Qp11 is formed on the P + drain diffusion layer 304a, and a columnar silicon layer 323b constituting the load transistor Qp21 is formed on the P + drain diffusion layer 304b. A gate insulating film 317 and a gate electrode 318 are formed around each columnar silicon layer. A P + source diffusion layer 316 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 315 is formed on the surface of the source diffusion layer. The contacts (309a, 309b) formed on the load transistors (Qp11, Qp21) are both connected to the power supply potential wiring Vcc1 through the wiring layer.

As shown in FIG. 15D, planar silicon layers (302a, 302b) which are storage nodes are formed on the buried oxide film layer (BOX) 301, and impurities are implanted into the planar silicon layer. An N + drain diffusion layer (303a, 305a) and a P + drain diffusion layer 304a are formed. A silicide layer 313a is formed on the drain diffusion layer, and the N + drain diffusion layers (303a, 305a) and the P + drain diffusion layer 304a are directly connected by the silicide layer 313a. Columnar silicon layer 321a constituting access transistor Qn11 is formed on N + drain diffusion layer 303a, columnar silicon layer 322a constituting driver transistor Qn31 is formed on N + drain diffusion layer 305a, and loaded on P + drain diffusion layer 304a. A columnar silicon layer 323a constituting the transistor Qp11 is formed. The N + drain diffusion layer 303a, the P + drain diffusion layer 304a, and the N + drain diffusion layer 305a are directly connected by a silicide layer 313a formed on the surface of the planar silicon layer 332a. A gate insulating film 317 and a gate electrode 318 are formed around each columnar silicon layer. A source diffusion layer is formed on each columnar silicon layer by impurity implantation or the like, and a silicide layer 315 is formed on the surface of the source diffusion layer. Contact 306a formed on access transistor Qn11 is connected to bit line BL1, contact 308a formed on driver transistor Qn31 is connected to power supply potential wiring Vss1a, and contact 309a formed on load transistor Qp11 is power supply potential. Connected to the wiring Vcc1a.
Contact 311a formed on gate wiring 318c extending from the gate electrodes of driver transistor Qn31 and load transistor Qp11 is connected to contact 310b formed on the drain diffusion layer of storage node 302b through storage node connection wiring Nb1. . The contact 311a formed on the wiring is connected to the contact 316b connected to the planar silicon layer 305b by the wiring layer.

In the SRAM cell, the N + drain diffusion layer and the P + drain diffusion layer formed in the planar silicon layers (302a, 302b) which are storage nodes are directly connected by the silicide layer formed on the planar silicon layer surface. Thus, the drain regions of the access transistor, driver transistor, and load transistor are made common and function as a storage node of the SRAM.

In this embodiment, since the silicon nitride spacer is removed after the silicide layer is formed, the nitride film formed around the gate electrode is formed only from the silicon nitride film for the contact stopper. For this reason, the interval between the contact and the columnar silicon layer can be formed narrow, and the SRAM area can be reduced.

An example of a manufacturing method for forming the semiconductor device of the present invention will be described below with reference to FIGS. In each figure, (a) is a plan view and (b) is a cross-sectional view taken along D-D '.

As shown in FIG. 16, a silicon nitride mask 319 is formed on the SOI substrate formed on the buried oxide film (BOX) 301. Thereafter, a pattern of the columnar silicon layers (321a to 323a, 321b to 323b) is formed by lithography, and the columnar silicon layers (321a to 323a, 321b to 323b) are formed by etching. At this time, silicon is formed in a planar shape at the bottom of the columnar semiconductor.

As shown in FIG. 17, the planar silicon layers are separated to form planar silicon layers (302a, 302b) that serve as storage nodes. Since the above element isolation can be formed only by separating the planar silicon layer, the element isolation with a small number of steps and an isolation width of the minimum processing dimension can be formed.

As shown in FIG. 18, an impurity is introduced into each of the N + implantation region and the P + implantation region by ion implantation or the like to form a drain diffusion layer below the columnar silicon layer in the planar silicon layers (302a, 302b). At this time, it is preferable to adjust the implantation conditions so that the impurities reach the buried oxide film 301 and the impurities are distributed so as to cover the bottom of the columnar silicon layer. Further, the silicon nitride film 319 prevents impurities from being introduced into the upper part of the columnar silicon layer.

As shown in FIG. 19, after forming the gate insulating film 317, a gate conductive film 318 is formed.

As shown in FIG. 20, a silicon oxide film 331 is formed to embed columnar silicon layers.

As shown in FIG. 21, the silicon oxide film 331, the gate conductive film 318 over the columnar silicon layer, and the gate insulating film 317 are polished by CMP to flatten the gate upper surface. At the time of CMP, the silicon nitride film mask 319 above the columnar silicon layer is used as a CMP stopper. By using the silicon nitride mask 19 as a CMP stopper, the CMP polishing amount can be controlled with good reproducibility.

As shown in FIG. 22, in order to determine the gate length, the gate conductive film 318 and the silicon oxide film 331 are etched back to form a gate electrode on the side wall of the columnar silicon layer. At this time, an etching condition that takes a high selectivity with respect to the silicon nitride mask 319 is used.

As shown in FIG. 23, a silicon nitride film is formed and etched back to form a silicon nitride film sidewall 332 on the metal gate. At this time, the silicon nitride film formation amount and the etch back amount are set so that the silicon nitride film sidewall 332 remaining on the gate just covers the gate. Since the portion of the gate covered with the nitride film sidewall is protected during the subsequent gate etching, the gate electrode can be formed in a desired thickness in a self-aligned manner.

As shown in FIG. 24, the silicon oxide film 331 remaining on the metal gate is removed by wet etching.

As shown in FIG. 25, a gate wiring pattern 333 is formed by lithography using a resist or a multilayer resist.

As shown in FIG. 26, using the resist 333 as a mask, the gate conductive film and the gate insulating film are etched and removed. As a result, gate wirings (318a to 318d) are formed.

As shown in FIG. 27, the silicon nitride film mask 319 and the silicon nitride film sidewalls 332 are removed by wet processing.

As shown in FIG. 28, a silicon nitride film spacer 334 is formed.

As shown in FIG. 29, the silicon nitride film is etched back so that the side walls of the columnar silicon layer and the side walls of the gate electrode are covered with a silicon nitride film spacer 334. With such a structure, since the gate insulating film 317 is covered with the silicon nitride film 34, damage due to wet processing on the gate insulating film and damage due to impurity implantation in a later step can be prevented.
Further, the silicon nitride film spacer 334 covering the columnar silicon layer and the side wall of the gate electrode can suppress a short circuit between the drain and the gate and between the source and the gate caused by the silicide layer.

As shown in FIG. 30, impurities are introduced into the N + implantation region and the P + implantation region by ion implantation or the like to form source diffusion layers (314, 316) above the columnar silicon layer.

As shown in FIG. 31, a source / drain diffusion layer is selectively silicided by sputtering a metal such as Co or Ni and performing heat treatment, and silicide layers (313a, 313b) on the drain diffusion layer and A silicide layer 315 is formed on the source diffusion layer above the columnar silicon layer.

As shown in FIG. 32, the silicon nitride film spacer 334 present on the side walls of the columnar silicon layer and the gate electrode is removed by wet etching or dry etching.

As shown in FIG. 33, a silicon nitride film 335 for contact stopper is formed.

As shown in FIG. 34, contacts (306a to 310a, 306b to 310b) are formed after forming a silicon oxide film as an interlayer film.

FIG. 35A shows an SRAM cell when the present invention is used, and FIG. 35B shows an SRAM cell when the present invention is not used. In FIG. 35A, the nitride film covering the gate electrode formed around the columnar silicon layer is only the silicon nitride film 335 for contact stopper, whereas in FIG. 35B, the columnar silicon is formed. The nitride film covering the gate electrode formed around the layer has a laminated structure of a silicon nitride film spacer 434 and a contact stopper silicon nitride film 435 formed before silicidation.
In the SRAM cell, the columnar silicon layer and the contacts are formed at the closest intervals in the vertical direction. Therefore, comparing the present invention and the conventional example, the columnar silicon layer in the present invention is equal to the film thickness of the silicon nitride film spacer. The contact interval can be reduced.
In the SRAM, there are four places where the columnar silicon layer and the contacts are arranged at a minimum interval in the vertical direction. Specifically, in FIG. 35A, the columnar silicon layers Qn11 and Qp11 and the contact 310a are formed with a minimum interval, and the columnar silicon layers Qp11 and Qn31 and the contact 311a are formed with a minimum interval. In addition, there are four locations in the lateral direction of the SRAM cell where the columnar silicon layer and the contact interval are arranged at the minimum interval. Specifically, in FIG. 35A, columnar silicon layers Qn11 and Qn41 and a contact 310a are formed with a minimum interval.

As in the case of Example 1, when the thickness of the silicon nitride film spacer is 30 nm, the minimum distance between the columnar silicon layer and the contact is reduced by 30 nm when the present invention is used. Therefore, the length of the SRAM cell in the vertical direction is reduced by 30 nm × 4 = 120 nm. If the diameter of the columnar silicon layer is 30 nm, the gate film thickness is 50 nm, the contact dimension is 60 nm, and the element isolation width is 60 nm, the length of the SRAM in the conventional example can be estimated to be about 840 nm. The direction length can be shrunk by about 14%.
Similarly, the lateral length of the SRAM is reduced by 30 nm × 2 = 60 nm because there are two places where the columnar silicon layer and the contact are formed at the minimum interval. If the diameter of the columnar silicon layer is 30 nm, the gate film thickness is 50 nm, the contact dimension is 60 nm, and the element isolation width is 60 nm, the lateral length of the SRAM in the conventional example can be estimated to be about 560 nm. The direction length can be shrunk by about 11%.
From the above, when estimating the SRAM area in the present invention and the conventional example,
The present invention: 690 nm × 420 nm = 0.29 um ²
Conventional example: 810 nm × 480 nm = 0.39 um ²
Thus, in the present invention, the SRAM cell area can be reduced to about 74% of the conventional example.

As described above, in the present invention, the area occupied by the circuit formed by the SGT can be reduced by reducing the silicon nitride film thickness on the outer periphery of the gate electrode of the SGT.

It is the top view and sectional drawing of the 1st Example of this invention. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is process drawing which shows the manufacturing method of the 1st Example of this invention in process order. It is the top view and sectional drawing which compared this invention and the prior art example. It is the top view and sectional drawing of the 2nd Example of this invention. FIG. 6 is an equivalent circuit diagram of an SRAM which is a third embodiment of the present invention. It is a top view of SRAM which is the 3rd example of the present invention. It is sectional drawing of SRAM which is the 3rd Example of this invention. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is process drawing which shows the manufacturing method of SRAM which is the 3rd Example of this invention in process order. It is the top view which compared the case where this invention of the SRAM which is the 3rd Example of this invention and this invention are not used. It is sectional drawing which compared the case where this invention of the SRAM which is the 3rd Example of this invention is not used with this invention. It is the bird's-eye view and sectional drawing which show the prior art example of this invention.

101, 201: Columnar silicon layer 102, 202: Gate insulating film 103, 203: Gate electrode 104, 204: Lower diffusion layer 105, 205: Upper diffusion layer 106: Silicon nitride film spacer 107, 207: Lower silicide layer 108, 208 : Upper silicide layers 109, 209: silicon nitride film for contact stopper 110: contact 301: buried oxide films 302a, 302b: planar silicon layers 303a, 303b, 305a, 305b: N + drain diffusion layers 304a, 304b: P + drain diffusion layers 306a, 306b: Access transistor source diffusion layer contacts 307a, 407a, 307b, 407b: Access transistor word line contacts 310a, 410a, 310b, 410b: Planar silicon layer contours 311a, 411a, 311b, 411b: gate wiring contacts 313a, 313b: drain portion silicide layer 314: N + source diffusion layer region 315: source portion silicide layer 316: P + source diffusion layer region 317: gate insulating film 318: gate electrode 318a, 318b, 318c, 318d: gate wiring 319: mask layer 321a, 321b: access transistor columnar silicon layer 322a, 322b: driver transistor columnar silicon layer 323a, 323b: driver transistor columnar silicon layer 324a, 324b: N + implantation region 325: P + implantation region 331: silicon oxide film 332: silicon nitride film sidewall 333: resist 334, 335: silicon nitride film

Claims (3)

This is a method for manufacturing a semiconductor device comprising a MOS transistor having a structure in which a source or a drain is formed above and below a columnar semiconductor layer formed on a silicon substrate, and a gate electrode surrounds the columnar semiconductor layer. And
Etching the silicon substrate to form a columnar semiconductor layer;
Forming a gate insulating film on the surface of the etched silicon substrate and the surface of the columnar semiconductor layer;
Forming a gate conductive film on the surface of the gate insulating film;
Etching each of the gate insulating film and the gate conductive film to form a gate electrode;
When a silicide layer is formed only on a portion where the diffusion layer is exposed on the surface of the diffusion layer disposed above and below the columnar semiconductor layer, at least a sidewall of the upper portion of the columnar semiconductor layer is protected from silicidation. Forming an insulating film of 1 on a sidewall of the upper part of the columnar semiconductor layer;
Forming a silicide layer only on a portion where the diffusion layer is exposed on the surface of the diffusion layer disposed above and below the columnar semiconductor layer; and
Removing the first insulating film after the silicide layer is formed;
Forming a second insulating film on the columnar semiconductor layer and the gate electrode as a contact stopper;
And a step of forming a third insulating film as an interlayer film on the second insulating film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a silicon oxide film, a silicon nitride film, or a stacked film of a silicon oxide film and a silicon nitride film.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a silicon nitride film and the third insulating film is a silicon oxide film.

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