JP5215650B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, and more particularly to a CCD image sensor having an accumulation unit that is provided between a photoelectric conversion unit and a charge transfer unit and accumulates charges photoelectrically converted by the photoelectric conversion unit.

  Patent Document 1 discloses a CCD image sensor as a solid-state imaging device of this type, which includes a photodiode that photoelectrically converts received light and a storage unit that performs accumulation control of photoelectrically converted charges. In this conventional CCD image sensor, the surface of the photodiode and the silicon substrate of the storage unit are N-type in operation. For this reason, a large amount of dark current is generated in these portions, and image deterioration is remarkable when long-time accumulation is performed. In particular, when the temperature is high, there is a problem that the accumulation time cannot be made sufficiently long. For example, in an autofocus image sensor, it is necessary to focus under a very wide light amount difference from night view to shooting under sunlight. For this reason, it is necessary to change the accumulation time widely, but with this structure, the range of brightness and temperature that can be used has been limited.

  In addition, a barrier gate is provided between the photodiode and the storage unit. A positive constant voltage is applied to the barrier gate, and the accumulation control of the signal charge generated by the photodiode is not performed. Further, a constant positive voltage is also applied to the storage unit, and since it is N-type up to the substrate surface in the operating state, a large amount of dark current is also generated in this part.

  FIG. 16 shows an example of a conventional solid-state imaging device in which a plurality of image areas 2-1 and 2-2 each including a plurality of photodiodes 2 are provided for a single CCD 8. Different video signals are input to the image areas 2-1 and 2-2, and signal charges are generated. The control gates 4-1 and 4-2 independently control the accumulation time, and the generated signal charges are accumulated in the storage unit 5. By using accumulation control in this way, it is possible to obtain a sufficient amount of signal even in an environment with a small amount of light, and in an environment with a large amount of light, image information without saturation can be obtained by shortening the accumulation time. Can be obtained.

  Patent Document 2 discloses a solid-state imaging device capable of reducing dark current. FIG. 17 is a diagram illustrating a configuration of the solid-state imaging device described in Patent Document 2. As shown in FIG. 17, the solid-state imaging device 1 described in Patent Document 2 has a structure in which charges generated by the photodiode 2 are accumulated by the storage gate 5. In this structure, a potential barrier that hinders charge transfer from the photodiode 2 to the CCD 8 does not occur, so that charges can be read out smoothly. In addition, by applying a negative voltage to the storage gate 5 to achieve a pinning state in which the substrate surface is P-type in the operation state, the storage gate 5 has a feature that image degradation is small when long-time accumulation is performed.

  Here, the operation of the solid-state imaging device 1 shown in FIG. 17 will be described with reference to FIGS. 18 and 19. 18A is a cross-sectional view taken along the line XX ′ of the solid-state imaging device 1 of FIG. 17, and FIG. 18B shows the potential of each part. FIG. 19 is a diagram illustrating a potential profile in the depth direction of each unit (photodiode unit, storage unit, transfer gate unit) of the solid-state imaging device 1. All charges generated in the photodiode 2 are accumulated in the storage gate 5. As shown in FIG. 19, a negative voltage is applied to the storage gate 5 so that the substrate surface is inverted to the P-type. In the pinned storage gate 5, the interface between the semiconductor and the gate oxide film is inverted to a P-type semiconductor, and the surface potential becomes the GND potential.

  For this reason, the thermoelectrons generated at the crystal defect portion frequently generated at the interface of the gate oxide film are less likely to affect the accumulated signal charges by recombining with holes in the P-type semiconductor in the inverted state. . Therefore, the signal current is less deteriorated by dark current than a normal buried channel type storage gate, and signal charge can be accumulated for a long time or at a high temperature. Since the substrate surface is P-type, the photodiode is already pinned and can have almost the same performance as the storage gate portion. Thus, by using a storage gate that is in a pinning state, dark current is reduced and signal charge is accumulated. Further, in the conventional solid-state imaging device 1, by forming all the parts from the photodiode 2 to the CCD 9 in the same N well, it is possible to completely transfer charges and to realize reading of the photodiode without an afterimage. Yes.

  Moreover, there is also a solid-state imaging device described in Patent Document 3 as an application example of a structure including a charge storage unit. This corrects a spatial line difference between a plurality of light receiving units by providing an analog memory between the light receiving unit and a shift register as a charge transfer unit.

  As another application example of a structure including a charge storage unit, there is an apparatus that optically measures a distance to a measurement object as disclosed in Patent Document 4. This is used in particular as a sensor for an AF (autofocus) function of a digital camera.

Japanese Patent No. 2937192 JP-A-6-216363 Japanese Patent Laid-Open No. 2004-112797 JP 2000-249907 A

  As described above, the solid-state imaging device having the charge storage unit is applied to various application fields. Especially in the image sensor for autofocus, under a very wide light amount difference from night view to shooting under sunlight. It is necessary to change the accumulation time widely because of the need to focus. Furthermore, since the amount of signal from the subject decreases as the darker, the dark current generated in the photodiode and the storage unit, that is, the noise component generated by the sensor itself is required to be reduced.

  However, not only the image sensors disclosed in Patent Documents 1 to 3, but also the image sensor disclosed in Patent Document 4 that mainly discloses an autofocus sensor is configured to satisfy these two requirements at the same time. Absent.

  A solid-state imaging device according to the present invention is provided between a photoelectric conversion unit, a charge storage unit, a charge transfer unit, a photoelectric conversion unit, and a charge storage unit, and controls movement of charges from the photoelectric conversion unit to the charge storage unit. A first control gate; and a second control gate provided between the charge storage unit and the charge transfer unit for controlling the movement of charge from the charge storage unit to the charge transfer unit, wherein the charge storage unit is pinned (PIN-ing) It is characterized by being configured to hold charges in a state.

  Here, in order to configure the charge storage unit to hold charges in a pinning state, a predetermined bias voltage is applied over one conductivity type region (typically N-type region) as the charge storage unit. It is preferable to cover with an electrode to which is applied, or to form another conductivity type region (and therefore a P type region) on the surface of one conductivity type region. The latter structure is widely adopted as the structure of the photoelectric conversion unit as a so-called PIN diode.

  Note that a preliminary charge accumulation region may be provided continuously to the photoelectric conversion region. In this case, it is preferable to cover the preliminary charge accumulation region with an electrode and apply a predetermined bias to a pinning state.

  According to such a configuration, the photoelectric conversion time and the charge accumulation time can be arbitrarily controlled by the first control gate and the second control gate, and a very wide light amount difference from night view to shooting under sunlight is possible. It is possible to hold a charge corresponding to a necessary light amount for an arbitrary time. In addition, the presence of the first and second control gates allows the charge storage region to be brought into a pinned state without being affected by the photoelectric conversion unit and the charge transfer unit, and generation of dark current can be suppressed. . Thus, it is possible to provide a solid-state imaging device capable of suppressing the generation of dark current and transferring signal charges without causing an afterimage.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In general, in a solid-state imaging device, a portion other than a light receiving surface of a photodiode that is a photoelectric conversion unit is covered with a light shielding film made of metal so that light does not enter, but in the following description and drawings, these are simplified. In some cases, illustration of the light shielding film is omitted. Further, the description of the same structure as the conventional structure such as the surface protection oxide film and the structure of the output circuit is omitted. Furthermore, the solid-state imaging device according to each embodiment of the present invention has a storage control function using an automatic adjustment function (AGC: Auto Gain Control) or the like so that the output signal does not exceed the reference level. Also good. Moreover, in each embodiment, the same structural part is shown with the same reference number, and those duplicate description is abbreviate | omitted.

  FIG. 1 is a schematic plan view illustrating the configuration of a solid-state imaging device according to Embodiment 1 of the present invention. 2A is a cross-sectional view taken along the line XX ′ of FIG. 1, and FIG. 2B is a diagram illustrating the potential of each part. 3A is a cross-sectional view taken along the line YY ′ of FIG. 1, and FIG. 3B is a diagram illustrating the potential of each part. 4A is a cross-sectional view taken along the line ZZ ′ of FIG. 1, and FIG. 4B is a diagram illustrating the potential of each part.

    As shown in FIG. 1, the solid-state imaging device 1 according to the present embodiment includes a photoelectric conversion unit 2, a preliminary charge storage unit 3 formed continuously with the photoelectric conversion unit 2, a charge storage unit 5, and these storage units 3 and 3. 5, a first control gate unit 4, a charge transfer unit 8, a second control gate unit 6 provided between the storage unit 5 and the transfer unit 8, a reset unit 7 for resetting the storage unit 5, In addition, an output amplifier 9 for amplifying and outputting the charge from the charge transfer unit 8 is provided.

  Referring to FIG. 2A, which is a cross section taken along line XX ′ of FIG. 1, in the present embodiment, a surface portion of a P-type semiconductor substrate (also referred to as a semiconductor substrate layer) 10 made of, for example, silicon. In addition, an N-type region 11 and an N-type region 12 (respective impurity concentration relationships will be described later) are selectively formed. The first region 11 and the second region 12 are formed adjacent to each other. A P + type region 21 having a higher concentration than that of the silicon substrate 10 is selectively formed on the surface portion of the N type first region 11. The P + type region 21 and the N type first region 11 form a so-called PIN photodiode structure photoelectric conversion unit 2. The photoelectric conversion unit 2 generates signal charges according to the received light. The P + type channel stop unit 13 prevents the signal charge generated in the photoelectric conversion unit 2 from flowing in a direction other than the first accumulation unit 3.

  Further, a portion of the first region 11 opposite to the channel stop portion becomes a spare charge storage portion 3 and receives signal charges generated in the photoelectric conversion portion 2. That is, charges generated by the incidence of light in the photoelectric conversion unit 2 are temporarily accumulated in the accumulation unit 3. The storage unit 3 has a first storage gate electrode 32 provided on the first region 11 via a first storage gate insulating film 31. A constant negative voltage is applied to the first storage gate electrode 32 during operation. For this reason, the pinned state in which the interface between the first region 11 and the first storage gate insulating film 31 is inverted to the P-type is obtained.

  On the other hand, in the second region 12, the charge storage unit 5 is provided adjacent to the first storage unit 3. The storage unit 5 receives signal charges from the storage unit 3. The storage unit 5 has a second storage gate electrode 52 provided on the second region 12 via a storage gate insulating film 51. A constant negative voltage is applied to the storage gate electrode 52 during operation. For this reason, the pinned state in which the interface between the second region 12 and the second storage gate insulating film 51 is inverted to the P-type is obtained. That is, the charge storage unit 5 also stores charges in the pinned state. In the second region 12, a charge transfer unit 8 is formed adjacent to the storage unit 5. The charge transfer unit 8 has a gate electrode 82 on the N-type second region via a gate insulating film 81. The charge transfer unit 8 receives the signal charge from the second accumulation unit 5 at a predetermined timing.

  A first control gate unit 4 is formed between the storage units 3 and 5. The control unit 4 controls the transfer of the signal charge stored in the preliminary storage unit 3 to the charge storage unit 5 and is formed across the surface portion of the first region 11 and the surface portion of the second region 13. Has been. Specifically, the control unit 4 spans the surface portion of the first region 11 and the surface portion of the second region 12 and has the same conductivity type as the first region 11 and the second region 12. A gate electrode 43 is provided on the first impurity layer 41 formed with a lower impurity concentration than the second region 12 with an insulating film 42 interposed therebetween. For example, by implanting boron so that the first impurity layer 41 becomes 9.0 × 1011 / cm 2 at 50 KeV, a part of the surface of the N-type regions 11 and 12 becomes a low-concentration N− layer.

  A predetermined clock pulse is applied to the first control gate electrode 43 formed on the first impurity layer 41 via the first control gate insulating film 42. As a result, delivery of charges from the storage unit 3 to the storage unit 5 is controlled. A part of the gate electrode 43 overlaps the first storage gate electrode 32 and the second storage gate electrode 52 on both sides thereof.

  A second control unit 6 is formed between the charge storage unit 5 and the charge transfer unit 8. The second control unit 6 delivers the signal charge accumulated in the second accumulation unit 5 to the charge transfer unit 8. The second controller 6 is selectively formed on the surface portion of the second region 12, and has the same conductivity type as the first region 11 and the second region 12 and has a lower concentration than the first region 11 and the second region 12. A second impurity layer 61 is provided. As the second impurity layer 61, for example, a thin N− layer is formed on the surface of the silicon substrate 10 by injecting boron so as to be 9.0 × 10 11 / cm 2 at 50 KeV as in the first impurity layer 41. can do.

  A second control gate electrode 63 is formed on the second impurity layer 61 via a second control gate insulating film 62. A predetermined clock pulse is applied to the second control gate electrode 63. As a result, delivery of charges from the storage unit 5 to the transfer unit 8 is controlled. A part of the second control gate electrode 63 overlaps the second storage gate electrode 52 on both sides thereof and the gate electrode 82 of the CCD register.

  The N-type region 12 has a higher impurity concentration than the N-type region 11. That is, the impurity concentration of the N layer of the storage unit 5 is higher than the impurity concentration of the N layer of the storage unit 3. Therefore, the storage unit 5 on the charge transfer unit 8 side has a higher potential than the storage unit 3, and as a result, the flow of signal charges from the storage unit 3 to the storage unit 5 and the charge transfer unit 8 is made smoother. be able to.

  The impurity concentration difference between the first region 11 and the second region 12 can be manufactured by double implantation. For example, N (phosphorus) is implanted in the first region 11 and the second region 12 at 80 KeV and 1.4 × 10 12 / cm 2 in the first time, and 4 × 10 11 / cm 2 in the second region 12 at 80 KeV in the second time. N (phosphorus) can be implanted under the following conditions. Alternatively, as shown in FIG. 5, P (boron) is implanted in the first region 11 and the second region 12 at 50 KeV at 4 × 10−11 / cm 2 in the first time, and in the first region 11 in the second time. It is also possible to implant N (phosphorus) under conditions of 4 × 1011 / cm 2 at 80 KeV.

  FIG. 2B shows that the 0 V (GND) potential is applied to the silicon substrate 10 and the channel stop region 13 of the solid-state imaging device 1 shown in FIG. 2A, the clock pulse φTG1 is applied to the first control gate electrode 43, and the second The potential profile of the substrate surface when the clock pulse φTG2 is applied to the control gate electrode 63 and the clock pulse φ1 is applied to the gate electrode 82 is shown. In FIG. 2B, solid lines indicate a state when the clock pulses φTG1, φTG2, and φ1 are at the “L” level, respectively, and a broken line indicates a state where these are at the “H” level. 2B, ψPD is the depth of the potential well of the photoelectric conversion unit 2, ψST1 is the depth of the potential well of the first storage portion 3, and ψST2 is the depth of the potential well of the second storage portion 5. Show.

  In the solid-state imaging device 1 according to the present embodiment, signal charges generated when light enters the photoelectric conversion unit 2 are accumulated in the potential well of the preliminary charge accumulation unit 3. The accumulated signal charge moves to the first control unit 4 by opening the first control gate 4 (φTG1 becomes “H”). Then, by closing the first control gate 4 (φTG1 becomes “L”), the signal charge accumulated so far in the first control unit 4 is accumulated in the potential well of the charge accumulation unit 28. Then, the accumulated signal charge is transferred under the gate electrode 82 of the charge transfer unit 8 by opening the second control gate 6 (φTG2 becomes “H”). As described above, the second control unit 6 on the charge transfer unit 8 side has a higher potential than the first control unit 4, and the first control unit 4 is formed across the first region 11 and the second region 12. Therefore, the flow of signal charges to the photoelectric conversion unit 2, the preliminary storage unit 3, the first control unit 4, the charge storage unit 5, the second control unit 6, and the charge transfer unit 8 can be made smooth.

As shown in FIG. 3A showing a cross-sectional view along the line YY ′ in FIG. 1, the reset unit 7 is formed adjacent to the charge storage unit 5. The reset unit 7 discharges unnecessary signal charges from the second control unit 6. The reset unit 7 is selectively formed on the surface portion of the second region 12 and has the same N type as the first region 11 and the second region 12 and has a lower concentration than the first region 11 and the second region 12. A third impurity layer 71 is provided. The third impurity layer 71 is thin on the surface of the silicon substrate 10 by implanting boron so as to be 9.0 × 1011 / cm 2 at 50 KeV, for example, like the first impurity layer 41 and the second impurity layer 61. N-layers can be formed. A first reset gate electrode 73 is formed on the third impurity 71 via a gate insulating film 72. A predetermined clock pulse is applied to the first reset gate electrode 73. A part of the first reset gate electrode 73 overlaps the second storage gate electrode 52. A reset drain 74 made of an N + region is provided on the silicon substrate 10. Unnecessary charges remaining in the second control unit 15 are discharged to the reset drain 74 via the first reset gate electrode 73.
3B shows a case where the silicon substrate 10 and the channel stop region 13 of the solid-state imaging device 1 shown in FIG. 3A have a 0 V (GND) potential, the first control gate electrode 43 has a clock pulse φTG1. The potential of each part of the substrate surface when the clock pulse φR1 is applied to the reset gate electrode 73 is shown. In FIG. 3B, solid lines indicate a state when the clock pulses φTG1 and φR1 are at the “L” level, respectively, and a broken line indicates a state where they are at the “H” level.

  In the solid-state imaging device according to the present embodiment, unnecessary charges remaining in the second accumulation unit 5 are discharged from the second control unit 4 to the reset drain 74 via the first reset gate electrode 73. That is, φTG1 applied to the first control gate electrode 43 and φTG2 applied to the second control gate electrode 63 are set to the “L” level, and φR1 is set to the “H” level, whereby the second control gate electrode 63 and In a state where the photoelectric conversion unit 2 is separated, the reset operation of the second storage unit 5 is possible. For this reason, unnecessary charges can be completely reset.

  As shown in FIG. 4, the charge transfer unit 8 in FIG. 1 is a well-known two-phase drive CCD, and the signal charges transferred via the second control unit 6 are sequentially transferred, It is output via the output amplifier 9.

  Here, the operation of the solid-state imaging device 1 according to Embodiment 1 will be described with reference to FIG. FIG. 5 is a diagram showing an example of the timing of each signal applied to the solid-state imaging device according to the present embodiment. In the reset period during which unnecessary charges accumulated in the charge accumulation unit 5 are discharged, the preliminary accumulation unit 3 There are a first accumulation period in which signal charges are accumulated, a second accumulation period in which signal charges are accumulated in the charge accumulation unit 5, and a charge transfer period in which signal charges are transferred in the charge transfer unit 8.

  In the reset period, φR1 is at “H” level, and φTG1 and φTG2 are at “L” level. During this time, unnecessary charges accumulated in the accumulation unit 5 are completely discharged to the reset drain 74. In the first accumulation period, φR1 becomes “L” level, and signal charges are transferred from the photoelectric conversion unit 2 to the accumulation unit 3 (T1). In the first accumulation period, the signal charge accumulated in the accumulation unit 3 is transferred to the accumulation unit 5 when φTG1 becomes “H” level (T2). Thereafter, φTG1 is set to the “L” level, and the signal charge is held in the storage unit 5 until reading in all the image areas is completed. In the charge transfer period, when reading in all the image areas is completed, φTG2 is set to the “H” level, and the second signal charge held in the storage unit 5 is transferred to the charge transfer unit 8 (T3). The signal charges transferred in the charge transfer unit 8 are sequentially taken out via the output amplifier 9.

  Thus, according to the present invention, not only the photoelectric conversion unit but also the preliminary storage unit, the first control unit, the charge storage unit, the second control unit, and the charge transfer unit are formed in the same conductivity type semiconductor region. , The movement of charges is performed smoothly. Further, during operation, since the surface of the semiconductor substrate is in a P-type pinning state, generation of dark current can be suppressed. Since unnecessary charges in the second accumulation unit can be completely discharged to the reset drain, the occurrence of afterimage can be suppressed.

  A second embodiment of the present invention will be described with reference to FIG. 6 corresponds to the configuration from the photoelectric conversion unit 2 to the reset unit 6 in FIG. In the present embodiment, the photoelectric conversion unit 2, the reserve charge storage unit 3, the first control gate unit 4, the signal charge storage unit 5, the second control gate unit 6, the charge transfer unit 8, the reset unit 7, etc. The semiconductor region 110 is formed as a base. Furthermore, since the single-layer semiconductor region 110 is employed, a predetermined potential difference does not occur in the first control gate unit 4 and the charge holding units 3 and 6 in this state. The surface impurity concentration of the portion 120 corresponding to a part of the portion 2, the preliminary charge storage portion 3 and the control gate portion 4 is set lower than that of the other portions. This is realized by selectively ion-implanting a P-type impurity such as boron into the corresponding portion 120.

  That is, after the channel stop region 13, the semiconductor region 110, and the P + region 21 of the photoelectric conversion unit 2 are formed, the P-month impurity in the corresponding portion 120 is selectively ion-implanted. After that, gate electrodes 32 and 52 made of polysilicon, for example, and the first gate electrode of the CCD portion are formed as the first gate electrode layer, a mask is applied to an undesired portion, and P-type impurities such as boron are ion-implanted again. Then, impurity layers 41 and 71 are formed.

  Also in this embodiment, it is easily understood that the same operation and effect as in the previous embodiment can be obtained, and thus detailed description thereof is omitted.

  Next, a solid-state imaging device according to Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 7 is a plan view showing the configuration of the solid-state imaging device 100 according to the present embodiment. FIG. 8A is a cross-sectional view taken along the line U-U 'in FIG. 7, and FIG. FIG. In the present embodiment, the difference from the first embodiment is the configuration of the reset unit 7, and the description of the other configurations is omitted.

  As shown in FIGS. 7 and 8A, the reset unit 7 according to the present embodiment has a function of discharging unnecessary charges from the preliminary storage unit 3 in addition to a function of discharging unnecessary charges from the charge storage unit 5. Have The reset unit 7 includes a fourth impurity layer 75 that is selectively formed on the surface portion of the first region and has the same N type as the first region 11 and has a lower concentration than the first region 11. The fourth impurity layer 75 is formed of a thin N− layer on the surface of the silicon substrate 10 by implanting boron so that the fourth impurity layer 75 becomes 9.0 × 1011 / cm 2 at 50 KeV, for example. be able to. A second reset gate electrode 77 is formed on the fourth impurity layer 75 via a gate insulating film 76. A predetermined clock pulse is applied to the second reset gate electrode 77. A part of the second reset gate electrode 77 overlaps the storage gate electrode 32. A reset drain 74 made of an N + region is provided on the silicon substrate 10. The reset drain 74 is shared by the second reset gate electrode 73 and the second reset gate electrode 77. Signal charges can be discharged from the storage unit 3 to the reset drain 74 via the second reset gate electrode 77.

  In FIG. 8B, a 0 V (GND) potential is applied to the silicon substrate 10 and the channel stop region 13 of the solid-state imaging device 1 illustrated in FIG. 8A, and a clock pulse φR <b> 2 is applied to the second reset gate electrode 77. The potential of each part on the substrate surface is shown. In FIG. 8B, a solid line indicates a state when the clock pulse φR2 is at the “L” level, and a broken line indicates a state where the clock pulse φR2 is at the “H” level.

  In the solid-state imaging device according to the present embodiment, signal charges generated when light enters the photoelectric conversion unit 2 are accumulated in the potential well of the preliminary accumulation unit 3. In an environment with a large amount of light, the signal charge overflowing from the photoelectric conversion unit 2 may affect the signal charge stored in the storage unit 3. At this time, by keeping φTG2 applied to the second control gate electrode 63 at the “L” level and φR2 at the “H” level, the signal charges overflowing in a state separated from the second control unit 6 are increased. It can be discharged to the reset drain 74. Thereby, good image information without saturation can be obtained.

  With reference to FIG. 9, the operation of the solid-state imaging device 100 according to Embodiment 3 will be described. As shown in FIG. 9, it has a reset period, a first accumulation period, a second accumulation period, and a charge transfer period.

  In the reset period, φR1 and φR2 are at “H” level, and φTG1 and φTG2 are at “L” level. During this time, unnecessary charges in the storage units 3 and 5 are completely discharged to the reset drain 74. In the first accumulation period, φR1 and φR2 become “L” level, and signal charges are transferred from the photoelectric conversion unit 2 to the accumulation unit 3 (T1). Then, during the first accumulation period, φTG1 becomes “H” level, whereby the signal charge accumulated in the first accumulation unit 3 is transferred to the second accumulation unit 5 (T2). Thereafter, φTG1 is set to the “L” level, and the signal charge is held in the storage unit 5 until reading in all the image areas is completed. In the charge transfer period, when reading in all the image areas is completed, φTG2 is set to the “H” level, and the second signal charge held in the storage unit 5 is transferred to the charge transfer unit 8 (T3). The signal charges transferred in the charge transfer unit 8 are sequentially taken out via the output amplifier 9.

  A solid-state imaging device according to Embodiment 4 of the present invention will be described with reference to FIGS. 11A is a cross-sectional view taken along the line XX ′ in FIG. 10, and FIG. 11B shows the potential of each part in FIG. The feature of the present embodiment is that the signal charge in the photoelectric conversion unit 2 is supplied and stored in the charge storage unit 5 under the control of the control gate 4 without going through the reserve charge storage unit 3 in FIG. It is in. Further, a reset drain 90 is provided on the side opposite to the side where the control gate charge of the photodiode as the photoelectric conversion unit 2 is provided. The reset drain 90 has an N-region 901 (formed simultaneously with the regions 41 and 61) and a reset gate electrode 902 thereon. An N + type drain region is formed on the side opposite to the control gate 4 in contact with the region 11. When the reset pulse φR2 is applied to the electrode 902, the charge of the photodiode is reset. 11 shows the light shielding film 200, the light shielding film 200 is similarly provided in the first to third embodiments.

  12 and 13 show a solid-state imaging device according to Embodiment 5 of the present invention. In this embodiment, a shutter structure 85 is provided in place of the reset drain of FIG. 11 to prevent undesired charges on the charge storage unit 5 side. As shown in FIG. 13, the shutter structure 85 includes an N + drain region 75 (this region is formed so as to be continuous between the photodiodes) provided on the opposite side of the control gate 4 in contact with the region 11, and a photo The P + region 851 is in contact with the P + region 2 of the diode and has a deep P + region 851.

  14 and 15 show a solid-state imaging device according to Embodiment 6 of the present invention. In this embodiment, unlike the previous embodiments, the transmission storage region is composed of a P-type region and an N-type region as in the photodiode 2. That is, as shown in FIG. 15, the P + type region 1052 is formed on the surface portion of the N type region 12 corresponding to the charge storage portion 5. Further, in order to obtain a desired potential, an N-type region 1051 is added to this portion, which is deeper than the regions 11 and 12 as a whole. Since the present embodiment is not a pinning gate type that reverses the surface to P-type by applying a negative voltage to the storage electrode as in the previous embodiments, the storage control electrode that covers the P + region 1052 is not necessary.

  In addition, since operation | movement of each of Embodiment 4-6 is easily understood from each Embodiment 1 thru | or 3, it abbreviate | omits.

  As described above, according to the present invention, not only the photoelectric conversion unit, but also each storage unit, each control unit, and the charge transfer unit are formed in the same conductivity type region, so that the movement of charges is performed smoothly. Generation of afterimages can be suppressed. Further, since the surface of the semiconductor substrate is in a P-type state during operation by the pinning control or the device structure itself in the storage unit, generation of dark current can be suppressed. The accumulation time can be controlled by the first control electrode and the second control electrode, and a sufficient amount of signal can be obtained even in an environment with a small amount of light. The image information without saturation can be obtained by shortening the accumulation time.

  The object of the present invention is to realize a structure capable of controlling the accumulation time with reduced dark current, and the parts other than the photoelectric conversion unit, the accumulation unit, the reset unit, the charge transfer unit, and the control of each unit other than the above-described example It is also possible to use this method. For example, in the above-described embodiment, the example using the charge transfer unit of two-phase driving has been described. However, other methods such as four-phase driving can be used as the driving method of the charge transfer unit. In the above-described embodiment, an example of a two-layer polysilicon gate structure is shown, but other structures such as a single-layer structure and a three-layer structure can be realized. Further, if the substrate is in a pinning state in which the surface of the substrate is P-type in the operating state, and the storage unit has two stages and a control gate electrode is provided at each outlet, the presence or absence of the reset unit can be selected. Furthermore, a solid-state imaging device in which the features of the embodiments are appropriately combined can be configured.

It is a top view which shows the solid-state imaging device which concerns on Embodiment 1 of this invention. FIG. 2 is a cross-sectional view taken along line XX ′ in FIG. 1 and a potential diagram during operation. FIG. 2 is a cross-sectional view taken along line YY ′ of FIG. 1 and a potential diagram during operation. FIG. 2 is a cross-sectional view taken along the line ZZ ′ of FIG. 1 and a potential diagram during operation. 3 is an example of timing for operating the solid-state imaging device according to the first embodiment. It is sectional drawing which shows the solid-state imaging device which concerns on Embodiment 2 of this invention. It is a top view which shows the solid-state imaging device which concerns on Embodiment 3 of this invention. FIG. 8 is a cross-sectional view taken along the line U-U ′ of FIG. 7 and a potential diagram during operation. 10 is an example of timing for operating the solid-state imaging device of Embodiment 3. It is a top view which shows the solid-state imaging device which concerns on Embodiment 4 of this invention. It is XX 'sectional drawing of FIG. 10, and the potential diagram at the time of operation | movement. It is a top view which shows the solid-state imaging device which concerns on Embodiment 5 of this invention. FIG. 13 is a cross-sectional view taken along line XX ′ in FIG. 12 and a potential diagram during operation. It is a top view which shows the solid-state imaging device which concerns on Embodiment 6 of this invention. FIG. 15 is a cross-sectional view taken along line XX ′ in FIG. 14 and a potential diagram during operation. It is a top view which shows the conventional image sensor. It is a top view which shows the other conventional image sensor. FIG. 18 is a cross-sectional view taken along the line XX ′ of FIG. 17 and a diagram showing potential during operation. It is a figure which shows the electric potential profile of the substrate depth direction of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Photoelectric conversion part 3 Preliminary storage part 4 1st control gate part 5 Charge storage part 6 2nd control gate part 7 Reset part 8 Charge transfer part 9 Output amplifier

Claims (14)

A photoelectric control unit, a charge storage unit, a charge transfer unit, and a first control gate that is provided between the photoelectric conversion unit and the charge storage unit and controls movement of signal charges from the photoelectric conversion unit to the charge storage unit comprising a part, and a second control gate portion for controlling the transfer of charge from the charge storage portion and provided between the charge transfer portion and the charge accumulating portion to said charge transfer unit, the charge storage section, N type A storage gate electrode that covers the N-type diffusion region via an insulating film in contact with the diffusion region and the N-type diffusion region, and a constant negative voltage is applied to the storage gate electrode; Is configured to hold the signal charge in a pinned state. Preliminary charge storage portion provided continuously to the photoelectric conversion unit, according to claim 1 wherein the signal charges, characterized in that it is moved to the charge storage portion via the first control gate from said preliminary charge storage section The solid-state imaging device described. Each of the charge storage unit and the reserve charge storage unit includes the N-type diffusion region and an electrode covering the region with an insulating film, and a predetermined bias voltage is applied to the electrode. The solid-state imaging device according to claim 2 . The photoelectric conversion unit, the preliminary charge storage unit, the charge storage unit, said charge transfer unit, the first control gate portion and the second control gate portion, N, which is formed in the surface portion of the P-type semiconductor substrate layer The solid-state imaging device according to claim 2, wherein the solid-state imaging device is formed using a semiconductor region of a mold as a base. The semiconductor region includes a first region in which the photoelectric conversion unit is formed, and a second region in which the charge storage unit and the second control gate unit are formed, and the second region is the first region. The solid-state imaging device according to claim 4 , wherein an impurity concentration is higher than the first control gate portion, and the first control gate portion is formed across the first and second regions. Each of the first and second control gate portions includes a third region having an N- type impurity concentration lower than that of the first and second regions, and a gate electrode covering the third region with an insulating film interposed therebetween. The solid-state imaging device according to claim 5 , comprising: Each of the first and second control gate portions has a low concentration region having an impurity concentration lower than that of the semiconductor region and having an N type, and a gate electrode covering the low concentration region with an insulating film interposed therebetween, according to claim 4, wherein the low concentration the photoelectric conversion portion side portion of the surface portion of the region having the first control gate portion is characterized in that in the low impurity concentration than the portion of the charge storage portion Solid-state imaging device. 7. The solid-state imaging device according to claim 5 , wherein the charge storage unit includes a storage gate electrode provided on the second region via a gate insulating film and to which a constant voltage is applied. Wherein the preliminary charge storage portion of the first region as a substrate is provided between the first control gate portion and the photoelectric conversion unit, the pre-charge accumulation portion is provided through a gate insulating film on the first region The solid-state imaging device according to claim 5, further comprising a pre-storage gate electrode to which a constant voltage is applied. Wherein the preliminary charge storage portion of the semiconductor region as a base is provided between said first control gate section and the photoelectric conversion unit, the surface impurity concentration of the portion of the semiconductor region where the pre-charge accumulation portion is formed the The solid-state imaging device according to claim 4 , wherein the solid-state imaging device is lower than other portions of the semiconductor region . The formed adjacent to the charge storage unit, the solid-state imaging device according to any one of claims 1 to 10 comprising a reset portion for discharging the signal charges from the charge storage part. The formed adjacent to the charge storage unit, the solid-state imaging device according to any one of claims 1 to 10 comprising a reset portion for discharging the signal charges from the charge storage part and the pre-charge accumulation portion. The solid-state imaging device according to claim 11 , further comprising a reset gate that resets a signal charge of the photoelectric conversion unit. The solid-state imaging device according to claim 11 , further comprising an overflow drain for the photoelectric conversion unit.

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