JP5193943B2 - Hall element manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a Hall element, and more particularly to a method for manufacturing a Hall element made of a compound semiconductor film having high mobility.

  The Hall element is a magnetic sensor that is formed of a compound semiconductor thin film having a thickness of several μm, and converts an electric field or a magnetic field into an electric signal using the Hall effect and outputs the electric signal. Usually, the compound semiconductor thin film has InSb or InAs. Etc. are used.

  There are several known manufacturing methods. For example, in the invention described in Patent Document 1, first, as shown in FIG. 2A, a silicon wafer 26 is used as a support, and the silicon wafer 26 is used. A thin insulating layer 28 of silicon dioxide is formed by performing an oxidation treatment on one surface side. Then, the compound semiconductor thin film 30 is formed on the insulating layer 28.

  Next, as shown in FIG. 2B, an element 32 is formed on the compound semiconductor thin film 30 by photolithography or the like, and an ohmic electrode 34 used as an input electrode and an output electrode is formed around the element 32.

Then, as shown in FIG. 2c, an insulating film 36 covering the element 32 and the ohmic electrode 34 is formed by Si ₃ N ₄ (silicon nitride) or the like, and then, on the insulating film 36 as shown in FIG. 2d. The element substrate 38 is bonded through the adhesive layer 40.

  Next, as shown in FIG. 2e, the silicon wafer 26 is removed by etching to expose the insulating layer 28. Then, the insulating layer 28 is etched, and as shown in FIG. Open.

  Thereafter, as shown in FIG. 2 g, the electrode terminal 44 of the ohmic electrode 34 is formed so as to fill the hole 42, and the insulating film 46 is formed on the remaining insulating layer 28. After conducting the electrical characteristic test, as a final step, dicing is performed at the position of the alternate long and short dash line 48 to obtain individual Hall elements.

  According to this manufacturing method, since the insulating layer 28 of silicon dioxide is formed on the silicon wafer 26 by surface oxidation, an insulating film that is thin but dense and has excellent insulating performance can be obtained. Overall thinning and low magnetic resistance can be achieved.

Japanese Patent No. 3161610

  However, in the above-described prior art, since the compound semiconductor thin film 30 is formed on the insulating layer 28 having a polycrystalline structure, a single crystal compound semiconductor thin film with high mobility cannot be obtained, and this achieves higher sensitivity. Making it difficult.

  Accordingly, an object of the present invention is to provide a method for manufacturing a Hall element comprising a single crystal compound semiconductor thin film having high mobility.

  In order to solve the above-described problems, a method for manufacturing a Hall element according to the present invention includes: a first support layer for forming a semiconductor thin film, wherein the first silicon layer is interposed between an insulating layer made of an oxide film on one surface side of the first silicon layer. A single-crystal compound semiconductor thin film used for a Hall element is formed on the second silicon layer using a SOI substrate on which a thinner second silicon layer is formed, to form a four-layer structure, After further laminating the core substrate of the Hall element via the adhesive on the compound semiconductor thin film side of the laminate, the SOI substrate is removed to expose the compound semiconductor thin film, and the exposed compound semiconductor thin film is patterned as required. After forming a plurality of element chips and forming an electrode portion including a pair of input electrodes and output electrodes on each element chip, the core substrate is diced to form a plurality of hoses. It is characterized by obtaining the element.

  In the present invention, the SOI substrate is removed from the first silicon layer side, the first silicon layer is removed by polishing or wet etching, the insulating layer is removed by predetermined etching, and the second silicon layer is removed. Is preferably removed by gas etching.

  As another aspect, the SOI substrate can be removed at once by gas etching the second silicon layer.

  The core substrate may be a non-magnetic material, but a magnetic material such as ferrite is preferably used.

  According to the present invention, the second silicon layer thinner than the first silicon layer is formed on the support substrate for forming the semiconductor thin film via the insulating layer made of the oxide film on one surface side of the first silicon layer. By using a SOI substrate and forming a compound semiconductor thin film on the second silicon layer, a Hall element made of a compound semiconductor thin film having a single crystal and high mobility can be obtained.

  Further, when the compound semiconductor thin film is exposed by removing the SOI substrate, since the second silicon layer is thin, it can be easily removed by gas etching without applying stress to the compound semiconductor thin film. it can.

The typical sectional view showing the SOI substrate applied to the present invention. The typical sectional view showing the state where the compound semiconductor thin film was formed in the above-mentioned SOI substrate. The typical sectional view showing the state where a core substrate is laminated on the above-mentioned compound semiconductor thin film. The typical sectional view showing the state where the core substrate was laminated on the compound semiconductor thin film. The typical sectional view showing the state where the 1st silicon layer of the above-mentioned SOI substrate was removed. The typical sectional view showing the state where the insulating layer of the above-mentioned SOI substrate was removed. The typical sectional view showing the state where the 2nd silicon layer of the above-mentioned SOI substrate was removed, and the compound semiconductor thin film was patterned and the element chip was formed. A typical sectional view showing the state where an electrode part was formed in the above-mentioned element chip. The typical perspective view which shows the Hall element manufactured by this invention. Typical sectional drawing for demonstrating the compound semiconductor thin film formation process in a prior art example. Typical sectional drawing for demonstrating the element and electrode formation process in a prior art example. Typical sectional drawing for demonstrating the insulating film formation process in a prior art example. Typical sectional drawing for demonstrating the element substrate formation process in a prior art example. Typical sectional drawing for demonstrating the silicon wafer removal process in a prior art example. Typical sectional drawing for demonstrating the electrode terminal formation process in a prior art example. Typical sectional drawing for demonstrating the dicing process in a prior art example.

  Next, an embodiment of the present invention will be described with reference to FIGS. 1a to 1i, but the present invention is not limited to this.

  First, as shown in FIG. 1a, an SOI substrate 10A is prepared as a support substrate for forming a semiconductor thin film. SOI is an abbreviation for Silicon On Insulator, and is formed on the SOI substrate 10A on the insulating layer 12, the first silicon layer 11, the insulating layer 12 formed on one surface of the first silicon layer 11. Three layers of the second silicon layer (single crystal) 13 are included. The SOI substrate 10A may be a general-purpose product used for manufacturing LSI or the like.

In this embodiment, the thickness of the first silicon layer 11 is about 500 μm, the thickness of the insulating layer 12 is about 5 μm, and the thickness of the second silicon layer 13 is about 5 μm. However, the thickness of each layer may be determined as appropriate. . The insulating layer 12 is preferably a silicon oxide film (SiO ₂ ).

  Next, as shown in FIG. 1b, a compound semiconductor thin film 14 used for a Hall element is formed on the second silicon layer 13 of the SOI substrate 10A by, for example, vapor deposition to form a laminated body 10B having a four-layer structure. To do.

  Since the second silicon layer 13 is single crystal, the single crystal compound semiconductor thin film 14 with high mobility can be formed on the second silicon layer 13. The compound semiconductor thin film 14 may be formed of InSb (indium antimony), InAs (indium arsenide), or the like used in a normal Hall element.

  Next, as shown in FIG. 1c, the compound semiconductor thin film 14 side of the laminate 10B is superposed on one surface of the core substrate 21 via the adhesive 22, and as shown in FIG. The substrate 21 is integrated. The core substrate 21 is preferably a magnetic material such as ferrite, but in some cases, a non-magnetic material may be employed.

  Since the first silicon layer 11 of the SOI substrate 10A is thick and has a certain degree of rigidity, the stacked body 10B and the core substrate 21 can be integrated without causing the compound semiconductor thin film 14 to crack or crack. Can do.

  Next, the SOI substrate 10A is sequentially removed from the first silicon layer 11 side to expose the compound semiconductor thin film 14. FIG. 1e shows a state where the first silicon layer 11 is removed.

The first silicon layer 11 may be removed by gas etching that specifically acts on Si, such as XeF ₂ (xenon fluoride), but the first silicon layer 11 is thick and expensive to completely remove. Since a large amount of gas is required, it is preferable to use polishing or wet etching in terms of cost.

In the case of wet etching, the insulating layer (SiO ₂ ) 12 present in the SOI substrate 10A functions as an etch stop layer. Therefore, it is possible to cover the disadvantage of wet etching that the unevenness of the surface to be etched becomes rough due to the difference in etching rate.

  Next, the insulating layer 12 is removed by etching. FIG. 1f shows a state where the insulating layer 12 is removed.

  Then, the last remaining second silicon layer 13 is removed to expose the compound semiconductor thin film 14, and the exposed compound semiconductor thin film 14 is subjected to patterning by photolithography or the like. As shown in FIG. A plurality of chips 14a serving as nuclei of is formed.

  The removal of the second silicon layer 13 is preferably performed by the gas etching described above. According to this, the thin second silicon layer 13 can be removed cleanly with almost no stress applied to the compound semiconductor thin film 14.

  Next, referring to FIG. 1h and FIG. 1i, an electrode portion 25 including a pair of input electrodes 23 and 23 and output electrodes 24 and 24 is formed around each chip 14a. The core substrate 21 is diced at the position indicated by the one-dot chain line to obtain the individual Hall elements 1 shown in FIG.

Thereafter, preferably after the electrical characteristics of each Hall element 1 are inspected, as a final process, a protective film is formed on the chip 14a and the electrode part 25 by SiO ₂ (silicon dioxide), Si ₃ N ₄ (silicon nitride) or the like. It is good to form.

  In removing the SOI substrate 10A, in the above-described embodiment, the SOI substrate 10A is sequentially removed from the first silicon layer 11 side. However, the portion of the second silicon layer 13 is gas-etched to remove the SOI substrate 10A all at once. Such an embodiment is also included in the present invention.

DESCRIPTION OF SYMBOLS 1 Hall element 10 SOI substrate 11 1st silicon layer 12 Insulating layer 13 2nd silicon layer 14 Compound semiconductor thin film 14a Chip 21 Core substrate 22 Adhesive 23 Input electrode 24 Output electrode 25 Electrode part

Claims (4)

An SOI substrate in which a second silicon layer thinner than the first silicon layer is formed on a support substrate for forming a semiconductor thin film via an insulating layer made of an oxide film on one surface side of the first silicon layer. Use
A single-crystal compound semiconductor thin film used for a Hall element is formed on the second silicon layer to form a four-layered laminate, and a core substrate of the Hall element is attached to the compound semiconductor thin film side of the laminate via an adhesive. After further stacking, the SOI substrate is removed to expose the compound semiconductor thin film, and the exposed compound semiconductor thin film is patterned in a predetermined manner to form a plurality of element chips. A hall element manufacturing method comprising: forming an electrode portion including an electrode and an output electrode; and then dicing the core substrate to obtain a plurality of hall elements.   The SOI substrate is removed from the first silicon layer side, the first silicon layer is removed by polishing or wet etching, the insulating layer is removed by predetermined etching, and the second silicon layer is removed by gas etching. The hall element manufacturing method according to claim 1, wherein the hall element is removed.   2. The method of manufacturing a Hall element according to claim 1, wherein the SOI substrate is removed by gas etching the second silicon layer.   4. The Hall element manufacturing method according to claim 1, wherein a magnetic material is used for the core substrate.

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