JP5028357B2 - Differential transmission circuit - Google Patents

Description

  The present invention relates to a circuit configuration for transmitting a differential signal.

  With the digitization and speeding up of electronic devices, it is necessary to transmit digital signals with high frequencies. Therefore, not only the external interface and the transmission cable between the boards in the device, but also the radiation noise generated from the wiring between the IC chips on the same board has become a big problem.

  As a countermeasure against this radiation noise, the differential transmission method is widely used. However, in the differential transmission method, the wiring of the transmission line intersects depending on the terminal arrangement of the IC chip, and as a result, the characteristic impedance is disturbed. . For this reason, if appropriate wiring that does not intersect is performed, IC chips having the same function and different terminal arrangements are required.

  Patent Document 1 describes a configuration of a printed wiring board that maintains isometricity and reduces disturbance of characteristic impedance even when wirings for differential transmission intersect.

  Patent Document 2 describes an integrated circuit having a shielding effect that protects a transmission signal from electromagnetic interference by surrounding a connection ball with a power supply and GND.

Patent Document 3 describes a technique for preventing signal quality degradation and noise emission by arranging a pair of data transmission circuits symmetrically on a substrate of a differential transmission circuit.
JP 2007-149805 A JP 2003-249904 A Japanese Patent Laid-Open No. 11-186664

  FIG. 14 shows the configuration of a conventional differential transmission circuit board.

  In FIG. 14, reference numeral 1400 denotes a transmission unit that transmits a pair of differential signals. Reference numeral 1410 denotes a receiving unit that receives the differential signal transmitted from the transmitting unit 1400. Each of the transmission unit 1400 and the reception unit 1410 includes, for example, BGA (Ball Gate Array) type P (positive logic) terminals 1401 and 1411 and N (negative logic) terminals 1402 and 1412. Reference numeral 1420 denotes a transmission path for transferring a differential signal. When the transmitter 1400 and the receiver 1410 are mounted on the same surface of the substrate 1480, the transmission path 1420 is equal in length and parallel.

  However, when the transmitter 1500 and the receiver 1510 are mounted on different surfaces such as the front surface and the back surface of the substrate 1580 as shown in FIG. 15, the P terminal 1501 and the N terminal 1502 of the receiver 1510 are the P terminal 1512 of the transmitter 1500. The position is reversed with respect to the N terminal 1511. For this reason, the transmission lines 1520 intersect and the characteristic impedances do not coincide with each other, so that the signal quality is lowered. A dotted line in FIG. 15 indicates that the receiving unit 1510 is mounted on the surface of the substrate 1580 opposite to the transmitting unit 1500.

  FIG. 16 shows a state in which the transmission unit and the reception unit are mounted on the same surface on the substrate in the differential transmission method for transmitting a plurality of signals.

  In FIG. 16, reference numeral 1600 denotes a transmission unit that transmits a differential signal. Reference numeral 1610 denotes a reception unit that receives the differential signal transmitted from the transmission unit 1600. Reference numeral 1620 denotes a transmission path for transferring a differential signal. Reference numerals 1601 and 1602 denote input signals for generating a differential signal. Reference numerals 1603 and 1604 denote flip-flop circuits for holding the input signals 1601 and 1602 of Data1 and Data2, respectively. Reference numerals 1605 and 1606 denote buffers for generating differential signals from the input signals 1601 and 1602, respectively. Reference numerals 1615 and 1616 denote buffers that receive a differential signal transmitted via the transmission line 1620 and output a difference. Reference numerals 1611 and 1612 denote output signals generated from the buffers 1615 and 1616, respectively. Reference numerals 1613 and 1614 denote flip-flop circuits for holding output signals 1611 and 1612, respectively. Differential signals are generated from the input signals 1601 and 1602 by the buffers 1605 and 1606, respectively, and transmitted to the receiving unit 1610 via the transmission line 1620. The flip-flop circuits 1613 and 1614 hold the output signals 1611 and 1612 generated by the buffers 1615 and 1616 from the received differential signals.

  FIG. 17 shows a state where the transmitter and the receiver are mounted on different surfaces on the substrate.

  In FIG. 17, 1780 is a circuit board, and 1781 is a via hole. In this case, if the transmission path 1720 is kept the same length and parallel, the signals are exchanged in the transmission unit 1700 and the reception unit 1710 as illustrated. If the signals are not interchanged, the transmission line 1820 intersects as shown in FIG. 18, making it difficult to control the characteristic impedance of the transmission line.

  Here, in the above-mentioned Patent Document 1, when the input unit and the output unit are mounted on different surfaces on the substrate, if there are a plurality of pairs of differential signals, the wirings of the transmission lines of each pair cross each other. Cannot handle.

  In Patent Document 2, the connection balls are arranged symmetrically with respect to the plane perpendicular to the substrate. However, in this case, when the transmission unit and the reception unit are mounted on different surfaces on the substrate in differential transmission, the transmission path is Crossing and characteristic impedance does not match. For this reason, the subject that the quality of a signal falls cannot be solved.

  Furthermore, just by arranging differential signal transmission lines symmetrically as in Patent Document 3, it is not possible to cope with signal quality degradation due to disturbance of characteristic impedance at the time of wiring crossing.

  The present invention has been made in view of the above problems, and enables a transmitter and a receiver to be mounted on different surfaces of a substrate with an IC chip having the same terminal arrangement while keeping the transmission lines in the differential transmission system parallel and equal in length. A circuit configuration is realized.

In order to solve the above-described problem, a differential transmission circuit according to the present invention generates a pair of differential signals from an input signal and transmits the differential signal, and receives the differential signal transmitted from the transmission unit. A transmission unit that transmits the differential signal from the transmission unit to the reception unit, and the transmission unit selects either the input signal or a signal obtained by inverting the polarity of the input signal. A differential transmission circuit that generates the differential signal from the signal selected by the selection unit, and the input signal includes a first input signal and a second input signal, The differential signal includes a first differential signal and a second differential signal, and the transmission path transmits a first differential signal from the transmission unit to the reception unit. And a second transmission path for transmitting the second differential signal from the transmission unit to the reception unit; The selection unit includes a first selection unit that selects one of the first input signal and a signal obtained by inverting the polarity of the first input signal, the second input signal, and the first input signal. A second selection unit that selects one of the signals obtained by inverting the polarity of the input signal, a signal selected by the first selection unit, and a signal selected by the second selection unit. A third selection unit that selects a third signal as a third signal, and a second selection unit that selects any one of the signal selected by the first selection unit and the signal selected by the second selection unit as a fourth signal. 4, and the transmitter generates the first differential signal from the third signal and the second differential signal from the fourth signal .

The differential transmission circuit of the present invention includes a transmission unit that generates and transmits a pair of differential signals from an input signal, a reception unit that receives the differential signal transmitted from the transmission unit, and the differential A transmission path for transmitting a signal from the transmission unit to the reception unit, and the reception unit receives either a differential signal obtained by taking a difference between the differential signals or a signal obtained by inverting the polarity of the differential signal. A differential transmission circuit having a selection unit for selecting and generating an output signal from the signal selected by the selection unit, wherein the input signal includes a first input signal and a second input signal; The differential signal includes a first differential signal and a second differential signal, the output signal includes a first output signal and a second output signal, and the transmission path includes the first difference signal. A first transmission path for transmitting a motion signal from the transmitter to the receiver, and the second differential signal A second transmission line that transmits from the transmission unit to the reception unit, and the selection unit takes a first differential signal generated from the first input signal. A difference between the first differential unit that selects either the differential signal or the signal obtained by inverting the polarity of the first differential signal and the second differential signal generated from the second input signal is obtained. A second selection unit that selects one of the second difference signal and a signal obtained by inverting the polarity of the second difference signal, the signal selected by the first selection unit, and the second selection A third selection unit that selects one of the signals selected by the unit, and a fourth selection unit that selects any one of the signal selected by the first selection unit and the signal selected by the second selection unit. And the reception unit receives the first signal from the signal selected by the third selection unit. To generate a force signal, to generate the second output signal from the selected signal by the fourth selector.
The differential transmission circuit of the present invention is a differential transmission circuit including an input signal, a pair of differential signals generated from the input signal, and an output signal generated from the differential signal. The input signal includes a first input signal and a second input signal, and the differential signal includes a first differential signal and a second differential signal, and the first input signal and A first selection unit that selects one of the signals obtained by inverting the polarity of the first input signal; and one of the signals obtained by inverting the polarity of the second input signal and the second input signal. A second selection unit that selects, a third selection unit that selects one of the signal selected by the first selection unit and the signal selected by the second selection unit as a third signal; Either the signal selected by the first selection unit or the signal selected by the second selection unit is a fourth A fourth selector that selects as a signal; and a generator that generates the first differential signal from the third signal and generates the second differential signal from the fourth signal. .
Moreover, the differential transmission circuit of the present invention includes an input signal, a pair of differential signals generated from the input signal, and an output signal generated from the differential signal. The input signal includes a first input signal and a second input signal, the differential signal includes a first differential signal and a second differential signal, and the output signal is A first differential signal having a first output signal and a second output signal and taking the difference between the first differential signals generated from the first input signal and the polarities of the first differential signal A first selection unit that selects one of the inverted signals, a second differential signal obtained by taking a difference between the second differential signal generated from the second input signal, and the second A second selection unit that selects one of the signals obtained by inverting the polarity of the difference signal, and selection by the first selection unit A third selection unit that selects one of the selected signal and the signal selected by the second selection unit, and the signal selected by the first selection unit and the second selection unit. A fourth selector that selects one of the signals; and the first output signal is generated from the signal selected by the third selector and the first output signal is selected from the signal selected by the fourth selector. A generating unit that generates two output signals.

  According to the present invention, it is possible to mount the transmission unit and the reception unit on different surfaces of the substrate with IC chips having the same terminal arrangement while maintaining the transmission lines in the differential transmission system in parallel and in the same length.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

  The embodiment described below is an example as means for realizing the present invention, and should be appropriately modified or changed according to the configuration and various conditions of the apparatus to which the present invention is applied. It is not limited to the embodiment.

[First Embodiment]
FIG. 1 shows the configuration of a differential transmission circuit board according to a first embodiment of the present invention.

  In FIG. 1, reference numeral 100 denotes a transmission unit that transmits a pair of differential signals, and reference numeral 110 denotes a reception unit that receives the differential signals transmitted from the transmission unit 100. Reference numeral 120 denotes a transmission path for transferring a differential signal. Reference numeral 101 denotes an input signal for generating a differential signal, and reference numeral 102 denotes a flip-flop circuit for holding the input signal 101. Reference numeral 103 denotes an inverter for inverting the polarity of the input signal 101, and reference numeral 104 denotes a selector (selection unit) that selects either the input signal 101 or the signal from the inverter 103. Reference numeral 105 denotes a buffer that generates a differential signal from the signal selected by the selector 104. Reference numeral 115 denotes a buffer that receives the differential signal generated by the buffer 105 and transmitted via the transmission path 120 and outputs a difference (difference signal). It is. Reference numeral 112 denotes a flip-flop circuit for holding the output signal 111 generated by the buffer 115. Reference numeral 180 denotes a circuit board.

  The state of the signal until the output signal 111 is obtained is shown in FIG. In the figure, a, b, c, d, and e indicate signals in each wiring of FIG. In the figure, H and L indicate the high level and low level of the signal, respectively. A dotted line 300 is a common mode voltage for a differential signal.

  When the transmission unit 100 and the reception unit 110 are mounted on the same surface on the substrate, the transmission path 120 is equal in length and parallel. In this case, the selector 104 selects the input signal 101 from the flip-flop 102. A differential signal generated by the buffer 105 from the signal selected by the selector 104 is transmitted from the transmission unit 100 to the reception unit 110 via the transmission path 120. An output signal 111 generated by the buffer 115 from the received differential signal is held in the flip-flop 112. If the input signal 101 is a signal having a waveform like a, the signal b selected by the selector 104 also has the same waveform. The differential signals generated by the buffer 105 are c and d, respectively, and the output signal 111 generated from the difference cd in the buffer 115 has a waveform e.

  FIG. 2 shows a state where the transmitter and the receiver are mounted on different surfaces on the substrate.

  In FIG. 2, 280 is a circuit board, and 281 is a via hole. In order to keep the transmission line 220 parallel and equal in length, the polarity of the buffer 215 is changed. In this case, the selector 204 selects a signal obtained by inverting the polarity of the input signal 201 from the flip-flop 202 in the inverter 203. A differential signal generated by the inverter 205 from the signal selected by the selector 204 is transmitted from the transmission unit 200 to the reception unit 210 via the transmission path 220. An output signal 211 generated by the buffer 215 from the received differential signal is held in the flip-flop 212. Assuming that the input signal 201 has a waveform like a, the signal b selected by the selector 204 has a waveform inverted by the inverter 203. The differential signals generated by the buffer 205 are c and d, respectively, and the output signal 211 generated from the difference dc in the buffer 215 has a waveform like e, which is the same output signal as when mounted on the same surface. Will be obtained.

  According to this embodiment, when transmitting a signal by the differential transmission method, it is possible to cope with the case where the transmitting unit and the receiving unit are mounted on the same surface or different surfaces of the substrate with an IC chip having the same terminal arrangement. Can realize a differential transmission circuit. In addition, it is possible to cope with the reduction in the area of the substrate and the downsizing of the apparatus.

[Second Embodiment]
FIG. 4 shows the configuration of the differential transmission circuit board of the second embodiment.

  In FIG. 4, reference numeral 400 denotes a transmission unit that transmits a differential signal, and reference numeral 410 denotes a reception unit that receives the differential signal transmitted from the transmission unit 400. Reference numeral 420 denotes a transmission path for transferring differential signals. 401 is an input signal for generating a differential signal, and 402 is a flip-flop circuit for holding the input signal 401. Reference numeral 405 denotes a buffer for generating a differential signal from the input signal 401, and reference numeral 415 denotes a buffer that receives the differential signal generated by the buffer 405 and transmitted via the transmission path 420 and outputs a difference (difference signal). is there. Reference numeral 413 denotes an inverter for inverting the polarity of the signal output from the buffer 415. Reference numeral 414 denotes a selector for selecting one of the signal from the buffer 415 and the signal from the inverter 413. Reference numeral 412 denotes a flip-flop circuit for holding the output signal 411 selected by the selector 414. Reference numeral 480 denotes a circuit board.

  When the transmission unit 400 and the reception unit 410 are mounted on the same surface of the substrate, a differential signal is generated from the input signal 401 and transmitted from the transmission unit 400 to the reception unit 410 via the transmission path 420. The selector 414 selects a signal generated by the buffer 415 from the received differential signal and holds it in the flip-flop 412.

  FIG. 5 shows a state where the transmitter and the receiver are mounted on different surfaces on the substrate.

  In FIG. 5, 580 is a circuit board, and 581 is a via hole. In order to keep the transmission line 520 parallel and equal in length, the polarity of the buffer 515 is switched. In this case, the selector 514 selects the signal generated by the buffer 515 from the received differential signal and inverted in polarity by the inverter 513, whereby the same output signal as when mounted on the same surface is obtained and held in the flip-flop 512. The

  According to this embodiment, when transmitting a signal by the differential transmission method, it is possible to cope with the case where the transmitting unit and the receiving unit are mounted on the same surface or different surfaces of the substrate with an IC chip having the same terminal arrangement. Can realize a differential transmission circuit. In addition, it is possible to cope with the reduction in the area of the substrate and the downsizing of the apparatus.

[Third Embodiment]
FIG. 6 shows the configuration of the differential transmission circuit board of the third embodiment.

  In FIG. 6, reference numeral 600 denotes a transmission unit that transmits a differential signal. Reference numeral 620 denotes a receiving unit that receives the differential signal transmitted from the transmitting unit 600. Reference numerals 640a and 640b denote transmission paths (first transmission path and second transmission path) for transferring differential signals. Reference numerals 601 and 602 denote input signals (first input signal and second input signal) for generating differential signals (first differential signal and second differential signal). Reference numerals 610 and 611 denote flip-flop circuits for holding input signals 601 and 602 of Data1 and Data2, respectively. Reference numerals 612 and 613 denote inverters for inverting the polarities of the respective input signals 601 and 602. Reference numeral 614 denotes a selector (first selection unit) that selects either the input signal 601 or the signal from the inverter 612. Reference numeral 615 denotes a selector (second selection unit) that selects either the input signal 602 or the signal from the inverter 613. Reference numerals 616 and 617 denote selectors (third selection unit and fourth selection unit) that select either the signal from the selector 614 or the signal from the selector 615 as the third signal or the fourth signal. Reference numerals 618 and 619 denote buffers for generating a difference (difference signal) between signals from the selectors 616 and 617, respectively. Reference numerals 632 and 633 denote buffers that receive signals generated by the inverters 618 and 619 and transmitted via the transmission lines 640a and 640b, respectively, and output a difference (difference signal). Reference numerals 621 and 622 denote output signals (first output signal and second output signal) generated from the buffers 632 and 633, respectively. Reference numerals 630 and 631 denote flip-flop circuits for holding the output signals 621 and 622, respectively.

  When the transmitter 600 and the receiver 620 are mounted on the same surface on the substrate, the selectors 614 and 615 select the input signals 601 and 602, respectively. The selector 616 selects the signal from the selector 614, and the selector 617 selects the signal from the selector 615. Differential signals generated by the buffers 618 and 619 from the selected signal are transmitted from the transmission unit 600 to the reception unit 620 via the transmission paths 640a and 640b, respectively. Output signals generated by the buffers 632 and 633 from the received differential signals are held in flip-flops 630 and 631, respectively.

  FIG. 7 shows a state where the transmitter and the receiver are mounted on different surfaces on the substrate.

  In FIG. 7, 780 is a circuit board and 781 is a via hole. The polarities of the buffers 732 and 733 are switched in order to keep the transmission lines 740a and b parallel and equal in length. In this case, the selectors 714 and 715 select signals obtained by inverting the polarities of the input signals 701 and 702 in the inverters 712 and 713, respectively. The selector 716 selects the signal from the selector 715, and the selector 717 selects the signal from the selector 714, thereby switching the input signals of Data1 and Data2. Differential signals generated by the buffers 718 and 719 from the signals selected by the selectors 716 and 717 are transmitted to the receiving unit 720 via the transmission paths 740a and 740b. From the received differential signal, the same output signals 721 and 722 as those on the same surface mounting are obtained by the buffers 732 and 733 and held in the flip-flops 730 and 731, respectively. Although the case where two signals are transmitted has been described, the present invention can be applied to the case where three or more signals are transmitted.

  According to the present embodiment, when a plurality of signals are transmitted by the differential transmission method, the transmitter and the receiver are mounted on the same surface or different surfaces of the substrate with an IC chip having the same terminal arrangement. A compatible differential transmission circuit can be realized. In addition, it is possible to cope with the reduction in the area of the substrate and the downsizing of the apparatus.

[Fourth Embodiment]
In differential transmission in which a plurality of signals are transmitted, if any of the plurality of input signals is a clock signal, the transmitter unit hits a preceding flip-flop as shown in FIG. 8, for example, to match the output timing. A mechanism to synchronize the clock is required.

  In FIG. 8, reference numeral 800 denotes the configuration of the transmission unit of the differential transmission circuit. Reference numeral 801 denotes a DDR (Double Data Rate) type clock. Reference numeral 802 denotes an inverter that inverts the clock 801. Reference numerals 803 and 804 denote flip-flops for holding differential transmission input signals Data and Clk. Reference numerals 805 and 806 denote buffers for generating differential signals from the signals from the flip-flops 803 and 804, respectively.

  FIG. 9 shows the configuration of the differential transmission circuit board of the fourth embodiment.

  In FIG. 9, reference numeral 900 denotes a transmission unit that transmits a differential signal. Reference numeral 920 denotes a receiving unit that receives the differential signal transmitted from the transmitting unit 900. Reference numerals 940a and 940b denote transmission lines (first transmission line and second transmission line) for transferring differential signals. Reference numerals 901 and 902 denote input signals (first input signal and second input signal) for generating a differential signal. Reference numerals 910 and 911 denote flip-flop circuits for holding Data and Clk input signals 901 and 902, respectively. Reference numerals 912 and 913 denote buffers for generating differential signals (first differential signal and second differential signal) from the input signals 901 and 902, respectively. Reference numerals 930 and 931 denote buffers that receive differential signals transmitted via the transmission paths 940a and 940b, respectively, and output differences (first differential signal and second differential signal). Reference numerals 932 and 933 denote inverters for inverting the polarities of the signals from the buffers 930 and 931, respectively. Reference numeral 934 denotes a selector (first selection unit) that selects one of the signal from the buffer 930 and the signal from the inverter 932. Reference numeral 935 denotes a selector (second selection unit) that selects one of the signal from the buffer 931 and the signal from the inverter 933. Reference numerals 936 and 937 denote selectors (third selection unit and fourth selection unit) that select one of the signal from the selector 934 and the signal from the selector 935 as the third signal or the fourth signal. Reference numeral 921 denotes an output signal generated from the selector 936. Reference numeral 922 denotes an output signal in which the frequency of the signal from the selector 937 is doubled. Reference numeral 938 denotes a flip-flop circuit for holding the output signal 921. Reference numeral 939 denotes a PLL (Phase Locked Loop) circuit for multiplying the frequency of the signal.

  Here, a case where the transmission unit and the reception unit are mounted on the same surface on the substrate will be described.

  Differential signals are generated from the input signals 901 and 902 by the buffers 912 and 913, and transmitted to the receiving unit 920 via the transmission paths 940a and 940b. The selectors 934 and 935 select the signals generated by the buffers 930 and 931 from the received differential signals. The selector 936 selects a signal from the selector 934, and the selector 937 selects a signal from the selector 935. The output signal 921 from the selector 936 is held in the flip-flop circuit 938, and the frequency of the output signal 922 from the selector 937 is doubled by the PLL circuit 939. The waveform obtained by this is shown in FIG. Reference numerals 1001 and 1002 denote a Data signal and a Clk signal to be transmitted, respectively. Reference numeral 1022 denotes a Clk signal obtained by doubling the frequency of the received Clk signal using a PLL circuit. Reference numeral 1021 denotes a received Data signal.

  FIG. 11 shows a state where the transmitter and the receiver are mounted on different surfaces on the substrate.

  In FIG. 11, 1180 is a circuit board and 1181 is a via hole. In this case, the polarities of the buffers 1130 and 1131 are switched in order to keep the transmission lines 1140a and b parallel and equal in length. Differential signals are generated from the input signals 1101 and 1102 by the buffers 1112 and 1113 and transmitted to the receiving unit 1120 via the transmission lines 1140a and 1140b. The selectors 1134 and 1135 select signals generated by the buffers 1130 and 1131 from the received differential signals and inverted in polarity by the inverters 1132 and 1133, respectively. The selector 1136 selects the signal from the selector 1135, and the selector 1137 selects the signal from the selector 1134, thereby switching the Data signal and the Clk signal. The output signals 1121 and 1122 from the selectors 1136 and 1137 become the same output signals as those on the same surface, the output signal 1121 is held in the flip-flop circuit 1138, and the frequency of the output signal 1122 is doubled by the PLL circuit 1139. Although the case where the signals to be transmitted are one Data signal and Clk signal has been described, the present invention can be applied to the case where two or more Data signals and Clk signals are transmitted.

  According to the present embodiment, when transmitting a plurality of signals including a clock signal by the differential transmission method, the transmitter and the receiver are mounted on the same surface or different surfaces of the substrate with an IC chip having the same terminal arrangement. In this case, a differential transmission circuit that can cope with this can be realized. In addition, it is possible to cope with the reduction in the area of the substrate and the downsizing of the apparatus.

[Fifth Embodiment]
As described with reference to FIG. 8, when any of the plurality of input signals is a clock signal, a mechanism is required to synchronize the clock by hitting the previous flip-flop in the transmission unit in order to match the output timing.

  FIG. 12 shows, as a fifth embodiment, a differential transmission circuit for exchanging data signals so as to have line symmetry with respect to the clock signal when an even number of data signals are transmitted with respect to one clock signal. The structure of a circuit board is shown.

  In FIG. 12, reference numeral 1200 denotes a transmission unit that transmits a differential signal, and reference numeral 1220 denotes a reception unit that receives the differential signal transmitted from the transmission unit 1200. Reference numerals 1240a, c, and b denote transmission paths (first transmission path, third transmission path, and second transmission path) for transferring all differential signals. 1201, 1202, and 1203 are input signals (first input signal, third input signal, and second input signal) for generating a differential signal. Reference numerals 1211, 1212, and 1213 denote flip-flop circuits for holding the input signals 1201, 1202, and 1203 of Data1, Clk, and Data2, respectively. Reference numerals 1214, 1215, and 1216 denote buffers for generating differential signals (first differential signal, third differential signal, and second differential signal) from the input signals 1201, 1202, and 1203, respectively. Buffers 1230, 1231, and 1232 receive differential signals transmitted via the transmission paths 1240a, c, and b, respectively, and output differences (first difference signal, third difference signal, and second difference signal). It is. Reference numerals 1233, 1250, and 1234 denote inverters for inverting the polarities of the signals from the buffers 1230, 1231, and 1232. Reference numerals 1235, 1251, and 1236 are selectors (first selection unit, fifth selection unit, and second selection unit) for selecting whether signals from the buffers 1230, 1231, and 1232 are passed through the inverters 1233, 1250, and 1234. is there. Reference numerals 1237 and 1238 denote selectors (third selection unit and fourth selection unit) for exchanging signals selected by the selectors 1235 and 1236 as necessary. Reference numerals 1221 and 1223 denote output signals generated from the selectors 1237 and 1238, respectively. Reference numeral 1222 denotes an output signal obtained by doubling the frequency of the signal from the selector 1251. Reference numerals 1224 and 1226 denote flip-flop circuits for holding output signals 1221 and 1223, respectively. Reference numeral 1225 denotes a PLL (Phase Locked Loop) circuit for multiplying the frequency of the signal.

  Next, a case where the transmission unit and the reception unit are mounted on the same surface on the substrate will be described.

  Differential signals are generated from the input signals 1201, 1202, and 1203 by the buffers 1214, 1215, and 1216 and transmitted to the receiving unit 1220 via the transmission paths 1240 a, c, and b. The selectors 1235 and 1236 select the signals generated by the buffers 1230 and 1232 from the received differential signals, and the selected signals are selected as the output signals 1221 and 1223 by the selectors 1237 and 1238 without being replaced. Output signals 1221 and 1223 are held in flip-flop circuits 1224 and 1226, respectively. A signal generated by the buffer 1231 from the received differential signal and selected by the selector 1251 is multiplied in frequency by the PLL circuit 1225 and becomes a clock of the flip-flop circuits 1224 and 1226 as an output signal 1222 of Clk.

  FIG. 13 shows a state where the transmitter and the receiver are mounted on different surfaces on the substrate.

  In FIG. 13, 1380 is a circuit board, and 1381 is a via hole. According to this configuration, transmission lines 1340a. c. In order to keep b parallel and equal in length, the polarities of the buffers 1330, 1331 and 1332 are switched. Differential signals are generated from the input signals 1301, 1302, and 1303 by the buffers 1314, 1315, and 1316 and transmitted to the receiving unit 1320 via the transmission paths 1340 a, c, and b.

  The selectors 1335, 1351, and 1336 select signals that are generated in the buffers 1330, 1331, and 1332 from the differential signals received via the transmission lines 1340a, c, and b, and are inverted in polarity in the inverters 1333, 1350, and 1334, respectively. To do. The selector 1337 selects the signal from the selector 1336, the selector 1338 selects the signal from the selector 1335, and holds them in the flip-flop circuits 1324 and 1326 as output signals 1321 and 1323, respectively. The signal generated in the buffer 1331 from the differential signal received via the transmission lines 1340a, c, b and the frequency selected by the selector 1351 is multiplied by the PLL circuit 1325. Then, the output signal 1322 of Clk becomes a clock signal of the flip-flop circuits 1324 and 1326.

  Here, the case where two Data signals and one Clk signal are transmitted from the transmission unit and the Data signal is replaced by the reception unit has been described. However, when four or more Data signals are transmitted, or the Data signal is transmitted by the transmission unit. Even in the case of replacement, the present invention is applicable.

  According to this embodiment, when an even number of data signals are transmitted with respect to one clock signal by a differential transmission method, an IC chip having the same terminal arrangement is used to transmit and receive a transmitter and a receiver on the same surface of the substrate and different from each other. It is possible to realize a differential transmission circuit that can cope with mounting on either surface. In addition, it is possible to cope with the reduction in the area of the substrate and the downsizing of the apparatus.

It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 1st Embodiment based on this invention on the same surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 1st Embodiment based on this invention on the different surface on a board | substrate. It is a figure which shows the mode of the signal until an output signal is obtained in the differential transmission circuit of 1st Embodiment. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 2nd Embodiment on the same surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 2nd Embodiment on the different surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 3rd Embodiment on the same surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 3rd Embodiment on the different surface on a board | substrate. It is a figure which shows the structure of the transmission part of a differential transmission circuit. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 4th Embodiment on the same surface on a board | substrate. It is a figure which shows the signal waveform obtained by the differential transmission circuit of 4th Embodiment. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 4th Embodiment on the different surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 5th Embodiment on the same surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of 5th Embodiment on the different surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of a prior art example on the same surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of a prior art example on the different surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of a prior art example on the same surface on a board | substrate. It is a figure which shows the board | substrate structure at the time of mounting the differential transmission circuit of a prior art example on the different surface on a board | substrate. FIG. 18 is a diagram showing a circuit configuration for preventing signals from being interchanged in the differential transmission circuit of FIG. 17.

Claims (7)

A transmitter that generates and transmits a pair of differential signals from an input signal, a receiver that receives the differential signals transmitted from the transmitter, and transmits the differential signals from the transmitter to the receiver The transmission unit includes a selection unit that selects either the input signal or a signal obtained by inverting the polarity of the input signal, and the difference from the signal selected by the selection unit A differential transmission circuit for generating a dynamic signal,
The input signal comprises a first input signal and a second input signal;
The differential signal includes a first differential signal and a second differential signal,
The transmission path includes a first transmission path for transmitting the first differential signal from the transmission section to the reception section, and a second transmission path for transmitting the second differential signal from the transmission section to the reception section. A transmission line, and
The selection unit selects a first selection unit that selects either the first input signal or a signal obtained by inverting the polarity of the first input signal, the second input signal, and the second input. A second selection unit that selects any one of the signals with the polarity of the signal inverted; a third signal that is selected by the first selection unit and a signal that is selected by the second selection unit; A third selection unit that selects the first signal, and a fourth selection that selects either the signal selected by the first selection unit or the signal selected by the second selection unit as the fourth signal. And comprising
The transmission unit generates the first differential signal from the third signal and generates the second differential signal from the fourth signal . A transmitter that generates and transmits a pair of differential signals from an input signal, a receiver that receives the differential signals transmitted from the transmitter, and transmits the differential signals from the transmitter to the receiver A transmission path, and the reception unit includes a selection unit that selects one of a difference signal obtained by taking a difference between the differential signals and a signal obtained by inverting the polarity of the difference signal. A differential transmission circuit for generating an output signal from the signal selected in
The input signal comprises a first input signal and a second input signal;
The differential signal includes a first differential signal and a second differential signal,
The output signal comprises a first output signal and a second output signal,
The transmission path includes a first transmission path for transmitting the first differential signal from the transmission section to the reception section, and a second transmission path for transmitting the second differential signal from the transmission section to the reception section. A transmission line, and
The selection unit selects one of a first difference signal obtained by taking a difference between the first differential signals generated from the first input signal and a signal obtained by inverting the polarity of the first difference signal. A first selection unit to be selected, a second differential signal obtained by taking a difference between the second differential signal generated from the second input signal, and a signal obtained by inverting the polarity of the second differential signal A second selection unit that selects any one of the signal, a third selection unit that selects any one of the signal selected by the first selection unit and the signal selected by the second selection unit, A fourth selection unit that selects one of the signal selected by the first selection unit and the signal selected by the second selection unit;
The reception unit generates the first output signal from the signal selected by the third selection unit, and generates the second output signal from the signal selected by the fourth selection unit. A differential transmission circuit characterized by the above. The input signal further comprises a third input signal, the differential signal further comprises a third differential signal,
The transmission path further includes a third transmission path for transmitting the third differential signal from the transmission unit to the reception unit,
The terminal of the first input signal and the terminal of the second input signal are arranged symmetrically with respect to the terminal of the third input signal,
The receiving unit may further include any one of a third differential signal obtained by taking a difference between the third differential signals generated from the third input signal and a signal obtained by inverting the polarity of the third differential signal. A fifth selection unit for selecting
Said third and of generating said first output signal from the selected signal in the selected signal and the fifth selector by the selection unit, the fourth selection portion signal and the fifth selected The differential transmission circuit according to claim 2 , wherein the second output signal is generated from a signal selected by a selection unit. 4. The differential transmission circuit according to claim 3 , wherein the first input signal and the second input signal are data signals, and the third input signal is a clock signal.   A differential transmission circuit comprising an input signal, a pair of differential signals generated from the input signal, and an output signal generated from the differential signal,
  The input signal comprises a first input signal and a second input signal;
  The differential signal includes a first differential signal and a second differential signal,
  A first selector for selecting one of the first input signal and a signal obtained by inverting the polarity of the first input signal; and the polarity of the second input signal and the second input signal are inverted. A second selection unit that selects any one of the selected signals, and a signal selected by the first selection unit and a signal selected by the second selection unit are selected as a third signal. A third selection unit; a fourth selection unit that selects any one of the signal selected by the first selection unit and the signal selected by the second selection unit as a fourth signal; and And a generation unit that generates the first differential signal from the third signal and generates the second differential signal from the fourth signal.   A differential transmission circuit comprising an input signal, a pair of differential signals generated from the input signal, and an output signal generated from the differential signal,
  The input signal comprises a first input signal and a second input signal;
  The differential signal includes a first differential signal and a second differential signal,
  The output signal comprises a first output signal and a second output signal,
  A first differential signal obtained by taking a difference between the first differential signals generated from the first input signal and a signal obtained by inverting the polarity of the first differential signal are selected. Select one of a selection unit and a second difference signal obtained by taking a difference between the second differential signal generated from the second input signal and a signal obtained by inverting the polarity of the second difference signal A second selection unit that selects one of the signal selected by the first selection unit and the signal selected by the second selection unit, and the first selection unit. A first selection signal is generated from the signal selected by the third selection unit and the fourth selection unit that selects either the signal selected by the second selection unit or the signal selected by the second selection unit And a generator that generates the second output signal from the signal selected by the fourth selector; Differential transmission circuit, characterized in that it comprises a.   The input signal further comprises a third input signal, the differential signal further comprises a third differential signal,
  The terminal of the first input signal and the terminal of the second input signal are arranged symmetrically with respect to the terminal of the third input signal,
  Further, the third differential signal obtained by taking the difference between the third differential signals generated from the third input signal and the signal obtained by inverting the polarity of the third differential signal are selected. With a selection part
  The first output signal is generated from the signal selected by the third selector and the signal selected by the fifth selector, and the signal selected by the fourth selector and the fifth The differential transmission circuit according to claim 6, wherein the second output signal is generated from the signal selected by the selection unit.

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