JP5021551B2 - Image reading apparatus and method - Google Patents

Description

  The present invention samples an analog image data signal generated by reading a document at a predetermined sample and hold timing, holds the sampled analog image data signal for a certain period of time, and outputs it from the sample and hold circuit. The present invention relates to an image reading apparatus and method for converting the output of the above into quantized image data and performing image processing on the image data.

  In general, in an image reading apparatus that reads a document image, a document placed on a document table is exposed by an exposure device, the reflected light of the document is incident on a line image sensor, the document is read, and output from the line image sensor. The analog image signal is sampled and converted into a digital signal to form read image data.

  FIG. 15 shows a configuration example of an optical system of the image reading apparatus. In FIG. 15, a contact glass 2 (original platen) is disposed on the upper surface of the housing 1 of the image reading apparatus, and a read original 3 is placed on the contact glass 2. Normally, a pressure plate for bringing the reading surface of the reading document 3 into close contact with the contact glass 2 is provided on the back surface of the reading document 3, but is omitted in FIG. A white reference plate 4 is provided at the left end (reading start position) of the contact glass 2 in order to form a white reference image for shading correction.

  The lamp 5 illuminates the document surface of the read document 3, and the reflected light from the document surface is sequentially reflected by the first mirror 6, the second mirror 7, and the third mirror 8 to the lens 11. The incident light is focused by the lens 11 and irradiated to the CCD line image sensor 13 provided on the reading control board 12.

  The lamp 5 and the first mirror 6 are mounted on the first carriage 9 and reciprocated in the sub-scanning direction SS, and the second mirror 7 and the third mirror 8 are mounted on the second carriage 10 and mounted on the sub-scanning direction SS. Reciprocates in the scanning direction SS. Further, in order to maintain the optical path length from the contact glass 2 to the CCD line image sensor 13, the second carriage 10 is moved at a speed half that of the first carriage 9.

  The scanner motor 14 is a motor for driving the first carriage 9 and the second carriage 10.

  FIG. 16 is a block diagram of a conventional signal processing unit from the output of the CCD line image sensor 13 to obtaining a digital image signal.

  First, an image signal is output from the CCD line image sensor 13 in synchronization with the drive pulse. This image signal is AC-coupled by a capacitor 23 via a buffer circuit 22 (usually composed of an emitter follower circuit), and is input to a signal processing integrated circuit device (AFE: Analog Front End) 28.

  The signal processing integrated circuit device 28 includes a clamp circuit 24, a sample hold circuit (S / H: Sample-Hold) 25, an amplifier circuit (PGA: Programmable Gain Amplifier) 26, and an analog / digital converter circuit (ADC: Analog-Digital Converter). 27 is an integrated circuit. The image signal input to the signal processing integrated circuit device 28 is first input to the clamp circuit 24. The clamp circuit 24 clamps the black offset level of the image signal to a predetermined potential at the input timing of the clamp signal CLP.

  The sample hold circuit (S / H) 25 samples the image signal output from the clamp circuit 24 at the input timing of the sample hold pulse SHD, and holds the sampled image signal for a certain period of time to continuously analog the image signal. Output as an image signal. Thereafter, the amplification circuit (PGA) 26 amplifies the output of the analog image signal to a certain level, and then the analog / digital conversion circuit (ADC) 27 converts the amplified analog image signal at the input timing of the conversion timing signal ADCLK. For example, it is converted into a 10-bit digital image signal (image data).

  The digital image signal thus obtained is transmitted to a subsequent image processing unit (not shown), and reflected from the white reference plate irradiated by the lamp 5 in a shading correction circuit (not shown) in the image processing unit. By reading the light with the CCD line image sensor 13, a predetermined density level is obtained, sensitivity variations of the CCD line image sensor 13 and uneven light distribution in the irradiation system are corrected, and digital processing such as γ correction is performed. The

  A signal necessary for driving the CCD line image sensor 13 and the signal processing integrated circuit device 28 is generated by a timing signal generation circuit 1630 based on an output signal of an oscillator (OSC) 29, and the CCD image sensor 13 and the signal processing are processed. Input to each circuit of the integrated circuit device 28.

  The timing signal generation circuit 1630 includes a PLL circuit 30a, divider / phase adjustment circuits 1630b, 1630c, 1630d, 1630e, 1630f, and a buffer 30p.

The output signal of the oscillator (OSC) 29 is multiplied by the PLL circuit 30a, and then the clocks φ1 and φ2 used for sampling the image light of the CCD line image sensor 13 and the divider / phase adjustment for forming the timing signal TG A circuit 1630b, a divider / phase adjustment circuit 1630c that forms a clock φ2L, CP used for signal output of the CCD line image sensor 13 and a reset signal RS, and a divider / phase adjustment circuit 1630d that forms a clamp signal CLP output to the clamp circuit 24 The divider / phase adjustment circuit 1630e for forming the sample hold pulse SHD output to the sample hold circuit (A / H) 25, and the divider / phase adjustment circuit for forming the conversion timing signal ADCLK output to the analog / digital conversion circuit 27. Is output to 1630F, each of the divider / phase adjustment circuit 1630b, 1630c, 1630d, 1630e, by 1630F, is divided appropriately, the timing signals required are formed.
Here, the clocks φ1 and φ2 are transfer clocks for transferring the signal charges obtained from the photodiode array in the CCD line image sensor 13 to the analog shift register and then transferring the charges on the analog shift register. The TG signal is a timing signal for transferring the charge accumulated in the photodiode during the exposure time to the analog shift register. The reset signal RS is provided in the CCD line image sensor 13, and the voltage of the floating capacitor provided in the source follower circuit for outputting the image signal to the outside of the CCD line image sensor 13 is initially set for each pixel of the image signal. This is a timing clock for returning to the state. The CP signal is a timing clock for determining an internal clamp timing for determining an offset voltage of the output waveform of the CCD line image sensor 13.

  The timing signal generation circuit 1630 is subjected to CCD drive timing and phase control by a CPU (Central Processing Unit) 1639.

  The sample hold circuit 25 has the circuit configuration shown in FIG. 17, and the sample hold pulse SHD input from the timing signal generation circuit 1630 is input to a switch element that turns on and off the signal to the capacitor that holds the sample value. As shown in FIG. 18, the sample starts (sample timing) at the falling edge of the sample hold pulse SHD, and ends the sample (hold timing) at the rising edge.

  This process needs to be performed during the CCD analog output image signal output period. That is, the hold timing in FIG. 18 needs to be surely within the image signal period, and the necessary sample period necessary for the operation of the circuit of FIG. 17 must also be within the image signal period.

  Usually, there is a relationship of “(sample period)> (required sample period)”, and the sample timing may be outside the image signal period as long as the necessary sample period is secured.

  With such a configuration of the sample and hold circuit 25, while the sample and hold pulse SHD is output from the timing signal generation circuit 1630 and input to the signal processing integrated circuit device 28, the output delay variation of the buffer 30p and the time constant of the transmission line are reduced. Hold timing may be lost due to variations. Also, the hold timing is shifted due to variations in the output delay of the timing signal buffer 30p for driving the CCD line image sensor 13, variations in the time constant of the transmission line, and variations in the signal output delay time of the CCD line image sensor 13 itself. End up.

JP 2000-307852 A

  When the signal delay variation as described above is accumulated, it becomes difficult to ensure proper hold timing including the variation and to guarantee the necessary sample period. Further, when the apparatus is driven at a high speed, the pixel frequency increases, so that the image signal period becomes narrow and it becomes difficult to guarantee the timing.

  If the hold timing is deviated from the CCD analog output image signal output period as shown in FIG. 19, the level to be followed by the sample hold circuit 25 is deviated from the original level, which is the deviation of the output of the apparatus. As a result, the image output by the image processing unit deteriorates. Further, when sample and hold is performed at a timing with respect to a signal portion whose signal level changes rapidly as shown in FIG. 19, the S / N of the image signal output of the apparatus is also deteriorated. It will deteriorate.

  The present invention has been made in view of the above, and prevents an operation timing of the sample and hold circuit from becoming an incorrect timing due to variations in signal delay or the like, and can output a high-quality image. An object is to provide an apparatus and method.

In order to solve the above-described problems and achieve the object, an image reading apparatus according to the present invention is an image reading apparatus that receives reflected light from an exposed document and generates a predetermined drive timing signal. An image sensor that outputs an image signal based on the reflected light by an input, a generation unit that generates a predetermined sample hold timing based on the driving timing signal, and the image signal for each of the plurality of sample hold timings The sampled image signal is sampled, an analog image signal is generated by holding the sampled image signal for a certain period of time, the generated analog image signal is output, and the analog image signal output from the sample hold circuit is quantized. A conversion unit for outputting a digitized digital image, and for each sample hold timing Based on said plurality of digital image signals output from the conversion unit, an adjustment unit for adjusting a phase of said sample-and-hold timing, an image processing unit for performing image processing on the digital image data, the sample hold timing For each delay step of the sample hold timing while changing the sample hold timing by each delay step by the delay unit within a range of effective pixels of the image sensor. A calculation unit that calculates an average value of the plurality of digital image signals, and the adjustment unit determines whether the average value is within a predetermined range for each delay step, and the average A delay step in which a value falls within a predetermined range and the average value are combined into a memory, and the average value Among the set of the delay step, the sample hold timing of the delay step of the center, by setting the optimum sample-and-hold timing, adjusts the phase of the sample-and-hold timing, the sample hold circuit, adjusts the phase The analog image signal is generated and output at the sampled and held timing.

The image reading method according to the present invention is an image reading method in which an image sensor receives reflected light from an exposed document and is based on the reflected light by inputting a predetermined driving timing signal. A step of outputting an image signal, a generation step of generating a predetermined sample hold timing based on the drive timing signal, and a sample hold circuit generating the image signal for each of the plurality of sample hold timings. A step of generating an analog image signal by sampling and holding the sampled image signal for a predetermined time, and outputting the generated analog image signal; and a conversion unit that outputs the analog image signal output from the sample hold circuit A step of outputting the quantized digital image, and an adjustment unit, the sample hold timing Based on said plurality of digital image signals output from the converting unit each time, and adjusting the phase of said sample-and-hold timing, a step of image processing unit performs image processing on the digital image data, A delay unit changing the sample hold timing within a range of effective pixels of the image sensor by a predetermined delay step; and a calculation unit, for each delay step of the sample hold timing, The step of calculating an average value of the image signal, and the adjustment unit determines whether the average value is within a predetermined range at each delay step, and the average value is within the predetermined range or Among the plurality of delay steps, the sample hold timing of the center delay step is set as the optimum sample hold timing. By constant, and adjusting the phase of said sample-and-hold timing, the sample hold circuit in the sample hold timing adjusted phase, to include a step of generating and outputting the analog image signal It is characterized by.

  According to the present invention, it is possible to prevent the operation timing of the sample and hold circuit from becoming an incorrect timing due to variations in signal delay or the like, and to output a high-quality image.

  Exemplary embodiments of an image reading apparatus and method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram illustrating an example of a configuration centering on a signal processing unit of the image reading apparatus according to the first embodiment. In this embodiment, the basic configuration of the reading optical system is the same as the conventional configuration shown in FIG. In FIG. 1, the same reference numerals are given to the same parts as those in FIG. 16 and corresponding parts.

  As shown in FIG. 1, the signal processing unit 42 of the image reading apparatus according to the first embodiment includes a CCD image sensor 13, a buffer circuit 22, a capacitor 23, a signal integrated circuit device 37, and an oscillator (OSC) 32. And a timing signal generating circuit 38 and a memory 40. In FIG. 1, in addition to the signal processing unit 42, a CPU 39 is also shown.

  In FIG. 1, an image signal is output from a CCD line image sensor 13 in synchronization with a drive pulse. This image signal is AC-coupled by a capacitor 23 via a buffer circuit 22 (emitter follower circuit) and input to a signal processing integrated circuit device (AFE) 37.

  As in FIG. 16, the signal processing integrated circuit device 37 includes a clamp circuit 33, a sample hold circuit (S / H) 34, an amplifier circuit (PGA) 35, and an analog / digital conversion circuit (ADC) 36 that are integrated and mounted. Circuit. The image signal input to the signal processing integrated circuit device 37 is first input to the clamp circuit 33. The clamp circuit 33 clamps the black offset level of the image signal to a predetermined potential at the input timing of the clamp signal CLP.

  The sample hold circuit (S / H) 34 samples the image signal output from the clamp circuit 33 at the input timing of the sample hold pulse SHD, and holds the sampled image signal for a certain period of time, thereby continuously analogizing the image signal. Output as an image signal. Thereafter, the amplification circuit (PGA) 35 amplifies the output of the analog image signal to a certain level, and then the analog / digital conversion circuit (ADC) 36 converts the amplified analog image signal at the input timing of the conversion timing signal ADCLK. For example, it is converted into a 10-bit digital image signal (image data). Here, the sample hold circuit 34 has the same configuration as the circuit configuration shown in FIG.

  The digital image signal thus obtained is transmitted to a subsequent image processing unit (not shown), and reflected from the white reference plate irradiated by the lamp 5 in a shading correction circuit (not shown) in the image processing unit. By reading the light with the CCD line image sensor 13, a predetermined density level is obtained, sensitivity variations of the CCD line image sensor 13 and uneven light distribution in the irradiation system are corrected, and digital processing such as γ correction is performed. The At the same time, the digital image signal is stored in the memory 40 for a certain number of pixels (for example, one line).

  A signal necessary for driving the CCD line image sensor 13 and the signal processing integrated circuit device 37 is generated by a timing signal generation circuit 38 based on an output signal of an oscillator (OSC) 32, and the CCD image sensor 13 and the signal processing are processed. Input to each circuit of the integrated circuit device 37. The CPU (central processing unit) 39 performs phase switching (phase adjustment) processing of the sample hold pulse SHD of the timing signal generation circuit 38 and refers to the digital image signal stored in the memory 40.

  The timing signal generation circuit 38 includes a PLL circuit 38a, divider / phase adjustment circuits 38b, 38c, 38d, 38e, 38g, and buffers 38f, 38p.

  In the timing signal generating circuit 38, the output signal of the oscillator 32 is multiplied by the PLL circuit 38a and then output to the divider / phase adjusting circuits 38b, 38c, 38d, and 38e. Each divider / phase adjustment circuit 38b, 38c, 38d, 38e divides the frequency appropriately to form a necessary timing signal.

  The divider / phase adjustment circuit 38b forms clocks φ1 and φ2 used for sampling image light of the CCD line image sensor 13 and a timing signal TG. The divider / phase adjustment circuit 38c forms a clock φ2L, CP and a reset signal RS used for signal output of the CCD line image sensor 13. The divider / phase adjustment circuit 38 d forms a clamp signal CLP output to the clamp circuit 24. Divider / phase adjustment circuit 38e forms conversion timing signal ADCLK to be output to analog / digital conversion circuit 27.

  The sample hold pulse SHD output to the sample hold circuit 34 is formed based on a reset signal RS that is a drive timing signal output to the CCD line image sensor 13. That is, as shown in FIG. 1, the reset signal RS formed by the divider / phase adjustment circuit 38c is input to the CCD image sensor and returned to the timing signal generation circuit 38, and the divider / phase is output via the buffer 38f. It is input to the adjustment circuit 38g. Then, as shown in FIG. 2, the divider / phase adjustment circuit 38g generates the sample hold pulse SHD with a fixed delay from the phase of the rising edge of the reset signal RS. The divider / phase adjustment circuit 38g that generates the sample hold pulse SHD performs, for example, a phase comparison between the external clock (reset signal RS) in the PLL circuit 38a and the internal clock generated based on the edge of the external clock. A circuit that varies the value of the external clock and matches (locks) the phase of the external clock and the internal clock can generate a clock having a desired delay amount based on the external clock (not shown). With this method, even if the phase comparison is missed due to noise or the like, the delay value is only slightly moved and is stable.

  Now, as shown in FIG. 2, reset noise occurs in the CCD analog image signal after the image signal period. Since the reset noise is generated with a slight delay from the timing phase of the reset signal RS input to the CCD line image sensor 13, the phase adjustment is performed so that the hold timing of the sample hold pulse SHD is always before the rising edge of the reset signal RS. If this is done, the hold timing will always come during the image signal period of the CCD line image sensor 13. Thus, even if it is not optimal, the timing can be used as the initial timing for adjusting the sample hold timing (the timing of “0” in FIG. 2). Here, the timing of the sample hold pulse SHD formed by the sample timing and the hold timing is referred to as a sample hold timing.

  At the time of adjustment, the CPU 39 changes the delay step of the divider / phase adjustment circuit 38g from this initial timing. At this time, the delay step is not changed every period of the main scanning line, but as shown in FIG. 3 and FIG. 4A to FIG. It is changed (the initial timing is maintained except for the effective pixel period). In this state, in each delay step, a plurality of digital image signals (hereinafter referred to as “image signal data”) output from the analog / digital conversion circuit (ADC) 36, for example, 64 image signal data are stored in the memory 40. To store. For the image signal data stored in the memory 40, the CPU 39 calculates an average value of a plurality of image signal data for each delay step. Note that the number of image signal data for obtaining the average value may be plural, and is not limited to 64.

  When the average value at each step is plotted, for example, a graph as shown in FIG. 5 is obtained. FIG. 5 is a graph showing the relationship between each delay step and the average value of a plurality of image signal data at each delay step. Here, assuming that the expected value of the average value is 40 LSB ± 2LSB with 10 bits (here, LSB is a quantization unit corresponding to one digital unit), when the delay step becomes larger than “0”, the hold Timing is affected by reset noise, and the level deviates from the expected value. Conversely, when the delay step is smaller than “0”, the hold timing is in the image signal period, but the required sample width cannot be secured, and the level deviates from the expected value. For this reason, the CPU 39 stores the average value within the range of the expected value in the memory 40 in combination with the delay step at that time.

  In this example, the average value for the delay step “−2, −1, 0” satisfies the expected value. For this reason, the CPU 39 acquires the delay step “−2, −1, 0” stored in the memory 40 in combination with the average value that satisfies the expected value. Then, the CPU 39 adopts the center delay step “−1” as a final appropriate sample hold timing in consideration of the timing margin.

  If the expected value is not obtained due to the delay of the initial timing: delay step “0”, the initial timing is shifted to “+1” or “−1” to search for the initial timing.

  Next, in the image reading apparatus of the present embodiment configured as described above, a sample hold timing setting process executed by the CPU 39 when adjusting the delay step will be described. FIG. 6 is a flowchart illustrating the procedure of the sample hold timing setting process according to the first embodiment.

  First, the CPU 39 sets the initialization timing as delay step = 0 (step S11). A plurality (64 in this example) of image signal data output from the analog / digital conversion circuit (ADC) 36 at one hold sample timing is stored in the memory 40 (step S12). The CPU 39 reads the 64 image signal data stored in the memory 40, calculates the average value of the read 64 image signal data (step S13), and the calculated average value is within the above expected value range. It is checked whether it is within (40LSB ± 2LSB) (step S14).

  When the average value is within the expected value range (step S14: Yes), the CPU 39 stores the average value in combination with the current delay step in the memory 40 (step S15). When it is outside the range of the expected value (step S14: No), the storage in the memory 40 is not performed.

  Then, the CPU 39 checks whether or not the processing from steps S12 to S15 has been completed for all delay steps (step S16). If the processing has not been completed (step S16: No), the delay step is performed. 1 is added or 1 is subtracted (step S17), and the processing from steps S12 to S15 is repeatedly executed.

  On the other hand, when the processing from step S12 to S15 is completed for all delay steps in step S16 (step S16: Yes), the timing of the center delay step among the delay steps stored in the memory 40 is The sample hold timing is set (step S18). The image signal is output as an analog image signal from the sample and hold circuit (S / H) 34 at an appropriate sample and hold timing set in this manner, whereby the image processing unit performs image processing of the image data.

  As described above, in the image reading apparatus according to the first embodiment, in order to prevent the sample hold from having an incorrect timing due to individual variations in the signal delay of the signals that drive the CCD line image sensor 13 and the signal processing integrated circuit device 37, It can be adjusted so that the sample hold timing is optimal at the time of power-on of the apparatus or at the time of factory shipment. For this reason, it is possible to prevent the operation timing of the sample hold circuit 34 from becoming an incorrect timing due to variations in signal delay or the like, and to output a high-quality image.

  In the first embodiment, the sample hold timing is adjusted to obtain the average value of the image signal data at each timing, and it is determined whether or not the value is within the range of a desired expected value. Since the delay step timing within the expected value range is set as the sample hold timing, a more appropriate sample hold timing can be obtained and a high quality image can be output.

  Further, in order to perform each correction correctly, it is necessary that the initial timing (sample hold timing) before the correction takes some CCD analog output period even if it is not optimal. For this reason, in the first embodiment, the drive signal (reset signal RS) input to the line image sensor 13 is fed back to the timing signal generation circuit, and the sample hold timing is generated based on that signal. The signal delay variation on the image sensor 13 side can be absorbed, and it can be used as the initial timing to obtain a more appropriate sample hold timing.

  In the first embodiment, since the sample hold timing is switched a plurality of times within one line period and the sample hold timing is switched, the detection of the waveform data (average value, etc.) can be completed in a short time.

(Embodiment 2)
Next, a second embodiment will be described. The configuration of the signal processing unit 42 of the second embodiment is the same as that of the first embodiment.

  The CPU 39 according to the second embodiment obtains an average value of a plurality of image signal data in each delay step as in the first embodiment. Then, the CPU 39 sets the timing of the delay step that minimizes the difference between the average values of the adjacent delay steps as the appropriate sample hold timing. Here, since there are two delay steps adjacent to the delay step to be processed, the delay step earlier in time and the delay step later in time, the CPU 39 determines that the sum of the two differences is minimum. The delay step to be processed is set as an appropriate sample hold timing. Thereby, a stable sample hold timing can be obtained.

  FIG. 8A is a graph illustrating the relationship between each delay step and the sum of differences between the average value of the plurality of image signal data at each delay step and the average value at the adjacent delay step. When the graph as illustrated in FIG. 8A is obtained, the CPU 39 sets the timing of the delay step “−1” as an appropriate sample hold timing.

  Next, in the image reading apparatus of the present embodiment configured as described above, a sample hold timing setting process executed by the CPU 39 when adjusting the delay step will be described. FIG. 7 is a flowchart showing the procedure of the sample hold timing setting process according to the second embodiment.

  First, similarly to the first embodiment, the CPU 39 sets the initialization timing as delay step = 0 (step S21), and outputs a plurality of outputs from the analog / digital conversion circuit (ADC) 36 at one hold sample timing. The number (in this example, 64) of image signal data is stored in the memory 40 (step S22), and an average value of the 64 pieces of image signal data stored in the memory 40 is calculated (step S23). Then, the CPU 39 sets the average value in combination with the current delay step and stores it in the memory 40 (step S24).

  Then, the CPU 39 checks whether or not the processing from steps S22 to S24 has been completed for all delay steps (step S25). If the processing has not been completed (step S25: No), the delay step is performed. 1 is added or 1 is subtracted (step S26), and the processing from steps S22 to S24 is repeatedly executed.

  On the other hand, in step S25, when the processing from step S22 to S24 is completed for all the delay steps (step S25: Yes), the CPU 39 refers to the memory 40 and sets the average value of all the delay steps. On the other hand, the difference from the average value in the delay steps on both sides (first and later in time) is calculated, and the two differences in each delay step are added (step S27).

  Then, the CPU 39 sets the delay step timing at which the added value is minimum as the sample hold timing (step S28). The image signal is output as an analog image signal from the sample and hold circuit (S / H) 34 at an appropriate sample and hold timing set in this manner, whereby the image processing unit performs image processing of the image data.

  As described above, in the image reading apparatus according to the second embodiment, the sample hold timing is adjusted, the average value of the image signal data at each timing is obtained, and the sum of the differences, which is the amount of change at each timing, is calculated. . Then, it is determined that the point where the sum of differences as the amount of change is out of the CCD analog image signal period, and the timing of the delay step at which the sum of the differences is minimum is set as the sample hold timing. In addition to the above effect, more appropriate sample hold timing can be obtained, and a high-quality image can be output.

(Embodiment 3)
Next, Embodiment 3 will be described. The configuration of the signal processing unit 42 of the third embodiment is the same as that of the first embodiment.

  The CPU 39 according to the third embodiment obtains a standard deviation of the plurality of image signal data in order to examine the variation of the plurality of image signal data in each delay step. The CPU 39 sets the delay step timing at which the standard deviation is equal to or smaller than a predetermined threshold as an appropriate sample hold timing. This is because a delay step with little variation in image signal data and stable is used as the sample hold timing. In the present embodiment, the CPU 39 sets the delay step timing at which the standard deviation is minimum as the standard deviation to be equal to or smaller than the predetermined threshold, that is, the delay step timing at which the variation in the image signal data is minimum as the appropriate sample hold timing. It is set. Note that the present invention is not limited to this, and any delay step in which the standard deviation is equal to or smaller than a predetermined threshold value can be set as an appropriate sample hold timing.

  FIG. 8-2 is a graph showing the relationship between each delay step and the standard deviation of a plurality of image signal data at each delay step. When the graph as illustrated in FIG. 8B is obtained, the CPU 39 sets the timing of the delay step “−1” as an appropriate sample hold timing.

  Next, in the image reading apparatus of the present embodiment configured as described above, a sample hold timing setting process executed by the CPU 39 when adjusting the delay step will be described. FIG. 9 is a flowchart illustrating the procedure of the sample hold timing setting process according to the third embodiment.

  First, as in the first embodiment, the CPU 39 sets the initialization timing as delay step = 0 (step S31), and outputs a plurality of signals output from the analog / digital conversion circuit (ADC) 36 at one hold sample timing. (In this example, 64) image signal data is stored in the memory 40 (step S32).

  Next, the CPU 39 calculates the standard deviation of the 64 image signal data stored in the memory 40 (step S33). Then, the CPU 39 stores the calculated standard deviation in combination with the current delay step in the memory 40 (step S34).

  Then, the CPU 39 checks whether or not the processing from steps S32 to S34 has been completed for all delay steps (step S35). If the processing has not been completed (step S35: No), the delay step is performed. 1 is added or 1 is subtracted (step S36), and the processing from steps S32 to S34 is repeatedly executed.

  On the other hand, in step S35, when the processing from step S32 to S34 is completed for all the delay steps (step S35: Yes), the CPU 39 refers to the memory 40 and the delay step that minimizes the standard deviation. Is set as the sample hold timing (step S37). The image signal is output as an analog image signal from the sample and hold circuit (S / H) 34 at an appropriate sample and hold timing set in this manner, whereby the image processing unit performs image processing of the image data.

  As described above, in the image reading apparatus according to the third embodiment, the sample hold timing is adjusted to obtain the variation amount (standard deviation) of the image signal data at each timing. Waveform changes become steep at locations outside the CCD analog image signal period, so it is determined whether the value falls within the desired value range, and the timing of the delay step that minimizes the standard deviation is sampled and held. Since the timing is set, in addition to the effects of the first embodiment, a more appropriate sample hold timing can be obtained, and a high-quality image can be output.

(Embodiment 4)
Next, a fourth embodiment will be described. FIG. 10 is a circuit diagram illustrating an example of a configuration centering on a signal processing unit of the image reading apparatus according to the first embodiment. In this embodiment, the basic configuration of the reading optical system is the same as the conventional configuration shown in FIG. In FIG. 10, the same parts as those in the first embodiment and corresponding parts are denoted by the same reference numerals.

  In the fourth embodiment, the sample hold pulse SHD applied to the sample hold circuit 34 is formed by dividing and phase adjusting by the divider / phase adjustment circuit 38g based on the output of the PLL circuit 38a.

  That is, in the fourth embodiment, the sample-and-hold pulse SHD is divided so that the output of the oscillator 32 is multiplied by the PLL circuit 38a and the desired frequency is obtained by the divider / phase adjustment 38h, similarly to the other timing clocks. It is obtained by going around. Here, the phase of the sample hold pulse SHD can be shifted at a certain interval by the phase adjustment mechanism of the divider / phase adjustment circuit 38g. However, phase adjustment in fine steps as in the first to third embodiments cannot be performed.

  In the fourth embodiment, the following factors are raised as the variation factors causing the deviation of the sample hold timing.

  That is, the position of the image signal period of the CCD analog output varies depending on the buffer delay variation between the timing signal generating circuit 38 and the CCD line image sensor 13, the transmission path time constant variation, and the output delay time variation of the CCD line image sensor 13. . Further, the phase of the sample hold pulse SHD varies depending on the delay variation of the buffer between the timing signal generation circuit 38 and the signal processing integrated circuit device 37 and the time constant variation of the transmission path.

  When these variations are accumulated, the range that can be taken as the initial timing is, for example, the shaded portion in FIG. 11, and the performance including the variation cannot be guaranteed as the initial timing.

  Therefore, the sample hold timing is adjusted when the power is turned on or when the process is shipped. First, the frequency (operating frequency) for driving the line image sensor 13 and the signal processing integrated circuit device 37 is used. In this case, the CPU 39 changes the pixel frequency to 1 / n slower than the PLL circuit 38a, for example, to 1/2. Since the timing variation factor is constant regardless of the frequency, in this state, as shown in FIG. 12, the timing is guaranteed in the initial state.

  In this state, the CPU 39 sets the sample hold timing at which the average value is most stable by the same method as in the second embodiment. Thereafter, by multiplying the frequency by n and returning to the actual image reading state, the optimum sample hold timing can be obtained.

  Next, an image reading process in the image reading apparatus of the present embodiment configured as described above will be described. FIG. 13 is a flowchart illustrating a procedure of image reading processing according to the fourth embodiment.

  First, the CPU 39 sends an instruction to the PLL circuit 38a to set the pixel frequency to 1 / n of the image frequency at the time of image reading. Upon receiving this instruction, the PLL circuit 38a sets the image frequency to the image at the time of image reading. The frequency is divided to 1 / n of the frequency (step S41). Then, for example, the sample hold timing setting process described in the first embodiment is executed (step S42). Then, the CPU 39 sends an instruction for returning the pixel frequency to the image frequency at the time of image reading to the PLL circuit 38a. Upon receiving this instruction, the PLL circuit 38a returns the image frequency to the image frequency at the time of image reading ( Then, image processing is performed by the image processing unit on the image signal data converted from the read analog image signal (step S44).

  In order to accurately adjust the sample and hold timing, it is necessary that the initial timing (sample and hold timing) before the correction takes some CCD analog output period even if it is not optimal. The signal delay variation of the CCD output and the sample hold timing is a fixed delay that does not depend on the driving frequency of the apparatus. For this reason, in the image reading apparatus of the fourth embodiment, the image frequency (operating frequency) of the image reading apparatus is once slowed when the hold timing is adjusted. As a result, the range in which an appropriate sample and hold operation can be performed at the initial timing can be expanded. Moreover, in this Embodiment, the effect of Embodiment 1 is also show | played.

(Embodiment 5)
Next, a fifth embodiment will be described. FIG. 14 is a circuit diagram showing an example of a configuration centering on the signal processing unit of the fifth embodiment. The present embodiment includes an integrated circuit device LL in which the configuration of the signal processing integrated circuit device of the first to fourth embodiments, the timing signal generation circuit 38, and the memory 40 are integrated into one package.

  In this case, an ON signal for starting the sample hold timing adjustment is received from the CPU 39, and the sample control timing setting process as described in the second embodiment is executed by hardware in the logic control unit 38k in the integrated circuit device LL. . That is, the sample hold timing setting process is not performed by software execution by the CPU 39.

  As described above, in the image reading apparatus according to the fifth embodiment, the configuration of the signal processing integrated circuit device according to the first to fourth embodiments, the timing signal generation circuit 38, and the memory 40 are integrated into one package. Since the LL is provided, sample hold timing generation, timing adjustment, waveform data detection, and optimum sample hold timing detection can all be performed within the integrated circuit device LL. For this reason, according to the present embodiment, in addition to the effects of the first embodiment, the sample hold timing can be adjusted with a simple configuration without the control by the complicated software processing by the CPU 39.

  It should be noted that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

FIG. 3 is a circuit diagram illustrating an example of a configuration centering on a signal processing unit of the image reading apparatus according to the first embodiment; It is a wave form chart for explaining generation of sample hold pulse SHD. It is explanatory drawing which shows the time chart of a line clamp signal, the sample hold pulse SHD, and CCD output. It is a wave form diagram for demonstrating the change mode (delay step = -3) at the time of changing a delay step. It is a wave form diagram for demonstrating the change mode (delay step = -2) at the time of changing a delay step. It is a wave form diagram for demonstrating the change mode (delay step = -1) at the time of changing a delay step. It is a wave form diagram for demonstrating the change mode (delay step = 0) at the time of changing a delay step. It is a wave form diagram for demonstrating the change mode (delay step = + 1) at the time of changing a delay step. It is a wave form diagram for demonstrating the change mode (delay step = + 2) at the time of changing a delay step. It is a graph which shows the relationship between each delay step and the average value of several image signal data in each delay step. 6 is a flowchart illustrating a procedure of a sample hold timing setting process according to the first embodiment. 10 is a flowchart illustrating a procedure of sample hold timing setting processing according to the second embodiment. It is a graph which shows the relationship between each delay step and the sum of the difference of the average value of the several image signal data in each delay step, and the average value in an adjacent delay step. It is a graph which shows the standard deviation of several image signal data in each delay step and each delay step, and a relationship. 10 is a flowchart illustrating a procedure of sample hold timing setting processing according to the third embodiment. FIG. 3 is a circuit diagram illustrating an example of a configuration centering on a signal processing unit of the image reading apparatus according to the first embodiment; It is a wave form chart for explaining initial timing. It is a wave form diagram for demonstrating the timing at the time of delaying a pixel frequency to 1/2. 15 is a flowchart illustrating a procedure of image reading processing according to the fourth embodiment. FIG. 10 is a circuit diagram illustrating an example of a configuration centering on a signal processing unit according to a fifth embodiment. 1 is a schematic configuration diagram illustrating a configuration example of an optical system of an image reading apparatus. It is the block diagram which showed the prior art example of the conventional signal processing part. It is the block diagram which showed an example of the sample hold circuit. It is a wave form diagram showing an example of sample timing-hold timing. It is a wave form diagram for demonstrating the malfunction of a sample timing-hold timing.

Explanation of symbols

2 Contact Glass 3 Reading Document 4 White Reference Plate 6 First Mirror 9 First Carriage 10 Second Carriage 11 Lens 22 Capacitor 22 Buffer Circuit 24 Clamp Circuit 25 Sample Hold Circuit 27 Analog / Digital Conversion Circuit 28, 37 Signal Processing Integrated Circuit Device 38 Timing signal generation circuit 38b, 38c, 38d, 38e, 38f, 38g, 1630b, 1630c, 1630d, 1630e, 1630f Divider / phase adjustment circuit 30p, 38p Buffer circuit 39 CPU
40 memory

Claims (7)

An image reading device,
An image sensor that receives reflected light from an exposed document and outputs an image signal based on the reflected light by inputting a predetermined driving timing signal;
A generating unit that generates a predetermined sample-hold timing based on the driving timing signal;
A sample and hold circuit that samples the image signal for each of a plurality of the sample and hold timings, generates an analog image signal by holding the sampled image signal for a predetermined time, and outputs the generated analog image signal;
A conversion unit that outputs a digital image obtained by quantizing the analog image signal output from the sample and hold circuit;
An adjustment unit that adjusts the phase of the sample hold timing based on the plurality of digital image signals output from the conversion unit for each sample hold timing;
An image processing unit that performs image processing on the digital image data;
A delay unit that changes the sample hold timing by a predetermined delay step within a range of effective pixels of the image sensor;
A calculation unit that calculates an average value of the plurality of digital image signals for each delay step of the sample hold timing while changing the sample hold timing by the delay step by the delay unit ;
The adjustment unit determines whether or not the average value falls within a predetermined range for each delay step, and sets the delay step and the average value within which the average value falls within the predetermined range to form a memory. In the set of the average value and the delay step, the phase of the sample and hold timing is adjusted by setting the sample and hold timing of the center delay step as the optimum sample and hold timing,
The sample and hold circuit generates and outputs the analog image signal at the sample and hold timing adjusted in phase;
An image reading apparatus. An image reading device,
An image sensor that receives reflected light from an exposed document and outputs an image signal based on the reflected light by inputting a predetermined driving timing signal;
A generating unit that generates a predetermined sample-hold timing based on the driving timing signal;
A sample and hold circuit that samples the image signal for each of a plurality of the sample and hold timings, generates an analog image signal by holding the sampled image signal for a predetermined time, and outputs the generated analog image signal;
A conversion unit that outputs a digital image obtained by quantizing the analog image signal output from the sample and hold circuit;
An adjustment unit that adjusts the phase of the sample hold timing based on the plurality of digital image signals output from the conversion unit for each sample hold timing;
An image processing unit that performs image processing on the digital image data;
A delay unit that changes the sample hold timing by a predetermined delay step within a range of effective pixels of the image sensor;
An average value of the plurality of digital image signals is calculated for each delay step of the sample hold timing while changing the sample hold timing by the delay step by the delay unit , and the average at the adjacent sample hold timing is calculated. A calculation unit that calculates a difference with a value and stores the calculated difference and the delay step in a memory as a set ,
The adjustment unit sets the sample hold timing of the delay step that minimizes the difference from the set of the difference and the delay step as an optimum sample hold timing, thereby setting the sample hold timing. Adjust the phase ,
The sample and hold circuit generates and outputs the analog image signal at the sample and hold timing adjusted in phase;
An image reading apparatus. An image reading device,
An image sensor that receives reflected light from an exposed document and outputs an image signal based on the reflected light by inputting a predetermined driving timing signal;
A generating unit that generates a predetermined sample-hold timing based on the driving timing signal;
A sample and hold circuit that samples the image signal for each of a plurality of the sample and hold timings, generates an analog image signal by holding the sampled image signal for a predetermined time, and outputs the generated analog image signal;
A conversion unit that outputs a digital image obtained by quantizing the analog image signal output from the sample and hold circuit;
An adjustment unit that adjusts the phase of the sample hold timing based on the plurality of digital image signals output from the conversion unit for each sample hold timing;
An image processing unit that performs image processing on the digital image data;
A delay unit that changes the sample hold timing by a predetermined delay step within a range of effective pixels of the image sensor;
While changing the sample hold timing by the delay step by the delay unit, the standard deviation of the plurality of digital image signals is calculated for each delay step of the sample hold timing , and the calculated standard deviation and the delay step are calculated. Is further provided with a calculation unit for storing in a memory
The adjustment unit sets the sample hold timing of the delay step where the standard deviation is equal to or less than a predetermined value from the set of the standard deviation and the delay step, and sets the sample hold timing as an optimal sample hold timing, Adjust the phase of sample hold timing ,
The sample and hold circuit generates and outputs the analog image signal at the sample and hold timing adjusted in phase;
An image reading apparatus. The adjustment unit adjusts a phase of the subsequent sample hold timing with respect to the initial timing, with the sample hold timing generated first based on the driving timing signal as an initial timing. The image reading apparatus according to any one of ? During adjustment of the sample-and-hold timing of the phase, before the sample-and-hold circuit and the operating frequency of the converter unit and the hearing Mejisensa, further comprising a control unit for controlling slower than the operating frequency at the time of image reading other than the adjustment of the phase the image reading apparatus according to any one of claims 1-3, characterized in that the. The image according to any one of claims 1 to 3, wherein the adjustment unit adjusts a phase of the sample hold timing based on the digital image signal converted from an analog image signal in a dark state. Reader. An image reading method comprising:
An image sensor that receives reflected light from an exposed document and outputs an image signal based on the reflected light by inputting a predetermined driving timing signal;
A generating step for generating a predetermined sample hold timing based on the driving timing signal;
A sample and hold circuit that samples the image signal for each of a plurality of the sample and hold timings, holds the sampled image signal for a predetermined time, generates an analog image signal, and outputs the generated analog image signal; ,
A step of outputting a digital image obtained by quantizing the analog image signal output from the sample hold circuit;
Adjusting the phase of the sample hold timing based on the plurality of digital image signals output from the conversion unit at each sample hold timing; and
An image processing unit performing image processing on the digital image data;
A delay unit changing the sample hold timing by a predetermined delay step within a range of effective pixels of the image sensor; and
A step of calculating an average value of the plurality of digital image signals for each of the delay steps of the sample and hold timing while the calculation unit changes the sample and hold timing by the delay step by the delay unit;
The adjusting unit determines whether or not the average value is within a predetermined range for each delay step, and sets the delay step and the average value within which the average value is within a predetermined range as a memory. Adjusting the phase of the sample and hold timing by setting the sample and hold timing of the center delay step as the optimum sample and hold timing in the set of the average value and the delay step;
The sample-and-hold circuit, in the sample hold timing adjusted phase, the step of generating and outputting the analog image signal,
An image reading method comprising:

Images