JP5014530B2 - Capacitor parts - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to electronic devices, and more particularly to an electronic device in which a semiconductor integrated circuit device is mounted on a substrate.
[0002]
A semiconductor integrated circuit device such as an LSI chip is generally mounted on a wiring board to constitute an electronic device. In such an electronic device, an external component such as a fluctuation in power supply voltage to the LSI chip via a power supply line to the LSI chip is used. In order to cut off the transmission of noise, and also to block the internal noise of the LSI chip caused by a sudden change in load impedance caused by high-speed LSI operation, for example, the transmission of high-frequency ripple to the wiring board via the feeder line For this reason, a decoupling capacitor is provided in the power supply line to bypass the noise component.
[0003]
[Prior art]
FIG. 1 shows a configuration of a conventional electronic device 10 having a decoupling capacitor.
[0004]
Referring to FIG. 1, the electronic device 10 has an LSI chip 12 mounted on a wiring board 11, and a decoupling capacitor 13 is disposed on the wiring board 11 so as to surround the LSI chip 12. ing. In the electronic device having such a configuration, by providing the decoupling capacitor 13, it is possible to avoid malfunction of the LSI chip or other elements mounted on the wiring substrate 11 due to the noise described above.
[0005]
On the other hand, in the configuration of FIG. 1, it is necessary to form a wiring pattern having a substantial length on the wiring board 11 in order to connect the LSI 12 and the decoupling capacitor 13. It becomes difficult to achieve desired suppression of power supply voltage fluctuations and absorption of high-frequency ripples. This problem becomes prominent particularly in an electronic device having an LSI chip that operates at a high speed, for example, at a clock frequency in the GHz band.
[0006]
In order to avoid such problems of the conventional decoupling capacitor 13 of FIG. 1, a configuration in which the decoupling capacitor 13 is formed in the wiring board 11 corresponding to the mounting position of the LSI chip 12 as shown in FIG. Proposed. See JP-A-7-37758.
[0007]
However, in the conventional configuration shown in FIG. 2, the degree of design freedom of the electronic device is reduced due to the decoupling capacitor 13 being built in the wiring substrate 11, and the electronic circuit formed on the wiring substrate 11 is reduced. There arises a problem that the design is restricted by the wiring substrate 11 used. Alternatively, it is necessary to specially order wiring boards having different capacitor positions for each electronic circuit. In any case, such a reduction in design freedom increases the cost of the electronic device being manufactured. In addition, if the decoupling capacitor 13 is formed in the wiring board 11, the manufacturing cost of the wiring board 11 increases.
[0008]
On the other hand, FIG. 3 shows an electronic device 20 according to the related art in which an interposer type capacitor component 14 including the decoupling capacitor 13 is inserted between the wiring board 11 and the LSI chip 12.
[0009]
Referring to FIG. 3, the capacitor component 14 is flip-chip mounted on the wiring substrate 11, and the LSI chip 12 is flip-chip mounted on the capacitor component 14. According to such a configuration, it is considered that the distance between the LSI chip 12 and the wiring substrate 11 is shortened, and the problem of functional degradation of the decoupling capacitor 13 due to the wiring inductance described above is solved.
[0010]
FIG. 4 shows a configuration according to a possible example of the capacitor component 14 of FIG.
[0011]
Referring to FIG. 4, the capacitor component 14 includes a lower electrode layer 14A, an upper electrode layer 14B, and a high dielectric capacitor insulating film 14C sandwiched between the lower electrode layer 14A and the upper electrode layer 14B. The lower electrode layer 14A, the upper electrode layer 14B, and the capacitor insulating film 14C constitute a decoupling capacitor 13 built in the capacitor component 14.
[0012]
As shown in FIG. 4, from the lower electrode layer 14A, a contact electrode 14a extends upward through a contact hole formed in the capacitor insulating film 14C and the upper electrode layer 14B, and the upper electrode 14B Also, the corresponding contact electrode 14b extends upward. The contact electrodes 14a and 14b are adapted to contact an electrode pad constituting a power supply terminal or a ground terminal of the LSI chip 12. Therefore, by flip-chip mounting the LSI chip 12 on the capacitor component 14, the decoupling capacitor 13 is inserted between the power supply terminal and the ground terminal of the LSI chip 12. A large number of via holes are formed in the capacitor component 14 to hold conductor plugs that connect electrode pads on the LSI chip 12 to corresponding wiring patterns on the wiring board 11.
[0013]
[Problems to be solved by the invention]
By the way, in the capacitor component 14, the above-described inductance problem can be avoided by forming the electrode layers 14A and 14B and the high dielectric film 14C by a thin film formation process. Since the electrode layers 14A and 14B are thin, it is unavoidable that the sheet resistance increases as shown in FIG. The electrode layers 14A and 14B formed by such a thin film forming process are made of a very thin conductive film of about 50 to 300 nm. When the high dielectric film 14C is formed by a firing process of a green sheet used in normal ceramic capacitor manufacturing, the pitch of the via holes is at least 100 to 200 μm, and the pitch of the electrode pads on the LSI chip. Will be bigger than. In other words, in such a capacitor component 14, the high dielectric film 14C and the electrode layers 14A and 14B must be formed by a thin film formation process.
[0014]
5A shows an equivalent circuit diagram of the capacitor component 14 of FIG. 4, and FIG. 5B shows frequency characteristics of the circuit of FIG. 5A.
[0015]
Referring to FIG. 5A, the capacitor component 14 has a configuration in which an equivalent series resistance ESR and an equivalent series inductance ESL are connected in series to a capacitor C. As shown in FIG. 5B, at the resonance frequency fc1. The frequency characteristic has a minimum impedance magnitude | Z |. In FIG. 5B, the vertical axis represents the impedance absolute value | Z | expressed in a logarithmic scale, and the horizontal axis represents the frequency expressed in a logarithmic scale.
[0016]
In the frequency characteristic of FIG. 5B, the contribution of the capacitor C in the equivalent circuit of FIG. 5A to the impedance Z is large in the frequency band lower than the resonance frequency fc1, while the frequency higher than the resonance frequency fc1. In the band, the contribution of the equivalent series inductance ESL to the impedance Z is large. Therefore, if the value of the equivalent series resistance ESR is small, the value of the equivalent series inductance ESL is decreased from ESL1 to ESL2, ESL3, thereby shifting the resonance frequency fc1 to a higher resonance frequency fc2, and the operation of the decoupling capacitor. Can follow the high-speed operation of the LSI chip 12.
[0017]
However, as described above with reference to FIG. 4, if the electrode layers 14A and 14B have a large sheet resistance, the value of the equivalent series resistance ESR in the equivalent circuit of FIG. )), Even if the value of the equivalent series inductance ESL is decreased, the impedance | Z | does not decrease correspondingly, and as a result, a desired resonance frequency cannot be realized.
[0018]
Accordingly, it is a general object of the present invention to provide a new and useful capacitor component that solves the above-described problems, and an electronic device having such a capacitor component.
[0019]
A more specific object of the present invention is to provide a capacitor component having a decoupling capacitor that reduces the equivalent series resistance and operates efficiently even in the ultra-high frequency band of GHz band, and an electronic device having such a capacitor component. It is in.
[0020]
[Means for Solving the Problems]
The present invention solves the above problems. A substrate having a plurality of through holes penetrating from the first side to the second side; a plurality of conductive plugs filling the plurality of through holes; and the plurality of conductive layers on the first side of the substrate. A plurality of contact electrode pads formed corresponding to the conductive plugs, and a first electrode layer, a high dielectric capacitor insulating film, and a second electrode layer formed on the second side of the substrate in sequence. The stacked high dielectric capacitor, the insulating film covering the high dielectric capacitor on the second side of the substrate, and the high dielectric capacitor and the insulating film are respectively corresponding to the plurality of through holes. A plurality of openings extending and exposing the corresponding conductive plug, and a corresponding conductive plug of the plurality of conductive plugs on the insulating film corresponding to the plurality of openings, respectively. To In the capacitor component having a plurality of contact electrode structures provided in a connected manner, the plurality of through holes include a first through hole and a second through hole. In the first through hole, A contact electrode structure is connected to the first electrode layer, and in the second through hole, the contact electrode structure is connected to the second electrode layer, and the contact electrode structure is connected to the second side of the substrate. The first electrode pattern is formed on the insulating film covering the high dielectric capacitor via a plurality of first conductor plugs provided so as to penetrate the insulating film covering the high dielectric capacitor. The second electrode pattern is formed on the second side of the substrate via a plurality of second conductor plugs, and is electrically connected to the electrode layer at a plurality of locations. The second electrode layer is formed in a state of being electrically connected at a plurality of locations, and the plurality of through holes extend from the first side to the second side in the substrate. A plurality of contact electrode structures corresponding to the third through holes; and the plurality of contact electrode pads corresponding to the third through holes. A capacitor component including a third contact electrode pad, wherein the third contact electrode structure does not contact any of the first and second electrode layers of the high dielectric capacitor. To solve.
[Action]
FIG. 6 illustrates the principle of the present invention. However, in FIG. 6, the same reference numerals are assigned to portions corresponding to the portions described above, and the description thereof is omitted.
[0021]
Referring to FIG. 6, in the present invention, the contact electrode 14a is contacted with the lower electrode 14A by a conductor plug at a plurality of locations, and the contact electrode 14b is contacted with the upper electrode 14B by a conductor plug at a plurality of locations. The At this time, a contact hole 13C exposing the lower electrode 14A is formed in each contact electrode 14a in the upper electrode 14B and the high dielectric capacitor insulating film 14C for the conductor plug extending from the contact electrode 14a. Correspondingly formed. A through hole 13T is formed in the capacitor 13 for passing a signal line.
[0022]
According to the configuration of FIG. 6, a plurality of locations of the capacitor lower electrode 14A are commonly connected to the contact electrode 14a, and a plurality of locations of the capacitor upper electrode 14B are commonly connected to the contact electrode 14b. Even if the sheet resistances of the upper and lower electrodes 14A and 14B are large, the equivalent series resistance ESR shown in FIG. 5A is small. Therefore, the capacitor component can follow the operation of the LSI in the GHz band by reducing the equivalent inductance ESL. The noise component can be effectively removed from the power supply line or the ground line.
[0023]
Although FIG. 6 shows that the contact electrodes 14a and 14b are formed at the same level, the contact electrodes 14a and 14b may be formed at different levels.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
[First embodiment]
Hereinafter, the configuration and structure of the capacitor component 30 according to the first embodiment of the present invention will be described in order with reference to FIG. 7A to FIG.
[0025]
Referring to FIG. 7A, typically, through holes 31a to 31c having a diameter of, for example, 60 μm are formed in a CF substrate in a Si substrate 31 having a thickness of 0.3 mm. _Four Typically, the through holes 31a to 31c are filled by a CVD process of refractory metal such as Pt, Au, or W by a dry etching process using an etching gas as a conductive plug. 31A to 31C are formed.
[0026]
Next, in the step of FIG. 7B, the upper and lower main surfaces of the Si substrate 31 are made of SiO. ₂ Films 32 and 33 are formed by CVD, respectively, and in the step of FIG. ₂ In the film 32, the openings 32A to 32C respectively correspond to the conductor plugs 31A to 31C so as to expose the end faces of the conductor plugs 31A to 31C, and the SiO 2 ₂ In the film 33, openings 33A to 33C corresponding to the conductor plugs 31A to 31C are formed so as to expose the end faces of the conductor plugs 31A to 31C.
[0027]
Next, in the step of FIG. 7D, the SiO substrate is formed on the upper main surface of the Si substrate 31. ₂ A first electrode layer 34 in which a Ti film having a thickness of 0.1 μm and a Pt film having a thickness of 0.2 μm are stacked so as to cover the film 33 is formed on the conductor plugs 31A to 31C in the openings 33A to 33C, respectively. It is formed by sputtering so as to cover 31C, and is patterned in the step of FIG. ₂ An opening 34B exposing the opening 33B in the film 33, and the SiO ₂ An opening 34C exposing the opening 33C in the film 33 is formed. On the other hand, the electrode layer 34 is not patterned in the opening 33A, and is in contact with the exposed end face of the conductor plug 31A in the opening 33A in the SiO 2 film 33.
[0028]
Next, in the step of FIG. 7F, typically (Ba, Sr) is formed on the structure of FIG. ₂ TiO _Three The first high dielectric film 35 made of a high dielectric material such as BST (hereinafter abbreviated as BST) covers the electrode layer 34, and the openings 34B and 34C have the SiO 2 ₂ A uniform thickness of about 200 nm is formed by a sol-gel method so as to cover the side wall surfaces of the openings 33B and 33C of the film 33 and further cover the exposed end surfaces of the conductor plugs 31B and 31C. In the process of FIG. 7F, the high dielectric film 35 is actually formed in two steps, each time applying a starting solution of alkoxide by spin coating at 2000 rpm for 30 seconds, and then 120 ° C. Then, a step of drying at 400 ° C. and pre-baking is performed.
[0029]
When the film thickness of the high dielectric film 35 reaches a desired thickness in this way, the structure of FIG. 7F is heat-treated in the atmosphere at a temperature of 600 ° C., and the BST film 35 is crystallized. The By performing the heat treatment in this manner, a BST film having a relative dielectric constant of 500 and a dielectric loss of 2% or less can be obtained as the high dielectric film 35.
[0030]
Next, in the process of FIG. 7G, the high dielectric film 35 is patterned by a photolithography process using a resist mask (not shown), and an electrode layer covering the conductor plug 31A corresponding to the opening 33A. 34A, the opening 35B exposing the conductor plug 31B in the opening 33B, and the opening 35C exposing the conductor plug 31C in the opening 33C are formed.
[0031]
Next, in the step of FIG. 8H, a second electrode layer 36 similar to the electrode layer 34 is formed by sequentially sputtering a Ti film and a Pt film on the structure of FIG. A uniform thickness of about 0.3 μm is deposited so as to cover the high dielectric film 35. The electrode layer 36 is patterned in the subsequent step of FIG. 8I. As a result, an opening 36A that exposes the opening 35A in the high dielectric film 35 corresponding to the conductor plug 31A is also formed in the conductor plug 31A. An opening 36B that exposes the opening 35B in the high dielectric film 35 is formed corresponding to the plug 31B. On the other hand, the electrode layer 36 is left in contact with the end face of the conductor plug 31C exposed by the opening 35C in the opening 35C in the high dielectric film 35. In the opening 35B, the end face of the conductor plug 31B is exposed.
[0032]
Next, in the step of FIG. 8J, the second high dielectric film 37 is formed in the same thickness as the first high dielectric film 34 on the structure of FIG. 8K, in the high dielectric film 37, the opening 37A corresponding to the conductor plug 31A exposes the electrode layer 34 covering the end surface of the conductor plug 31A. An opening 37B corresponding to the conductor plug 37B is formed so as to expose the end face of the conductor plug 31B. Further, in the high dielectric film 37, an opening 37C corresponding to the conductor plug 37C is formed so as to expose the electrode layer 36 covering the end face of the conductor plug 31C.
[0033]
Next, in the step of FIG. 8L, a third electrode layer 38 similar to the first electrode layer 36 is formed with a uniform thickness of about 0.3 μm on the structure of FIG. Further, in the step of FIG. 8M, an opening 38B exposing the end face of the conductor plug 31B in the electrode layer 38 corresponding to the opening 37B in the high dielectric film 37 is also provided in the electrode layer 38. Corresponding to 37C, an opening 38C exposing the electrode layer 36 covering the end face of the conductor plug 31C is formed.
[0034]
8M, the electrode layers 34 and 38 are used as lower electrodes on the Si substrate 31, the first and second high dielectric films 35 and 37 are used as capacitor insulating films, and the electrode layer 36 is used. A ferroelectric capacitor C is formed with the upper electrode as the upper electrode.
[0035]
Next, a polyimide interlayer insulating film 39 is formed so as to cover the structure of FIG. 8M in the step of FIG. 9N, and in the polyimide interlayer insulating film 39 in the step of FIG. Contact holes 39A to 39C are formed corresponding to the conductor plugs 31A to 31C, respectively. However, the contact hole 39A exposes a portion of the electrode layer 38 laminated on the electrode layer 34 covering the end face of the conductor plug 39A, while the contact hole 39B exposes the short face of the conductor plug 39B. . Further, the contact hole 39C exposes the electrode layer 36 covering the end face of the conductor plug 39C.
[0036]
In the step of FIG. 9 (O), contact holes 39a that expose the electrode layer 38 are formed in the polyimide interlayer insulating film 39 at a plurality of locations where the electrode layer 38 covers the high dielectric film 37. 9P, an Au layer 40 having a thickness of about 2 μm is formed on the structure of FIG. 9O so as to fill the openings 39A to 39C and the contact hole 39a. .
[0037]
In the step of FIG. 9 (Q), the Au layer 40 includes a first connection pattern 40V that is electrically connected to the electrode layer 38 in 39a, and FIGS. 9 (O) to 10 (W). The electrode layer 36 is interposed through a plurality of other contact holes (not shown) formed so as to penetrate the electrode layer 38 and the high dielectric film 37 in the interlayer insulating film 39 and expose the electrode layer 36. The second connection pattern 40G is electrically connected to the second connection pattern 40G. As a result of such patterning, the contact holes 39A to 39C are exposed again in the step of FIG.
[0038]
Next, in the step of FIG. 9R, the structure of FIG. 9Q is covered with another polyimide film 41. In the step of FIG. 10S, the openings 39A to 39C are respectively formed in the polyimide film 41. Correspondingly, an opening 41A that exposes the electrode layer 38 that covers the end face of the conductor plug 31A via the electrode layer 34, an opening 41B that exposes an end face of the conductor plug 31B, and the conductor plug 31C. An opening 41C exposing the electrode layer 36 covering the end face is formed.
[0039]
Next, in the step of FIG. 10 (T), a 0.05 μm thick Cr film, a 2 μm thick Ni film, and a 0.2 μm thick Au film are sequentially formed on the structure of FIG. 10 (S). A conductor layer 42 is formed on the polyimide film 41 so as to cover the side walls and bottom surfaces of the openings 41A to 41C by depositing uniformly by a sputtering method. Further, in the step of FIG. The layer 42 is patterned to form surface electrode pads 42A to 42C corresponding to the openings 41A to 41C, respectively. Further, the openings 41A to 41C are filled with Au by performing electrolytic plating.
[0040]
Next, in the step of FIG. 10 (V), the SiO 2 is formed on the lower main surface of the structure of FIG. 10 (C). ₂ A conductor film 43 similar to the conductor film 42 is formed so as to cover the film 32 so that the conductor film 43 contacts the conductor plugs 31A to 31C in the openings 32A to 32C, respectively. In the step W), this is patterned to form contact electrode pads 43A to 43C corresponding to the openings 32A to 32C, respectively.
[0041]
FIG. 11A is a cross-sectional view of the capacitor component 30 thus formed, corresponding to the cross-sectional view of FIG. 10W, while FIG. 12B is a different cross-section of the same capacitor component 30. A cross-sectional view of is shown. However, illustration of the plating layer filling the openings 41A to 41C is omitted in order to avoid the illustration from becoming complicated.
[0042]
Referring to FIG. 11A, the conductor layer 40V is formed on the electrode layer 38 constituting the lower electrode of the ferroelectric capacitor C by a conductor plug 40v extending through the polyimide layer 39 at a plurality of locations. You can see that they are connected. The electrode layer 38 is connected to the surface electrode pad 42A together with the electrode layer 34 in the opening 41A. On the other hand, in the opening 41C, the electrode layer 36 is connected to the surface electrode pad 42C.
[0043]
The structure including the high dielectric capacitor C formed on the Si substrate 31, the connection patterns 40V and 40G, the insulating films 33, 39 and 41, and the surface electrode pads 42A to 42C is formed on the Si substrate 31 as a capacitor module CM. Configure.
[0044]
As will be described later, the conductor plug 31A is connected to the power supply line V on the wiring board to supply the power supply voltage to the LSI chip mounted on the capacitor component 30, while the conductor plug 31C is connected to the ground line. Connected to G to supply a ground potential to the LSI chip. Further, the conductor plug 31B transmits a signal between the LSI chip and the wiring board.
[0045]
FIG. 12B is a cross-sectional view taken along another cross section of the capacitor component 30 of FIG.
[0046]
Referring to FIG. 12B, in the electrode layer 38 and the high dielectric film 37, openings for exposing the electrode layer 36 are formed at a plurality of locations. The electrode layer 36 is connected to a corresponding connection pattern 40G via a conductor plug 40g extending through the interlayer insulating film 39.
[0047]
In the capacitor component 30 having such a configuration, the conductor plug 31A is electrically connected to the conductor plug 31C via a high dielectric capacitor composed of the electrode layers 34, 36, 38 and the high dielectric films 35, 37, and When the conductor plug 31A is connected to the power supply line V and the conductor plug 31C is connected to the ground line G, high-frequency noise on the power supply line V can be released to the ground line G through the high dielectric capacitor. Become. On the other hand, the conductor plug 31B is not connected to any of the conductor plugs 31A and 31C, and is connected to the signal line S to thereby transmit a signal between the LSI chip and the substrate.
[0048]
In the capacitor component 30, the electrode layers 34 and 38 are connected to the connection pattern 40V at a plurality of locations, and the electrode layer 36 is connected to the connection pattern 40G at a plurality of locations. At that time, the connection patterns 40V and 40G have a low thickness because they have a sufficient thickness. As a result, the electrode layers 34 and 38 or the electrode layer 36 is a conductor layer having a large sheet resistance formed by a thin film process. Even in this case, the equivalent series resistance ESR of the high dielectric capacitor C can be effectively reduced.
[0049]
In this embodiment, the ferroelectric insulating films 35 and 37 can be formed by sputtering or CVD in addition to the sol-gel method. As the ferroelectric insulating films 35 and 37, in addition to the BST film, (Pb, Zr) TiO _Three Membrane, SrBi ₂ Ta ₂ O ₉ Film or Pb (Mg, Nb) O _Three A membrane can be used. These films can be formed by a sol-gel method or a sputtering method.
[0050]
The substrate 31 may be a sapphire substrate in addition to the Si substrate. In this case, the through holes 31a to 31c may be formed by laser beam processing in the step of FIG.
[Second Embodiment]
FIG. 13 shows a configuration of an electronic device 100 according to the second embodiment of the present invention using the capacitor component 30 of FIGS. 11 (A) and 11 (B). However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
[0051]
Referring to FIG. 13, the electronic device 100 includes a wiring board 101 carrying wiring patterns 101V, 101G, and 101S. On the wiring board 101, the wiring pattern 101V is a power supply voltage supply pattern, and the wiring pattern 101G is a wiring pattern 101G. The ground pattern and the wiring pattern 101S constitute a signal pattern. The capacitor component 30 is mounted on the wiring substrate 101 by connecting the contact electrode pads 43A to 43C to the corresponding wiring patterns 101V, 101S, and 101G by solder bumps 102, and further on the capacitor component 30. The LSI chip 104 is mounted by connecting the surface electrode pads 42 </ b> A to 42 </ b> C of the capacitor component 30 to corresponding electrode pads (not shown) on the LSI chip 104 by solder bumps 103.
[0052]
In the electronic device 100 having such a configuration, since the capacitor component 30 is mounted in a form inserted between the wiring substrate 101 and the LSI chip 104, the equivalent inductance ESL described above with reference to FIG. Become. Further, since the increase in the electrode sheet resistance of the high dielectric capacitor C is suppressed by using the connection patterns 40V and 40G, the equivalent series resistance ESR is also reduced. As a result, ESR in FIG. _Three And ESL _Three As shown by the curve with the parameter as the parameter, even at a very high operating frequency fc2, the magnitude of the impedance of the capacitor component 30 is minimum, and even if the LSI chip 104 operates in the GHz band, the power supply noise Or it becomes possible to remove a high frequency ripple effectively.
[0053]
For example, Sn 96.5% -Ag 3.5% lead-free solder alloy is used as the solder bump 102 on the wiring board 101 side, and Pb 95% -Sn 5% solder alloy is used as the solder bump 103 on the LSI chip 104 side. be able to. In this case, the solder bump 102 has a melting point of 221 ° C., and the solder bump 103 has a melting point of 315 ° C.
[Third embodiment]
FIG. 14 shows the structure of a capacitor component 30A according to the third embodiment of the present invention. However, in FIG. 14, the same reference numerals are given to the parts described above, and the description thereof is omitted.
[0054]
Referring to FIG. 14, in this embodiment, unlike the previous embodiment of FIGS. 11 (A) and 12 (B), between one conductor plug 31A and an adjacent conductor plug 31B, or one conductor plug 31B. And 31C are provided with a single connection pattern 40G or 40V. In the cross section shown in the drawing, the connection pattern 40V is connected to the electrode layer 38 of the ferroelectric capacitor C through the conductor plug 40v in the interlayer insulating film 39. The conductor plug 40G is connected to the electrode layer 36 of the capacitor C through a conductor plug 40g (not shown).
[0055]
According to the capacitor part 30A of FIG. 14, the patterning of the connection patterns 40V and 40G is facilitated, and thus a preferable feature is obtained that facilitates the manufacture of the capacitor part 30A.
[Fourth embodiment]
15A and 15B show the configuration of a capacitor component 30B according to the fourth embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. As in the previous embodiment, FIGS. 15A and 15B show cross-sectional views along different cross sections of the same capacitor component 30B.
[0056]
Referring to FIG. 15A, in this embodiment, only the connection pattern 40V is formed on the interlayer insulating film 39 in the capacitor module CM, and the connection pattern 40G is formed on the interlayer insulating film 39. It is formed on an insulating film 41 covering the connection pattern 40V. Further, the connection pattern 40G is covered with another insulating film 44 on the insulating film 41.
[0057]
As shown in FIG. 15A, the connection pattern 40V is connected to the electrode layer 38 of the high dielectric capacitor at a plurality of locations by conductor plugs 40v extending through the interlayer insulating film 39. On the other hand, as shown in FIG. 15B, in the capacitor component 30C of the present embodiment, the connection pattern 40V, the electrode layer 38 of the high dielectric capacitor C, and the openings formed in the high dielectric insulating film 37 are formed. By forming and extending the conductor plug 40g through the opening, the connection pattern 40G is electrically connected to the electrode layer 36 at a plurality of locations.
[0058]
15A and 15B, the surface electrode pads 42A to 42C are formed inside the openings 44A to 44C formed in the insulating film 44 corresponding to the conductor plugs 31A to 31C, respectively. However, in the mounting structure of FIG. 13, the molten solder bump 103 can form contacts with the electrode pads 42 </ b> A to 42 </ b> C formed in the openings 44 </ b> A to 44 </ b> C. Of course, the electrode pads 42 </ b> A to 42 </ b> C can be extended to the surface of the insulating film 41.
[0059]
In the capacitor component 30B shown in FIGS. 15A and 15B, the connection patterns 40V and 40G can be easily patterned.
[Fifth embodiment]
16A and 16B show the configuration of a capacitor component 30C according to the fifth embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
[0060]
Referring to FIG. 16A, in this embodiment, the connection patterns 40V and 40G are formed directly on the substrate 31, and the conductor plug 40v is formed of the SiO 2. ₂ The connection pattern 40V is connected to the electrode layer 34 so as to extend through the film 33.
[0061]
On the other hand, in the cross section of FIG. 16B, the connection pattern 40G is formed on the substrate 31 by the conductor plug 40g extending through the contact hole formed in the electrode layer 34 and the high dielectric insulating film 35. Connected to layer 36. In the contact hole formed in the electrode layer 34, the side wall surface of the contact hole is covered with the high dielectric insulating film 35, and a short circuit between the conductor plug 40g and the electrode layer 34 is avoided.
[Sixth embodiment]
FIG. 17 shows a configuration of a capacitor component 30D according to the sixth embodiment of the present invention.
Referring to FIG. 17, the capacitor component 30 </ b> D has a vertically symmetrical configuration in which the capacitor module CM is formed on both sides of the Si substrate 31. The electronic device 100 of FIG. 13 can also be configured by the capacitor component 30D having such a configuration.
[0062]
Further, in the capacitor component 30D of FIG. 17, the high dielectric films 35 and 37 on one side of the substrate 31 are replaced with SrBi. ₂ TiO ₉ The high dielectric films 35 and 37 on the other side are formed of Pb (Mg, Nb) O. _Three May be formed.
[0063]
Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the claims.
[0064]
(Appendix 1) A capacitor component having a high dielectric capacitor,
A high dielectric capacitor having a structure in which a first capacitor electrode layer, a high dielectric capacitor insulating film, and a second capacitor electrode layer are sequentially stacked;
A plurality of through holes penetrating through the high dielectric capacitor;
A first electrode formed on the high dielectric capacitor and spaced apart and electrically connected to the first capacitor electrode layer at a plurality of locations;
A capacitor component comprising: a second electrode formed on the high dielectric capacitor so as to be spaced apart and electrically connected to the second capacitor electrode layer at a plurality of locations.
[0065]
(Supplementary note 2) The capacitor component according to supplementary note 1, wherein the first electrode and the second electrode are formed on substantially the same plane.
[0066]
(Supplementary Note 3) The capacitor component according to Supplementary Note 1, wherein the first electrode and the second electrode are formed in different planes.
[0067]
(Additional remark 4) The said 1st and 2nd electrode consists of a conductor pattern substantially thicker than any of the said 1st and 2nd capacitor electrode layer, Any one of Claims 1-3 characterized by the above-mentioned. The capacitor component according to claim 1.
[0068]
(Supplementary Note 5) The capacitor component according to any one of Supplementary Notes 1 to 4, wherein each of the first and second capacitor electrode layers has a thickness in a range of 50 to 300 nm.
[0069]
(Supplementary Note 6) The first electrode is connected to the first capacitor electrode layer by a plurality of conductor plugs, and the second electrode is connected to the second capacitor electrode layer. A plurality of contact holes formed so as to extend through the layer and the capacitor insulating film and expose the second capacitor electrode layer, and are connected by a plurality of conductor plugs extending through the plurality of contact holes. The capacitor component according to any one of Appendices 1 to 5, characterized in that:
[0070]
(Supplementary note 7) a substrate having a plurality of through holes penetrating from the first side to the second side;
A plurality of conductive plugs filling the plurality of through holes;
A plurality of contact electrode pads formed corresponding to each of the plurality of conductive plugs on the first side of the substrate;
A high dielectric capacitor formed on the second side of the substrate and having a first electrode layer, a high dielectric capacitor insulating film, and a second electrode layer sequentially stacked;
An insulating film covering the high dielectric capacitor on the second side of the substrate;
A plurality of openings extending through the high-dielectric capacitor and the insulating film corresponding to each of the plurality of through holes, and exposing the corresponding conductive plugs;
A plurality of contact electrode structures are provided on the insulating film so as to be electrically connected to the corresponding one of the plurality of conductive plugs, corresponding to each of the plurality of openings. In capacitor parts,
The plurality of through holes include a first through hole and a second through hole,
In the first through hole, the contact electrode structure is connected to the first electrode layer;
In the second through hole, the contact electrode structure is connected to the second electrode layer;
A first electrode pattern is formed on the second side of the substrate in a state of being electrically connected to the first electrode layer at a plurality of locations via a plurality of first conductor plugs. And
A second electrode pattern is formed on the second side of the substrate in a state of being electrically connected to the second electrode layer at a plurality of locations via a plurality of second conductor plugs. Capacitor parts characterized by having
[0071]
(Supplementary Note 8) The first and second electrode patterns are formed on the insulating film, and each of the first conductor plugs penetrates the insulating film and the second electrode layer and the high dielectric constant. Appendix 7 wherein the second conductive plug extends through a contact hole formed in the body capacitor insulating film so as to expose the first electrode layer, and the second conductive plug penetrates the insulating film. The capacitor component described.
[0072]
(Supplementary Note 9) The second electrode pattern is formed on the insulating film, and each of the second conductor plugs is formed through the insulating film,
The first electrode pattern is formed on another insulating film formed on the insulating film so as to cover the second electrode pattern, and each of the first conductor plugs includes the insulating film and the other Appendix 7 characterized by extending through a contact hole penetrating an insulating film and exposing the first electrode pattern in the second electrode layer and the high dielectric capacitor layer The capacitor component described.
[0073]
(Supplementary Note 10) The first electrode pattern is formed on the insulating film, each of the first conductor plugs penetrates the insulating film, and further in the second electrode layer and the high dielectric capacitor layer. Extending in a contact hole formed to expose the first electrode pattern,
The second electrode pattern is formed on another insulating film formed on the insulating film so as to cover the first electrode pattern, and each of the second conductor plugs includes the insulating film and the other The capacitor component according to appendix 7, wherein the capacitor component penetrates the insulating film.
[0074]
(Supplementary Note 11) The high-dielectric capacitor is formed on an interlayer insulating film that covers a surface of the substrate on the first side, and the first and second electrode patterns are formed on the first substrate of the substrate. The first conductor plugs pass through the interlayer insulating film, and the second conductor plugs are formed on the interlayer insulating film, and are covered with the interlayer insulating film. Appendix 7 characterized by extending through a contact hole formed so as to penetrate the insulating film and to expose the second electrode pattern in the first electrode layer and the ferroelectric capacitor layer. The capacitor component described.
[0075]
(Additional remark 12) Further, the plurality of through holes include a third through hole extending from the first side to the second side in the substrate, and the plurality of contact electrode structures include the third through hole. A third contact electrode structure corresponding to the through hole; and the plurality of contact electrode pads include a third contact electrode pad corresponding to the third through hole; The capacitor component according to any one of appendices 7 to 11, wherein the capacitor component is not in contact with any of the first and second electrode layers of the high dielectric capacitor.
[0076]
(Additional remark 13) The said 1st and 2nd electrode layer consists of a refractory metal selected from the group which consists of Pt, Au, Cu, Pd, Ni, Ru, and Ir. A capacitor component according to any one of the above.
[0077]
(Supplementary Note 14) Any one of Supplementary Notes 7 to 11, wherein the first and second electrode layers are made of a conductive metal oxide selected from the group consisting of Ru oxide and Ir oxide. The capacitor component according to one item.
[0078]
(Supplementary Note 15) The supplementary note wherein the high dielectric capacitor insulating film is made of a double oxide of a metal element selected from the group consisting of Sr, Ba, Pb, Zr, Bi, Ta, Ti, Mg, and Nb. The capacitor component according to any one of 7 to 11.
[0079]
(Supplementary Note 16) A wiring board carrying a wiring pattern including a power supply pattern, a ground pattern, and a signal line pattern, a capacitor component mounted on the wiring board, and a semiconductor chip flip-chip mounted on the capacitor component In an electronic device
The capacitor component has the configuration according to any one of appendices 7 to 14, wherein the first side faces the wiring board, and the first contact electrode pad is on the wiring board. The third contact electrode pad is further contacted with one of the power supply pattern or the ground pattern, and the second contact electrode pad is contacted with the other of the power supply pattern or the ground pattern on the wiring board. Mounted on the wiring board so as to contact the signal line pattern on the wiring board,
In the semiconductor chip, a ground pad is in contact with the first and second contact electrode structures connected to the power supply pattern on the wiring substrate, so that the ground pad is in the first and second contact electrode structures. Of the contact electrode structure, the signal line pad is mounted on the capacitor component so as to be in contact with the one connected to the ground pattern on the wiring board, and so that the signal line pad is in contact with the third contact electrode structure. An electronic device characterized by being made.
[0080]
【Effect of the invention】
According to the present invention, in a capacitor component that is inserted between an LSI chip and a wiring board to constitute an electronic device, a low resistance connection pattern is provided at a plurality of locations on an electrode layer of a high dielectric capacitor formed by a thin film process. By connecting, an increase in sheet resistance of the electrode layer can be avoided, and as a result, the equivalent series resistance of the capacitor component can be reduced. Such capacitor components with reduced equivalent series resistance can effectively eliminate noise by reducing the equivalent series inductance even when the LSI chip operates at a clock frequency in the GHz band.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a conventional electronic device having a capacitor connected to an LSI chip with a wiring pattern on a wiring board.
FIG. 2 is a diagram showing a configuration of another conventional electronic device having a capacitor embedded in a wiring board.
FIG. 3 is a diagram showing a configuration of an electronic device using an interposer type capacitor component according to the related art of the present invention.
4 is a diagram showing a configuration of a capacitor component in FIG. 3;
5A and 5B are diagrams showing an equivalent circuit diagram and frequency characteristics of the capacitor component of FIG. 3, respectively.
FIG. 6 is a diagram illustrating the principle of the present invention.
FIGS. 7A to 7G are views (No. 1) showing a manufacturing process of a capacitor component according to the first embodiment of the present invention. FIGS.
FIGS. 8H to 8M are views (No. 2) showing the manufacturing process of the capacitor component according to the first embodiment of the invention. FIGS.
9 (N) to (R) are views (No. 3) showing the manufacturing process of the capacitor component according to the first embodiment of the invention. FIG.
FIGS. 10 (S) to 10 (W) are views (No. 4) showing the manufacturing process of the capacitor component according to the first embodiment of the invention. FIGS.
FIG. 11A is a cross-sectional view showing the structure of the capacitor component according to the first embodiment of the present invention along the first cross section;
FIG. 12B is a sectional view showing the configuration of the capacitor component according to the second embodiment of the present invention along the second section.
FIG. 13 is a diagram showing a configuration of an electronic device according to a second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a configuration of a capacitor component according to a third embodiment of the present invention.
FIGS. 15A and 15B are cross-sectional views showing the configuration of the capacitor component according to the fourth embodiment of the present invention along the first and second cross sections, respectively. FIGS.
FIGS. 16A and 16B are cross-sectional views showing the configuration of the capacitor component according to the fifth embodiment of the present invention along the first and second cross sections, respectively. FIGS.
FIG. 17 is a cross-sectional view showing a configuration of a capacitor component according to a sixth embodiment of the present invention.
[Explanation of symbols]
10, 20, 100 Electronic device
11, 101 Wiring board
12, 104 LSI chip
13 Capacitor
13C contact hole
13T through hole
14, 30, 30A, 30B, 30C, 30D Capacitor parts
14a, 14b electrode terminal
14A, 14B electrode layer
14C High dielectric insulating film
31 substrates
31A-31C Conductor plug
32,33 SiO ₂ film
32A-32C, 33A-33C Opening
34, 36, 38 Electrode layer
35, 37 BST film
39, 41, 44 Interlayer insulation film
40, 42 Conductor film
40V, 40G connection pattern
40v, 40g conductor plug
42A-42C Surface electrode pad
43A-43C Electrode pad
102,103 Solder bump
C High dielectric capacitor
CM capacitor module

Claims (1)

A substrate having a plurality of through holes penetrating from the first side to the second side;
A plurality of conductive plugs filling the plurality of through holes;
A plurality of contact electrode pads formed on the first side of the substrate respectively corresponding to the plurality of conductive plugs;
A high dielectric capacitor formed on the second side of the substrate and having a first electrode layer, a high dielectric capacitor insulating film, and a second electrode layer sequentially stacked;
An insulating film covering the high dielectric capacitor on the second side of the substrate;
A plurality of openings extending through the high dielectric capacitor and the insulating film in correspondence with the plurality of through holes, respectively, and exposing the corresponding conductive plugs;
A capacitor having a plurality of contact electrode structures provided on the insulating film so as to be electrically connected to a corresponding one of the plurality of conductive plugs corresponding to the plurality of openings, respectively. In parts,
The plurality of through holes include a first through hole and a second through hole,
In the first through hole, the contact electrode structure is connected to the first electrode layer;
In the second through hole, the contact electrode structure is connected to the second electrode layer;
On the insulating film where the first electrode pattern covering the high dielectric capacitor in said second side of said substrate, the high dielectric capacitor a plurality of first provided so as to penetrate the insulating film covering It is formed in a state where it is electrically connected to the first electrode layer at a plurality of locations via a conductor plug,
Said second side of said substrate on the insulating film where the second electrode pattern covering the high-dielectric capacitor, the plurality of second provided so as to penetrate the insulating film covering the high-dielectric capacitor It is formed in a state where it is electrically connected to the second electrode layer at a plurality of locations via a conductor plug,
Further, the plurality of through holes include a third through hole extending in the substrate from the first side to the second side, and the plurality of contact electrode structures correspond to the third through hole. The plurality of contact electrode pads include a third contact electrode pad corresponding to the third through hole, and the third contact electrode structure includes the high dielectric capacitor. A capacitor component which is not in contact with any of the first and second electrode layers.

Images