JP5071655B2 - Control circuit - Google Patents

Description

  The present invention relates to a control circuit.

When controlling an external device based on data from a central processing unit (CPU) or the like, the number of output terminals required for the external device is required. However, there are not a few cases where the number of output terminals exceeding the number of output terminals prepared in the CPU is required. In such a case, a control circuit (control IC) that relays between the CPU and the external device is generally provided, and the control circuit has a number of output terminals necessary for controlling the external device.
JP-A-5-36270

  Conventionally, a control IC having the necessary number of output terminals has been prepared and used. However, since the required number of output terminals differs depending on the application (product), if a control IC having a large number of output terminals that can be used in all products is prepared, the package becomes large. Therefore, the mounting area becomes large and the package itself becomes expensive.

  In addition, when the number of output terminals of the control IC is minimized and the number of output terminals exceeding that is required, an external flip-flop circuit is provided outside the output terminal for outputting data from the CPU as it is. There is also a method of substantially increasing the number of output terminals by connecting and using the output terminals of the flip-flop circuit. However, since the output state of the external flip-flop circuit cannot be confirmed from the CPU, it is necessary to store the output state of the external flip-flop circuit inside the CPU, which causes a problem that the program operating on the CPU becomes complicated. . Further, although it is possible to newly provide a terminal for reading the output state of the external flip-flop circuit in the control IC, the purpose of reducing the number of terminals cannot be achieved.

  The present invention has been made in view of the above problems, and an object thereof is to provide a control circuit that can read the output state of an external flip-flop circuit from a CPU or the like without increasing the number of terminals. .

  (1) A control circuit according to the present invention is a control circuit that receives a control signal from a central processing unit and outputs data to at least one external device or the central processing unit according to the control signal. An input / output unit that inputs / outputs the control signal and data to / from a processing device, a first output unit that includes a plurality of external output terminals that output data input from the input / output unit, and an output terminal that includes the output terminal A data terminal of an external flip-flop circuit connected to one of the external devices and corresponding one-to-one with an address in the address space of the central processing unit is connected to the external output terminal of the first output unit. When connection is assumed, the external flip-flop circuit and a corresponding flip-flop circuit corresponding to one-to-one are included, and the external processing unit is connected to the external processing unit via the input / output unit. When a control signal for writing predetermined data to an address corresponding to the flip-flop circuit and the corresponding flip-flop circuit is received, the predetermined data is written to the external flip-flop circuit and the corresponding flip-flop circuit, and the input / output When a control signal for reading data at an address corresponding to the external flip-flop circuit and the corresponding flip-flop circuit is received from the central processing unit via the unit, the data held in the corresponding flip-flop circuit is And outputting to the central processing unit via the input / output unit.

  The control signal may include, for example, an instruction for writing predetermined data in a flip-flop circuit corresponding to a predetermined address and an instruction for reading data of a flip-flop circuit corresponding to a predetermined address.

  The external device may be a device that can be controlled based on a control signal from the central processing unit, such as a data input / output device, a communication device, a storage device, a lighting device, a display device, a power supply device, and a motor.

  The input / output unit may include an input terminal and an output terminal, or may share the input terminal and the output terminal. Further, the input / output unit and the central processing unit may be connected by, for example, a communication bus.

  The external flip-flop circuit and the corresponding flip-flop circuit may include a clock terminal that receives a clock signal for determining data update timing.

  According to the present invention, by using an output terminal that directly outputs data from the central processing unit and an external flip-flop circuit, a terminal that can output data to an external device without increasing the number of actual external output terminals is substantially provided. Furthermore, by reading out the output state of the corresponding flip-flop circuit from the central processing unit, the output state of the external flip-flop circuit is substantially read out without newly increasing the number of terminals of the control circuit. be able to.

  (2) In the control circuit according to the present invention, the same data is input to the data terminals of the external flip-flop circuit and the corresponding flip-flop circuit, and the clock terminals of the external flip-flop circuit and the corresponding flip-flop circuit are input. A clock signal based on the same timing signal is input.

  The control circuit may include a decoding unit that generates a clock signal from a control signal from the central processing unit.

  The clock signal may be generated based on a part of the control signal from the central processing unit as a timing signal. The clock signal may be generated based on a timing signal generated by performing a logical operation on a part of the control signal. The control signal that is the basis of the timing signal includes, for example, a chip select signal that designates the control circuit, an address signal that designates the address of the flip-flop circuit, and a write enable signal that permits the flip-flop circuit to write data.

  According to the present invention, the same data can be written to the external flip-flop circuit and the corresponding flip-flop circuit.

  (3) A control circuit according to the present invention includes a second output unit including a plurality of external output terminals, an external output terminal of the second output unit, and one address in an address space of the central processing unit. An output flip-flop circuit corresponding to each one-to-one and outputting data from the second output unit, and an address corresponding to the output flip-flop circuit from the central processing unit via the input / output unit When a control signal for writing predetermined data is received, the predetermined data is written to the output flip-flop circuit, and an address corresponding to the output flip-flop circuit is transmitted from the central processing unit via the input / output unit. When the control signal for reading the data is received, the data held in the output flip-flop circuit is transferred via the input / output unit. And outputs to the central processing unit.

  The output flip-flop circuit may include a clock terminal that receives a clock signal that determines data update timing.

  According to the present invention, since data can be output directly from the output flip-flop circuit, data can be output to an external device even when the external flip-flop circuit is not connected.

  (4) The control circuit according to the present invention has different timing signals for the external flip-flop circuit whose data terminal is connected to the same external output terminal of the first output section and the clock terminal of the output flip-flop circuit, respectively. A clock signal based on the above is input.

  The control circuit may include a decoding unit that generates a clock signal from a control signal from the central processing unit.

  The clock signal may be generated based on a part of the control signal from the central processing unit as a timing signal. The clock signal may be generated based on a timing signal generated by performing a logical operation on a part of the control signal. The control signal that is the basis of the timing signal includes, for example, a chip select signal that designates the control circuit, an address signal that designates the address of the flip-flop circuit, and a write enable signal that permits the flip-flop circuit to write data.

  According to the present invention, different data can be written to the external flip-flop circuit and the output flip-flop circuit. Thereby, the external output terminal can be used effectively.

  (5) The control circuit according to the present invention is configured such that the clock of the external flip circuit is connected when the data terminals of the plurality of external flip-flop circuits are assumed to be connected to the same external output terminal of the first output unit. A clock signal based on a different timing signal is input to each terminal.

  The control circuit may include a decoding unit that generates a clock signal from a control signal from the central processing unit.

  The clock signal may be generated based on a part of the control signal from the central processing unit as a timing signal. The clock signal may be generated based on a timing signal generated by performing a logical operation on a part of the control signal. The control signal that is the basis of the timing signal includes, for example, a chip select signal that designates the control circuit, an address signal that designates the address of the flip-flop circuit, and a write enable signal that permits the flip-flop circuit to write data.

  According to the present invention, different data can be written to a plurality of external flip-flop circuits.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. Moreover, this invention shall include what combined the following content freely.

  1 to 4 are diagrams for explaining an example of a control circuit according to an embodiment to which the present invention is applied.

(1) Configuration FIG. 1 is a diagram showing an example of a configuration of a control circuit according to an embodiment to which the present invention is applied.

  The control circuit 100 includes an input / output unit 101. The input / output unit 101 inputs / outputs control signals and data to / from the central processing unit 200. The input / output unit 101 may include an input terminal and an output terminal, or may share an input terminal and an output terminal. Further, the input / output unit 101 and the central processing unit 200 may be connected by, for example, a communication bus 130. The central processing unit 200 includes an address space 201 inside.

  The control circuit 100 includes a first output unit 110. The first output unit 110 outputs the data received by the input / output unit 101 to the external flip-flop circuit 301. The first output unit 110 includes a plurality of external output terminals 111. In the present embodiment, m external output terminals from external output terminals 111-1 to 111-m are included. The external device 400 may be a device that can be controlled based on a control signal from the central processing unit 200, such as a data input / output device, a communication device, a storage device, a lighting device, a display device, a power supply device, or a motor.

  The external flip-flop circuit 301 corresponds one-to-one with one address in the address space 201 of the central processing unit 200. The external flip-flop circuit 301 includes a clock terminal, a data terminal, a reset terminal (clear terminal), and an output terminal. An output terminal of the external flip-flop circuit 301 is connected to a predetermined external device 400 and outputs predetermined data.

  In this embodiment, k external flip-flop circuits from external flip-flop circuits 301-1 to 301-k are connected to each external output terminal 111 one by one. Note that the external flip-flop circuit 301 need not be connected to all the external output terminals 111. A plurality of external flip-flop circuits 301 may be connected to one external output terminal 111.

  The control circuit 100 may include a second output unit 112. The second output unit 112 outputs the output data of the output flip-flop circuit 104 to a predetermined external device 400. The second output unit 112 includes a plurality of external output terminals 113. In the present embodiment, n external output terminals from external output terminals 113-1 to 113-n are included.

  The control circuit 100 includes a corresponding flip-flop circuit 103. The corresponding flip-flop circuit 103 includes a clock terminal, a data terminal, a reset terminal (clear terminal), and an output terminal. Corresponding flip-flop circuit 103 corresponds to external flip-flop circuit 301 on a one-to-one basis. Data received by the input / output unit 101 is input to the data terminal of the corresponding flip-flop circuit 103. In the present embodiment, the data input to the data terminal of the corresponding flip-flop circuit 103-1 and the data output from the external output terminal 111-1 are the same. The output terminal of the corresponding flip-flop circuit 103 is connected to the input / output unit 101 via an output switching unit 107 described later.

  In the present embodiment, the control circuit 100 includes k corresponding flip-flop circuits corresponding to each external flip-flop circuit 301, corresponding to the corresponding flip-flop circuits 103-1 to 103-k. Note that the number of corresponding flip-flop circuits may be as many as the number of external flip-flop circuits that are assumed to be connected. For example, the corresponding flip-flop circuits include cases corresponding to external flip-flop circuits that are not actually connected.

  The control circuit 100 may include an output flip-flop circuit 104. The output flip-flop circuit 104 includes a clock terminal, a data terminal, a reset terminal (clear terminal), and an output terminal. The output flip-flop circuit 104 has a one-to-one correspondence with one address in the address space 201 of the central processing unit 200. Data received by the input / output unit 101 is input to the data terminal of the output flip-flop circuit 104. In the present embodiment, since n external output terminals 113-1 to 113-n are included, n output flip-flop circuits 104 are also provided corresponding to each external output terminal. ing. The output terminal of the output flip-flop circuit 104 is connected to a predetermined external device 400 via the second output unit 112. An output terminal of the output flip-flop circuit 104 is connected to the input / output unit 101 via an output switching unit 108 described later.

  Note that the corresponding flip-flop circuit 103 and the output flip-flop circuit 104 may be integrally configured as the internal flip-flop matrix 120.

  The control circuit 100 may include a decoding unit 105. The decoding unit 105 may determine an address and a write or read command included in the control signal from the central processing unit 200. The decoding unit 105 may output a clock signal to the clock terminal of the external flip-flop circuit 301, the corresponding flip-flop circuit 103, or the output flip-flop circuit 104 corresponding to the address included in the control signal from the central processing unit 200. Further, the decoding unit 105 may output a result of determining a write or read command included in the control signal from the central processing unit 200 to the output switching unit 107 and the output switching unit 108 described later.

  The control circuit 100 may include a reset signal generation unit 106. The reset signal generation unit 106 outputs a predetermined signal to the reset terminal (clear terminal) of the external flip-flop circuit 301, the corresponding flip-flop circuit 103, and the output flip-flop circuit 104 based on a signal from the outside of the control circuit 100. Initial values of the external flip-flop circuit 301, the corresponding flip-flop circuit 103, and the output flip-flop circuit 104 may be set. The central processing unit 200 may output an external signal.

  The control circuit 100 may include an output switching unit 107. The output switching unit 107 is connected to the output terminal of the corresponding flip-flop circuit 103, and is output to the central processing unit 200 via the input / output unit 101 and the normal state in which data is not output to the outside based on the output result of the decoding unit 105. The read state to be switched may be switched.

  The control circuit 100 may include an output switching unit 108. The output switching unit 108 is connected to the output terminal of the output flip-flop circuit 104, and based on the output result of the decoding unit 105, the normal state in which data is output only to the external device 400 via the second output unit 112, and the data May be output to the external device 400 via the second output unit 112 and the read state to be output to the central processing unit 200 via the input / output unit 101 may be switched.

  The control circuit 100 according to the present embodiment may be configured with, for example, a dedicated semiconductor integrated circuit, or may be configured with a CPLD (Complex Programmable Logic Device). Further, the external flip-flop circuit 301 may be constituted by a general-purpose flip-flop IC with a clock input including a plurality of flip-flop circuits.

(2) Operation (a) Write Operation to External Flip-Flop Circuit and Corresponding Flip-Flop Circuit First, a control signal for writing predetermined data from the central processing unit 200 to addresses corresponding to the external flip-flop circuit 301 and the corresponding flip-flop circuit 103 The operation of writing predetermined data in the external flip-flop circuit 301 and the corresponding flip-flop circuit 103 when the signal is received will be described.

  FIG. 2 is a timing chart for explaining the operation of writing data to the external flip-flop circuit 301 and the corresponding flip-flop circuit 103 based on the control signal of one clock of the central processing unit 200 in the control circuit of FIG. .

  The signal (A) in FIG. 2 is a chip select signal. The chip select signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The chip select signal is used to specify a control circuit to which a command is sent when a plurality of control circuits are connected to the central processing unit 200. In the present embodiment, the control circuit 100 is selected when the chip select signal is at a low level.

  The signal (B) in FIG. 2 is an address signal. The address signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The address signal corresponds to an address in the address space 201 and is used to specify a flip-flop circuit to which data is written. In the present embodiment, the decoding unit 105 is configured so that the address signal is associated with each flip-flop circuit.

  The signal (C) in FIG. 2 is an input data signal. The input data signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The input data signal represents data written to each flip-flop circuit.

  The signal (D) in FIG. 2 is a write enable signal. The write enable signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The write enable signal is used to allow the flip-flop circuit specified by the chip select signal and the address signal to write data represented by the input data signal. In this embodiment, data is written to the specified flip-flop circuit when the write enable signal is at the low level.

  A signal (E) in FIG. 2 is an address decode signal that is an internal signal of the decoding unit 105. The address decode signal is a signal that specifies a flip-flop circuit to which data is written by the chip select signal and the address signal input from the input / output unit 101. In this embodiment, the address decode signal is set to the high level when both the chip select signal and the address signal are at the low level. In this embodiment, since the address decode signal is generated after the write enable signal is changed from the high level to the low level and writing is permitted, the decode unit 105 performs decoding compared to the chip select signal and the address signal. The address decode signal is generated with a delay of time (decode time) T1 required.

  A signal (F) in FIG. 2 is an output signal of the decoding unit 105 and is a first clock signal input to the clock terminal of the corresponding flip-flop circuit 103. The first clock signal determines the update timing of data held by the corresponding flip-flop circuit 103. In the present embodiment, the data held in the corresponding flip-flop circuit 103 is input to the data terminal of the corresponding flip-flop circuit 103 at the timing when the first clock signal changes from the Low level to the High level. It is comprised so that it may update to the data which represents. In this embodiment, after the address decode signal changes from the low level to the high level and the corresponding flip-flop circuit 103 is specified, the decode unit 105 inverts the write enable signal to generate the first clock signal. Therefore, the first clock signal is generated with a delay of the time required for decoding by the decoding unit 105 (decoding time) T2 as compared with the write enable signal. That is, in this embodiment, the first clock signal is generated using the product of the address decode signal and the inverted signal of the write enable signal as a timing signal.

  A signal (G) in FIG. 2 is an output signal of the corresponding flip-flop circuit 103. The output signal of the corresponding flip-flop circuit 103 is output from the output terminal of the corresponding flip-flop circuit 103 as the updated data corresponding to the first clock signal, that is, the data held in the corresponding flip-flop circuit 103 Signal. In the present embodiment, as the output signal of the corresponding flip-flop circuit 103, the data held in the corresponding flip-flop circuit 103 is output at the timing when the first clock signal changes from the Low level to the High level.

  A signal (H) in FIG. 2 is an output signal of the decoding unit 105 and is a second clock signal input to the clock terminal of the external flip-flop circuit 301. The second clock signal determines the update timing of data held by the external flip-flop circuit 301. In this embodiment, the data held by the external flip-flop circuit 301 is input to the data terminal of the external flip-flop circuit 301 at the timing when the second clock signal changes from the Low level to the High level. It is comprised so that it may update to the data which represents. In the present embodiment, similarly to the first clock signal, after the address decode signal changes from the low level to the high level and the corresponding flip-flop circuit 103 is specified, the decode unit 105 inverts the write enable signal. Thus, the second clock signal is generated. That is, in this embodiment, the second clock signal is generated using the product of the address decode signal and the inverted signal of the write enable signal as a timing signal. In this embodiment, since the decoding unit 105 generates the second clock signal depending on the first clock signal, the pulse width of the first clock signal is larger than that of the first clock signal. Although the second clock signal is generated with a time T4 shorter than T3, T4 may be zero.

  A signal (I) in FIG. 2 is an output signal of the external flip-flop circuit 301. The output signal of the external flip-flop circuit 301 is output from the output terminal of the external flip-flop circuit 301 as the data after being updated corresponding to the second clock signal, that is, the data held in the external flip-flop circuit 301 Signal. In the present embodiment, as the output signal of the external flip-flop circuit 301, data held in the external flip-flop circuit 301 is output at the timing when the second clock signal changes from Low level to High level.

  With the above operation, the same data can be written to the external flip-flop circuit 301 and the corresponding flip-flop circuit 103 based on the control signal of one clock of the central processing unit 200.

  The reset signal generation unit 106 outputs a reset signal at the same timing to the clear terminal (reset terminal) of the external flip-flop circuit 301 and the clear terminal (reset terminal) of the corresponding flip-flop circuit 103, so that the external The initial values of the flip-flop circuit 301 and the corresponding flip-flop circuit 103 can be made uniform.

(B) Reading Operation from Corresponding Flip-Flop Circuit Next, a control signal for reading data at addresses corresponding to the external flip-flop circuit 301 and the corresponding flip-flop circuit 103 is received from the central processing unit 200 via the input / output unit 101. The operation of outputting the data held in the corresponding flip-flop circuit 103 to the central processing unit 200 via the input / output unit 101, that is, the operation of reading the data from the corresponding flip-flop circuit 103 will be described.

  FIG. 3 is a timing chart for explaining the operation of reading data from the corresponding flip-flop circuit 103 based on the control signal of one clock of the central processing unit 200 in the control circuit of FIG.

  The signal (J) in FIG. 3 is a chip select signal. The chip select signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The chip select signal is used to specify a control circuit to which a command is sent when a plurality of control circuits are connected to the central processing unit 200. In the present embodiment, the control circuit 100 is selected when the chip select signal is at a low level.

  The signal (K) in FIG. 3 is an address signal. The address signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The address signal corresponds to an address in the address space 201 and is used to specify a flip-flop circuit that reads data. In the present embodiment, the decoding unit 105 is configured so that the address signal is associated with each flip-flop circuit.

  The signal (L) in FIG. 3 is an output data signal. The output data signal is output from the control circuit 100 via the input / output unit 101 and input to the central processing unit 200. That is, this signal represents data read by the central processing unit 200 in this operation. A method for generating the output data signal will be described later.

  A signal (M) in FIG. 3 is a read enable signal. The read enable signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The read enable signal is used to permit the flip-flop circuit specified by the chip select signal and the address signal to read data. In the present embodiment, data is read from the specified flip-flop circuit when the read enable signal is at a low level.

  A signal (N) in FIG. 3 is an address decode signal that is an internal signal of the decoding unit 105. The address decode signal is a signal that identifies a flip-flop circuit that reads data based on a chip select signal and an address signal input from the input / output unit 101. In this embodiment, the address decode signal is set to the high level when both the chip select signal and the address signal are at the low level. In this embodiment, since the address decode signal is generated after the read enable signal is changed from the high level to the low level and the read is permitted, the decode unit 105 performs the decoding compared to the chip select signal and the address signal. The address decode signal is generated with a delay of time (decode time) T5.

  A signal (O) in FIG. 3 is an output enable signal that is an output signal of the decoding unit 105. The output enable signal is input to the output switching unit 107. The output switching unit 107 to which the output enable signal is input, from the normal state in which the output signal from the output terminal of the corresponding flip-flop circuit 103 is not output to the outside, from the input / output unit 101 via the communication bus 130 to the central processing unit. The read state is output to 200. In the present embodiment, the read enable state is set when the output enable signal is at a high level. In this embodiment, since the output enable signal is generated after the address decode signal is changed from the low level to the high level and the corresponding flip-flop circuit 103 is specified, the output enable signal is generated as compared with the read enable signal. The output enable signal is generated with a delay of the time required for decoding by the unit 105 (decoding time) T6. Note that the output enable signal may be output only when the write enable signal described with reference to FIG. 2 is not input in the write operation.

  Then, when the output enable signal is switched to the read state, the output data signal described above is output to the central processing unit 200 via the input / output unit 101. In this embodiment, the output data signal is configured to be output at time T7 when the chip select signal, the address signal, and the output enable signal overlap.

  With the above operation, data can be read from the corresponding flip-flop circuit 103 based on the control signal of one clock of the central processing unit 200. Since the same data is written in the corresponding flip-flop circuit 103 and the external flip-flop circuit 301 by the above-described write operation, the same result as when the central processing unit 200 reads the data from the external flip-flop circuit 301 is obtained. be able to.

(C) Write Operation to Output Flip-Flop Circuit Next, when a control signal for writing predetermined data to an address corresponding to the output flip-flop circuit 104 is received from the central processing unit 200 via the input / output unit 101, An operation for writing predetermined data in the output flip-flop circuit 104 will be described.

  FIG. 4 is a timing chart for explaining the operation of writing data to the output flip-flop circuit 104 based on the control signal of one clock of the central processing unit 200 in the control circuit of FIG.

  The signal (P) in FIG. 4 is a chip select signal. The chip select signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The chip select signal is used to specify a control circuit to which a command is sent when a plurality of control circuits are connected to the central processing unit 200. In the present embodiment, the control circuit 100 is selected when the chip select signal is at a low level.

  The signal (Q) in FIG. 4 is an address signal. The address signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The address signal corresponds to an address in the address space 201 and is used to specify a flip-flop circuit to which data is written. In the present embodiment, the decoding unit 105 is configured so that the address signal is associated with each flip-flop circuit.

  The signal (R) in FIG. 4 is an input data signal. The input data signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The input data signal represents data written to each flip-flop circuit.

  The signal (S) in FIG. 4 is a write enable signal. The write enable signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The write enable signal is used to allow the flip-flop circuit specified by the chip select signal and the address signal to write data represented by the input data signal. In this embodiment, data is written to the specified flip-flop circuit when the write enable signal is at the low level.

  A signal (T) in FIG. 4 is an address decode signal that is an internal signal of the decoding unit 105. The address decode signal is a signal that specifies a flip-flop circuit to which data is written by the chip select signal and the address signal input from the input / output unit 101. In this embodiment, the address decode signal is set to the high level when both the chip select signal and the address signal are at the low level. In this embodiment, since the address decode signal is generated after the write enable signal is changed from the high level to the low level and writing is permitted, the decode unit 105 performs decoding compared to the chip select signal and the address signal. The address decode signal is generated with a delay of time (decode time) T8 required.

  A signal (U) in FIG. 4 is an output signal of the decoding unit 105 and is a third clock signal input to the clock terminal of the output flip-flop circuit 104. The third clock signal determines the update timing of data held by the output flip-flop circuit 104. In this embodiment mode, the data held by the output flip-flop circuit 104 is input to the data terminal of the output flip-flop circuit 104 at the timing when the third clock signal changes from the Low level to the High level. It is comprised so that it may update to the data which represents. In this embodiment, after the address decode signal changes from the low level to the high level and the output flip-flop circuit 104 is specified, the decode unit 105 inverts the write enable signal to generate the first clock signal. Therefore, the third clock signal is generated with a delay of the time required for decoding by the decoding unit 105 (decoding time) T9 compared to the write enable signal. That is, in the present embodiment, the third clock signal is generated using the product of the address decode signal and the inverted signal of the write enable signal as a timing signal.

  In the address space 200 described above, the output flip-flop circuit 104 has a one-to-one correspondence with different addresses from the corresponding flip-flop circuit 103 and the external flip-flop circuit 301. Therefore, the third clock signal is generated at a timing that does not overlap with the first clock signal and the second clock signal described above.

  A signal (V) in FIG. 4 is an output signal of the output flip-flop circuit 104. The output signal of the output flip-flop circuit 104 is a signal that is output from the output terminal of the output flip-flop circuit 104 in accordance with the data written corresponding to the third clock signal, that is, the data held in the output flip-flop circuit 104 It is. In the present embodiment, as the output signal of the output flip-flop circuit 104, the data held in the output flip-flop circuit 104 is output at the timing when the third clock signal changes from Low level to High level.

  With the above operation, data can be written to the output flip-flop circuit 104 based on the control signal of one clock of the central processing unit 200.

  Unlike the corresponding flip-flop circuit 103, the output flip-flop circuit 104 is not a flip-flop circuit corresponding to the external flip-flop circuit 301 on a one-to-one basis. Therefore, the operation of writing the same data as the data written to the output flip-flop circuit 104 to the external flip-flop circuit 301 is not performed.

  Further, the reset signal generation unit 106 can set the initial value of the output flip-flop circuit 104 by outputting a reset signal to the clear terminal (reset terminal) of the output flip-flop circuit 104.

(D) Reading Operation from Output Flip-Flop Circuit Next, when a control signal for reading data at an address corresponding to the output flip-flop circuit 104 is received from the central processing unit 200 via the input / output unit 101, an output flip-flop An operation of outputting data held in the output circuit 104 to the central processing unit 200 via the input / output unit 101, that is, an operation of reading data from the output flip-flop circuit 104 will be described.

  In the control circuit of FIG. 1, the operation of reading data from the output flip-flop circuit 104 based on the control signal of one clock of the central processing unit 200 is almost the same as the operation of reading data from the corresponding flip-flop circuit 103. This will be described with reference to the timing chart of FIG. 3 again.

  The signal (J) in FIG. 3 is a chip select signal. The chip select signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The chip select signal is used to specify a control circuit to which a command is sent when a plurality of control circuits are connected to the central processing unit 200. In the present embodiment, the control circuit 100 is selected when the chip select signal is at a low level.

  The signal (K) in FIG. 3 is an address signal. The address signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The address signal corresponds to an address in the address space 201 and is used to specify a flip-flop circuit that reads data. In the present embodiment, the decoding unit 105 is configured so that the address signal is associated with each flip-flop circuit.

  The signal (L) in FIG. 3 is an output data signal. The output data signal is output from the control circuit 100 via the input / output unit 101 and input to the central processing unit 200. That is, this signal represents data read by the central processing unit 200 in this operation. A method for generating the output data signal will be described later.

  A signal (M) in FIG. 3 is a read enable signal. The read enable signal is one of control signals output from the central processing unit 200 and input to the input / output unit 101 via the communication bus 130. The read enable signal is used to permit the flip-flop circuit specified by the chip select signal and the address signal to read data. In the present embodiment, data is read from the specified flip-flop circuit when the read enable signal is at a low level.

  A signal (N) in FIG. 3 is an address decode signal that is an internal signal of the decoding unit 105. The address decode signal is a signal that identifies a flip-flop circuit that reads data based on a chip select signal and an address signal input from the input / output unit 101. In this embodiment, the address decode signal is set to the high level when both the chip select signal and the address signal are at the low level. In this embodiment, since the address decode signal is generated after the read enable signal is changed from the high level to the low level and the read is permitted, the decode unit 105 performs the decoding compared to the chip select signal and the address signal. The address decode signal is generated with a delay of time (decode time) T5.

  A signal (O) in FIG. 3 is an output enable signal that is an output signal of the decoding unit 105. The output enable signal is input to the output switching unit 108. The output switching unit 108, to which the output enable signal is input, from the normal state in which the output signal from the output terminal of the output flip-flop circuit 104 is output only to the external device 400 via the second output unit 112, from the second state. Output to the external device 400 via the output unit 112, and switch to a reading state in which the input / output unit 101 outputs to the central processing unit 200 via the communication bus 130. In the present embodiment, the read enable state is set when the output enable signal is at a high level. In this embodiment, since the output enable signal is generated after the address decode signal changes from the low level to the high level and the output flip-flop circuit 104 is specified, the output enable signal is generated as compared with the read enable signal. The output enable signal is generated with a delay of the time required for decoding by the unit 105 (decoding time) T6. Note that the output enable signal may be output only when the write enable signal described with reference to FIG. 4 is not input in the write operation.

  Then, when the output enable signal is switched to the read state, the output data signal described above is output to the central processing unit 200 via the input / output unit 101. In this embodiment, the output data signal is configured to be output at time T7 when the chip select signal, the address signal, and the output enable signal overlap.

  With the above operation, data can be read from the output flip-flop circuit 104 based on the control signal of one clock of the central processing unit 200.

(3) Effects of the present embodiment The control circuit according to the present embodiment is configured as described above. According to this control circuit, the corresponding flip-flop circuit 103 corresponding one-to-one with the external flip-flop circuit 301 is used, and the address corresponding to the external flip-flop circuit 301 is predetermined from the central processing unit 200 via the input / output unit 101. When the control signal for writing the data is received, predetermined data is written to the external flip-flop circuit 301 and the corresponding flip-flop circuit 103, and from the central processing unit 200 to the external flip-flop circuit 301 via the input / output unit 101. When a control signal for reading the data at the corresponding address is received, the data held in the corresponding flip-flop circuit 103 is output to the central processing unit via the input / output unit. The first output unit 110 that outputs as it is and the external flip-flow By using the circuit 301, it is possible to substantially increase the number of terminals that can output data to the external device 400 without increasing the number of actual external output terminals. By reading the output state of the circuit 103, the output state of the external flip-flop circuit 301 can be substantially read without newly increasing the number of terminals of the control circuit 100.

  Further, the same data is input to the data terminals of the external flip-flop circuit 301 and the corresponding flip-flop circuit 103, and clock signals based on the same timing signal are input to the clock terminals of the external flip-flop circuit 301 and the corresponding flip-flop circuit 103. Since it is input, the same data can be written to the external flip-flop circuit 301 and the corresponding flip-flop circuit 103.

  Furthermore, by having the output flip-flop circuit 104 corresponding one-to-one with each address in the address space 201 of the external output terminal 111 and the central processing unit 200, it is possible to directly output from the output flip-flop circuit 104, Data can be output to the external device 400 even when the external flip-flop circuit 301 is not connected.

  In addition, clock signals based on different timing signals are input to the clock terminals of the external flip-flop circuit 301 and the output flip-flop circuit 104 whose data terminals are connected to the same external output terminal 111, whereby the external flip-flop circuit Different data can be written to 301 and the output flip-flop circuit 104. Thereby, the external output terminal 111 can be used effectively.

  In addition, when the data terminals of a plurality of external flip-flop circuits 301 are connected to the same external output terminal 111, they correspond to different addresses in the address space 201 on a one-to-one basis. Clock signals based on different timing signals are input to clock terminals of the flip circuit 301, and different data can be written to the plurality of external flip-flop circuits 301.

  Furthermore, in the control circuit according to the present embodiment, for example, even if data is input to the corresponding flip-flop circuit 103 corresponding to the external flip-flop circuit 301 that is not actually connected, the data is output from the external output terminal 111. Only the data is ignored, and no particular inconvenience occurs. Therefore, regardless of whether or not the external flip-flop circuit 301 is connected, the central processing unit 200 can execute the same program, and a control circuit with high program compatibility and versatility can be realized.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

  For example, in this embodiment, k external flip-flop circuits from external flip-flop circuits 301-1 to 301-k are connected to each external output terminal 111 one by one. Need not be connected to all external output terminals 111, and a plurality of external flip-flop circuits 301 may be connected to one external output terminal 111. That is, the number of external flip-flop circuits 301 can be arbitrarily set according to the needs of the external device 400.

An example of the structure of the control circuit which concerns on embodiment to which this invention is applied. 4 is a timing chart for explaining the operation of the control circuit according to the embodiment to which the present invention is applied. 4 is a timing chart for explaining the operation of the control circuit according to the embodiment to which the present invention is applied. 4 is a timing chart for explaining the operation of the control circuit according to the embodiment to which the present invention is applied.

Explanation of symbols

100 control circuit, 101 input / output unit, 103 corresponding flip-flop circuit, 104 output flip-flop circuit, 105 decoding unit, 106 reset signal generation unit, 107 output switching unit, 108 output switching unit, 110 first output unit, 111 external Output terminal, 112 Second output unit, 113 External output terminal, 120 Internal flip-flop matrix, 130 Communication bus, 200 Central processing unit, 201 Address space, 301 External flip-flop circuit, 400 External device

Claims (5)

A control circuit that receives a control signal from a central processing unit and outputs data to at least one external device or the central processing unit according to the control signal;
An input / output unit for inputting / outputting the control signal and data to / from the central processing unit;
A first output unit including a plurality of external output terminals for outputting data input from the input / output unit;
An output terminal is connected to one of the external devices, and a data terminal of the external flip-flop circuit corresponding to one address in the address space of the central processing unit is connected to the external of the first output unit. When connection to an output terminal is assumed, the external flip-flop circuit and a corresponding flip-flop circuit corresponding one-to-one,
When a control signal for writing predetermined data to an address corresponding to the external flip-flop circuit and the corresponding flip-flop circuit is received from the central processing unit via the input / output unit, the external flip-flop circuit and the Write the predetermined data to the corresponding flip-flop circuit,
When a control signal for reading data at an address corresponding to the external flip-flop circuit and the corresponding flip-flop circuit is received from the central processing unit via the input / output unit, the control signal is held in the corresponding flip-flop circuit. The control circuit is characterized in that the output data is output to the central processing unit via the input / output unit. The control circuit according to claim 1,
The same data is input to the data terminals of the external flip-flop circuit and the corresponding flip-flop circuit,
A control circuit, wherein clock signals based on the same timing signal are input to clock terminals of the external flip-flop circuit and the corresponding flip-flop circuit. The control circuit according to claim 1 or 2,
A second output unit including a plurality of external output terminals;
An output flip-flop circuit that has a one-to-one correspondence with an external output terminal of the second output unit and one address in the address space of the central processing unit, and outputs data from the second output unit; Including
When a control signal for writing predetermined data to an address corresponding to the output flip-flop circuit is received from the central processing unit via the input / output unit, the predetermined data is written to the output flip-flop circuit,
When a control signal for reading data at an address corresponding to the output flip-flop circuit is received from the central processing unit via the input / output unit, the data held in the output flip-flop circuit is input to the input flip-flop circuit. A control circuit for outputting to the central processing unit via an output unit. The control circuit according to claim 3,
Clock signals based on different timing signals are input to the clock terminals of the external flip-flop circuit and the output flip-flop circuit whose data terminals are connected to the same external output terminal of the first output section, respectively. Control circuit. The control circuit according to any one of claims 1 to 4,
When connection of data terminals of the plurality of external flip-flop circuits is assumed to be connected to the same external output terminal of the first output unit, clock signals based on different timing signals are respectively provided to clock terminals of the external flip circuit. A control circuit characterized by being input.

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