JP4928666B2 - Format and frame rate conversion for 24Hz source video display - Google Patents

Description

[0001]
This application is related to US patent application serial number 09 / 001,952 (patent attorney docket number 12713). This is filed on the same day as the present application.
[0002]
This application is related to US patent application serial number 09 / 001,620 (patent attorney docket 12669). This is filed on the same day as the present application.
[0003]
BACKGROUND OF THE INVENTION
The present invention relates generally to video processing systems, and in particular, video processing systems capable of receiving and processing multiple video signal formats, such as various high definition and standard definition formats. Is related to.
[0004]
BACKGROUND OF THE INVENTION
Current television receivers, such as NTSC (National Television Commission) television receivers, include video processing circuitry, which typically can only process video signals that conform to only a single predetermined video format. . Most future digital television (DTV) receivers are expected to be implemented according to broadcast standards established by the Next Generation Television Standards Committee (ATSC). A similar standard is the European Digital Video Broadcasting (DVB) standard. The compressed digital video system is described in ATSC digital television standard document A / 53, which is included herein by reference. In addition, the Color Video Code Standards Working Group (MPEG) has published several standards for digital data transmission systems. The first is known as MPEG-1 and relates to the ISO / IEC standard 11172, which is included herein as a reference. The second is known as MPEG-2 and relates to ISO / IEC standard 13818, which is included in the present application as a reference. The new DTV standard allows broadcasters to transmit in virtually any format up to 1920x1080 pixels. Specifically, the DTV receiver is capable of images with various spatial resolutions (480, 720, 1080), temporal resolution (60 fps, 30 fps, 24 fps), scanning format (2: 1 interlaced or progressive scanning). You must be able to receive source video with a sequence.
[0005]
It is known in the computer industry to display multiple image formats on so-called “multisync” display devices. Specifically, the multisync display changes the horizontal scanning frequency and the vertical scanning frequency in response to a change in the graphic format. Such a multi-sync approach can be implemented in a video or television environment, using studio equipment raster formats, etc., standardized by the Association of Movie and Television Engineers (SMPTE). Unfortunately, the multi-sink approach leads to increased cost due to the complexity of the deflection circuit, increased power consumption, and the long switching time between formats due to the long time constant associated with the deflection coil inductance.
[0006]
A better approach is disclosed by Lee in US Pat. No. 5,485,216 “High Quality Television Video Converter” issued on January 16, 1996. In Lee's patent, a high-definition television signal is decoded and then converted to a 30 Hz frame rate, followed by vertical reduction and horizontal reduction in sequence, and interleaved to produce a 30 Hz, 1050 vertical scan video signal. Therefore, Lee's method uses a brute force technique to convert a high definition television signal to a 30 Hz, 1050 vertical scan line video signal. The television signal whose format has been converted is processed by a conventional method to form an image.
[0007]
Unfortunately, Lee's method has the disadvantage of requiring complex timing, switching, and video processing circuitry. In addition, the television signal produced by Lee's method has the property of causing video video malfunctions in the case of 24 Hz source video (film, etc.). This is because 24 frames per second video is converted to 60 frames per second using the 3: 2 pull-up sequence, which is well known by Lee's method. As a result, when the converted video is displayed, A problem with video jitter occurs. Since most of the golden hour television programs are film master, most of the video data will continue to be transmitted in 24Hz progressive scan format.
[0008]
Thus, there is a need for cost-effective video processing system technology suitable for use with, for example, television receivers that support multiple formats. Furthermore, it would be desirable to provide a video processing system suitable for use with 24 Hz source video.
[0009]
SUMMARY OF THE INVENTION
The present invention avoids defects in video display due to 3: 2 conversion of 24 Hz source video by doubling the frame rate of the source video and reactively adjusting the format of the resulting video signal. An electronic format and frame rate conversion method and associated apparatus in an adaptive multi-format video processing system.
[0010]
Specifically, the present invention is a method for use in a video processing system comprising a format converter and a frame rate converter, the format converter being responsive to a format control signal for the vertical and horizontal formats of the input video signal The frame rate converter adapts the frame rate of the input video signal in response to the frame rate control signal. The steps provided by this method include checking the format and frame rate of the input video signal, adapting the input video signal to the native display format, and if the frame rate of the input video signal is a first value, eg, about 24 Hz, Triple the frame rate of the input video signal.
[0011]
The present invention is also an apparatus for processing an input video signal having one of a plurality of video formats to produce an output video signal. The apparatus is coupled to receive an input video signal, and is combined with a format converter that adapts the vertical and horizontal formats of the input video signal in response to the format control signal, and a frame rate control signal. A frame rate converter, a format converter, and a frame rate converter for adapting a frame rate of the input video signal in response to the controller, and transmitting a format control signal and a frame rate control signal. In the case of an input video signal having a first value frame rate, the controller causes the frame rate converter to triple the input video frame rate and the format converter to perform the vertical and horizontal format of the input video signal. Is adapted to a format suitable for use in a display device.
[0012]
The content of the present invention can be easily understood by considering the following detailed description in conjunction with the accompanying drawings. The drawings are as follows.
[0013]
Detailed Description of Preferred Embodiments
The present invention has the advantages of US Provisional Patent No. 60/060112, filed September 26, 1997, which is hereby incorporated by reference in its entirety.
[0014]
The present invention will be described in the case of a digital television (DTV) receiver, such as an ATSC television receiver. However, it will be apparent to those skilled in the art that the present invention is applicable to any multiple format video processing system, including systems suitable for DVB, MPEG-1, MPEG-2 and other information streams.
[0015]
FIG. 1 shows a high level block diagram of a DTV receiver 100 according to the present invention. Specifically, the DTV receiver 100 includes a video processing portion and a timing portion. The video processing part includes a video decoder 120, an optional deinterlacer 130, a vertical resizer 140, a horizontal resizer 150, and a frame buffer 160. The timing portion includes a clock circuit 110, a raster generator 190, a display clock 195, a read address generator 180, and a write address generator 185. The video signal S2 processed in the video processing part is received by a DTV front end including an antenna 102, a tuner 104, a demodulator 106, and a transport demultiplexer 108. The processed video signal S8 is displayed on a display device 175 or the like (after appropriate color matrix processing) according to the horizontal and vertical timing signals H-DEF and V-DEF emitted by the raster generator 190.
[0016]
An RF source 102 (e.g., an antenna or cable television distribution network) is a radio frequency (e.g., comprising a plurality of television signals modulated in accordance with vestigial sideband (VSB), quadrature amplitude modulation (QAM) and other optimal modulation schemes. RF) A signal RF is supplied. The supplied RF television signal is combined with a tuner 104, which downconverts the requested television signal to produce a first intermediate frequency (IF) television signal IF. The demodulator 106, for example VSB or QAM, demodulates the IF television signal IF and generates a digital information stream S1. An example of a digital information stream S1 is a system stream S1 such as MPEG that includes one or more program transport streams such as MPEG.
[0017]
Program transport streams such as MPEG are similar to NTSC channels in that each program transport stream typically carries the audiovisual portion of a single program, such as a movie or other audiovisual program. Each program transport stream comprises a plurality of elementary streams associated with the audiovisual portion of the audiovisual program being carried.
[0018]
The transport demultiplexer 108 operates in a known manner and demultiplexes a specific program transport stream from a system stream S1, such as MPEG. The elementary audio stream S3 associated with the demultiplexed program transport stream is combined with the audio decoder 115 and decoded before being processed by an audio driver circuit (not shown). The basic video stream S2 associated with the demultiplexed program transport stream is combined with the video decoder 120.
[0019]
The transport demultiplexer 108 also includes a program clock reference (PCR) contained in what is called the adaptation field of the selected transport stream packet (reference packet) of the demultiplexed program transport stream. Extract. This PCR is a 27 MHz clock sample used to encode the demultiplexed program transport stream before delivering the program transport stream. The extracted PCR is combined with the clock circuit 110.
[0020]
The clock circuit 110 includes, for example, a phase lock loop (PLL) 112 and a voltage controlled oscillator (VCO) 114. The clock circuit 110 generates a system clock fSYS, a 27 MHz system clock suitable for processing information streams such as MPEG. The clock circuit 110 uses the PCR extracted from the demultiplexed program transport stream to convert the decoder system clock (that is, the system clock fSYS) of the DTV receiver into the demultiplexed program transport. Lock to the system clock of the encoder generating the port stream.
[0021]
The PLL 112 operates in a known manner and generates a control signal C1 in response to a comparison (for example) of the 27 MHz output of the VCO 114 and the PCR received from the transport demultiplexer 108. The VCO 114 is responsive to the control signal C1 and operates in a known manner to increase or decrease the frequency of the 27 MHz system clock fSYS.
[0022]
Video decoder 120 decodes video stream S2 in a standard manner and generates decoded video signal S4 having a constant transmission format and frame rate. Video decoder 120 examines the sequence header of video stream S2 to determine the format, colorimetric determination (if possible), and other information related to the video signal encoded in video stream S2. After examining the sequence header, the video decoder 140 combines the format, colorimetric, and other information with the output to produce a header data signal HD.
[0023]
Optional deinterlacer 130 receives at least the input of decoded video signal S4 and header data signal HD. If the decoded video signal S4 comprises video information having an interlace format (as indicated by the HD signal), the deinterlacer 130 converts the decoded video signal S4 into a progressive scan format video signal and combines it with the output to This is signal S5. If the decoded video signal S4 comprises video information having a progressive scan format, the deinterlacer 130 combines the decoded video signal S4 with the direct output to form the video signal S5. The deinterlacer 130 is implemented using, for example, a video adaptation approach that requires frame storage, a direct vertical interpolation, or a line iteration approach.
[0024]
The horizontal resizer 150 receives the video signal S5, and selectively changes the number of pixels (pixels) per line of video information included in the video signal S5 in response to the control signal HS from the controller 200. The horizontal resizer 150 generates a video signal S6 resized in the horizontal direction. The horizontal resizer 150 can increase the number of pixels per line using, for example, an interpolation technique that calculates the luminance and chrominance information of a new pixel inserted between two existing pixels. In addition, the horizontal resizer 150 can reduce the number of pixels per line by reducing all video lines by removing all Nth pixels included in the line, for example.
[0025]
The vertical resizer 140 receives the video signal S6 resized in the horizontal direction, and selectively selects the number of vertical scanning lines per frame of the video information included in the video signal S6 in response to the control signal VS from the controller 200. change. The vertical resizer 140 generates a video signal S7 resized in the vertical direction. The vertical resizer 140 can increase the number of lines per video frame using, for example, an interpolation technique that calculates the luminance and chrominance information of a new line inserted between the existing two lines. The vertical resizer 140 can also reduce the number of lines per video frame, for example, using an interpolation technique that calculates new scan lines at a reduced line density.
[0026]
If the optional deinterlacer 130 is implemented using the vertical interpolation or line iteration approach, the deinterlacing function can be incorporated into the vertical resizing unit 140. In this case, the horizontal resizer 150 is coupled to receive the decoded video signal S4 directly from the video decoder 120, as shown by the dotted line in FIG.
[0027]
The frame buffer 160 selectively receives the video signal S7 resized in the horizontal direction and the vertical direction. The frame buffer 160 is a double buffering type frame buffer, and includes an input frame store buffer 162 and an output frame store buffer 164. Video information in the video signal S7 is stored in the input frame store buffer 162 in response to the buffer input control signal IN. When the contents of output frame store buffer 164 are completely read, the contents of input frame store buffer 162 are used as output frame store buffer 164. That is, the input buffer and output buffer are functionally swapped to avoid the need to transfer the input buffer information to the output buffer. The video information stored in the output frame store buffer 164 is combined with the frame buffer output in response to the buffer output control signal OUT to become a buffered video signal S8. Since frame buffer 160 is a double buffering type frame buffer, output data is output frame store at a faster (or slower) rate than input data is stored in input frame store buffer 162. Can be fetched from buffer 164 That is, the clock frequency associated with video signal S7 need not be the same as the clock frequency associated with buffered video signal S8. In order to utilize 30 Hz video information on a 60 Hz display, each video frame is read from the output frame store buffer 164 twice before the next video frame enters the output frame store buffer 164. .
[0028]
The frame buffer 160 is preferably a double buffering device as shown in FIG. Although a single buffering device can be used, the single buffering device is prone to “tearing” defects in the display image when the buffer reading speed and the buffer writing speed are different. In the example embodiment, the buffer read speed (determined by the OUT signal) and the buffer write speed (determined by the IN signal) will be different, and for 24 Hz source video, the differences described below will occur. The use of low transmission frame rate video signals (such as 24 or 30 Hz) can cause a wide range of undesirable flicker in images displayed using most display technologies, necessitating these display rate conversions. Become.
[0029]
The RGB matrix and driver 170 receives the buffered video signal S8. The RGB matrix and driver 170 operates in a known manner and processes the buffered video signal S8 according to the matrix coefficients, transmission characteristics, and primary color information contained in the sequence header of the basic video stream S2. Specifically, the RGB matrix and driver 170 converts the transmitted Y, Cr, and Cb color components into red (R), green (G), and blue (B) color signals necessary for display. The color conversion process necessary for Three color signals R, G, B are combined with display device 175, where each color signal is used to drive, for example, an associated electron gun (not shown) in the picture tube. Note that the RGB matrix and the three color signals R, G, B emitted by the driver 170 need to be further amplified by an appropriate driver circuit (not shown) before being combined with the display device 175. May occur.
[0030]
The raster generator 190 generates a fixed frequency horizontal deflection signal H-DEF and a vertical deflection signal V-DEF in a conventional manner in response to the raster clock signal fRAST. The raster clock signal fRAST is transmitted by the display clock circuit 195 in a conventional manner. The horizontal and vertical deflection signals H-DEF, V-DEF are used, for example, to drive the associated horizontal and vertical deflection coils in the picture tube, respectively. It should be noted that the horizontal and vertical deflection signals H-DEF and V-DEF transmitted from the raster generator 190 need to be amplified by an appropriate driver circuit (not shown) before being combined with the display device 175. In some cases.
[0031]
The write address generator 180 generates a frame buffer input control signal IN in response to the control signal WRITE from the controller 200 and the clock signal fSYS. Similarly, the read address generator 185 generates a frame buffer output control signal OUT in response to the control signal READ from the controller 200 and the clock signal fRAST. Importantly, the video information of the video signal S7 is stored in the input frame store buffer 162 at a rate determined by the system clock fSYS. Similarly, video information in the output frame store buffer 164 is captured at a rate determined by the raster clock fRAST. Thus, for example, with a 27 MHz display clock (such as when selectively associated with the 27 MHz system clock fSYS) and an 81 MHz raster clock fRAST, the rate at which data is captured from the frame buffer 160 is three times the storage rate.
[0032]
The controller 200 can be implemented in a standard manner using a standard microprocessor, on-board memory unit, input / output ports and associated support circuitry. In addition, the controller 200 can include a special purpose digital signal processing circuit. The controller 200 receives the format, colorimetric determination, and other information regarding the decoded video signal S4 from the video decoder 120 through the header data signal HD. Using this information and additional information about the display device 175 (such as the native format of the display device), the controller 200 generates a vertical size control signal VS for the vertical resizer 140, a horizontal size control signal HS for the horizontal resizer 150, and a write address generation. A write address control signal WRITE is transmitted to the device 180 and a read address control signal READ is transmitted to the read address generator 185.
[0033]
In one embodiment of the present invention, all the processing and storage operations are performed using a 4: 2: 0 sampling (ie MPEG YUV) component format to minimize processing and storage conditions. .
[0034]
An ATSC receiver such as the DTV receiver 100 illustrated in FIG. 1 needs to process a video signal according to at least the ATSC recommended compression format. This format is shown in Table 1 below. In Table 1, “P” represents progressive scanning, and “I” represents interlaced scanning. Furthermore, the frame rate numbers shown in Table 1 are integer values. The ATSC standard also allows the frame rate value to be multiplied by 1000/1001 (ie 59.94 Hz instead of 670 Hz base).
[0035]
[Table 1]
In the DTV receiver of FIG. 1, the normal independent video format conversion and display rate conversion processes are controlled and coordinated according to the present invention. That is, the video format of the input video signal is controlled using the deinterlacer 130, the vertical resizer 140, and the horizontal resizer 150. Similarly, the display rate conversion process is controlled using a write address generator 180 and a read address generator 185. The controller 200 controls both processes and coordinates the use of the processes so that the image displayed on the display device 175 does not include video glitches due to the use of 24 Hz source data on a 60 Hz display device. To do.
[0036]
Therefore, in one embodiment of the DTV receiver 100 shown in FIG. 1, the display device 175 has one of the transmission formats (so-called native display format) at a frame refresh rate of 60 Hz (or 59.94 Hz). Operate with the horizontal deflection frequency selected to implement. Transmission video information having a field or frame rate of 60 Hz (or 59.94 Hz) is not subject to frame rate conversion. In contrast, transmitted video information having a frame rate of 30 Hz (or 29.97 Hz) is converted to 60 Hz (or 59.94 Hz) using 2: 1 frame repetition. That is, the controller 200 causes the output frame store buffer 164 of the frame buffer 600 to be read twice for each frame.
[0037]
Since the 24 Hz frame rate cannot be displayed on a 60 Hz (or 30 Hz) display device without causing undesirable video glitches due to the typical 3: 2 frame rate conversion process, the DTV receiver 100 of FIG. Operates differently when 24 Hz video is decoded. Specifically, 24Hz (or 24 * 1000 / 1001Hz) video is resized as needed in the format conversion process and eventually converted to 72Hz (or 72 * 1000 / 1001Hz) in the frame rate conversion process Is done. Display device 175 operates at a 72 Hz refresh rate when 24 Hz video is present. It should be noted that the format conversion process is adapted to the 72 Hz frame rate by the controller 200 as described below.
[0038]
Alternatively, 24 Hz (or 24 * 1000/1001 Hz) video is eventually converted to 48 Hz (or 48 * 1000/1001 Hz) video in the format conversion process, as needed in the format conversion process. When operating at 48 Hz, those skilled in the art using the present disclosure can adapt the various parameters associated with the implementation of the described 72 Hz method and apparatus to the 48 Hz method and apparatus. This 48 Hz operation may be desirable when the display device is a liquid crystal display device. It is important to note that the use of an integer multiple (3 for 72 Hz and 2 for 48 Hz) avoids the 3: 2 problem described here in the present invention.
[0039]
FIG. 2 is a high level block diagram of a DTV receiver including a light valve display according to the present invention. Since the DTV receiver 200 of FIG. 2 operates in much the same way as the DTV receiver 100 of FIG. 1, only the differences between the two figures will be described. Specifically, the DTV receiver 200 includes a display 175 including a projection display of, for example, a light valve or a digital micromirror display (DMD) type or a liquid crystal display (LCD) type. Therefore, the DTV receiver 200 of FIG. 2 does not include a circuit that transmits horizontal and vertical deflection signals. In this embodiment, the read address generator 185 switches to a 6/5 (ie, 72/60) higher frequency and provides a 72 Hz read of a double buffered frame display when a 24 Hz transmission format is present. . Note that the spatial format adjustment of the 24 Hz transmission format is usually not required for such displays.
[0040]
In the following description, it is assumed that display device 175 includes a cathode ray tube (CRT) display. In order to implement the present invention in a cost-effective manner in a CRT-based receiver, the horizontal deflection frequency of the CRT display should be kept constant, so that 5/6 of the number of scan lines (ie 60/72). ) Change is required. In order to change the number of scan lines, the controller 200 causes the vertical resizer 140 to reduce the number of lines of the video signal S5. In order to repeat the frame (2: 1 repetition), the controller 200 causes the output frame store buffer 164 to be read twice before receiving the next frame. Also, to repeat the frame twice (3: 1 repetition), the controller 200 causes the output frame store buffer 164 to be read three times before receiving the next frame.
[0041]
Table 2 shows a list of video transmission and display formats and processing parameters suitable for processing such video signals in the case of the DTV receiver 100. Specifically, this processing parameter is suitable for processing such video signals in the manner described above for display device 175, which is a 1920 pixel by 1080 line progressive scan display with a horizontal scan frequency of 64.8 kHz. Yes. Note that this display 175 operates in 900 line mode for 24 Hz source video.
[0042]
The vertical interpolation parameter (vertical interpolation), horizontal interpolation parameter (horizontal interpolation), and frame repetition parameter (frame repetition) are the vertical resizing coefficient, horizontal resizing coefficient, frame Each has a rate conversion coefficient. Controller 200 modifies these parameters to maintain a fixed horizontal display frequency and avoids problems with moving images in the case of 24 Hz source video, as previously described.
[0043]
[Table 2]
Table 3 shows the same type of information as in Table 2 above, but Table 3 shows the case of a display device 175 which is a progressive scan display of 1280 pixels × 720 lines with a horizontal scan frequency of 45 kHz.
[0044]
[Table 3]
Table 4 shows the same type of information as Tables 2 and 3 above, but Table 4 shows the case of a display device 175 which is a 1920 pixel by 1080 line interlaced scanning display with a horizontal scanning frequency of 32 kHz. Yes. Note that this display operates in 900 line mode for 24 Hz source video. The approach in 1920 × 1080 progressive scan (Table 2) is used, but with modifications appropriate to the fact that the display is interlaced.
[0045]
In this case, the highest speed de-interlacing is only required when running with 480 line format video, so the complexity and memory required for implementing the de-interlacer 130 can be greatly reduced. As a further note, the double frame buffer 160 can emit an interlaced scan format output signal S8.
[0046]
[Table 4]
Table 5 shows the same type of information as Tables 2-4 above, but in Table 5 for the display device 175, which is an interlaced scanning display of 1280 pixels by 720 lines with a horizontal scanning frequency of 22.5 kHz. Represents. Note that this display operates in 600 line mode for 24 Hz source video. The above approach in 1280 × 720 progressive scan (Table 3) is used, but with modifications appropriate to the fact that the display is interlaced. Also, as described with respect to Table 4, the complexity and required memory in the deinterlacer 130 can be significantly reduced and the read address generator circuit 185 must be modified.
[0047]
[Table 5]
In Tables 2 to 5, interpolation ratios such as 30/11, 20/11, and 15/11 occur several times. These ratios can be simplified to 3/1, 2/1 and 3/2, respectively, to reduce the complexity of interpolation. Such simplification naturally leads to a reduction of the active image range.
[0048]
FIG. 3 is a flowchart of a method 300 for processing a video signal in accordance with the present invention. Specifically, FIG. 3 is a flowchart illustrating a method for optimally formatting a video signal so that a 3: 2 pull-up failure does not propagate to a display device such as the display device 175 shown in FIGS. is there. The routine 300 of FIG. 3 can be implemented, for example, by hardware, software, a combination of hardware and software using the controller 200 of FIGS.
[0049]
The routine 300 of FIG. 3 begins at step 302 where an input video signal is received by either the DTV receiver of FIG. 1 or the DTV receiver 200 of FIG. In step 304, the format and frame rate of the video signal are identified and the routine continues to step 306. In step 306, an inquiry is made as to whether the received video signal is compatible with the native format of display device 175. If the answer to the question at step 306 is negative, the routine proceeds to step 308 to match the format of the video signal with the native format of the display device. Thereafter, the routine 300 proceeds to step 310. If the answer to the question at step 306 is affirmative, the routine 300 proceeds to step 310.
[0050]
In step 310, an inquiry is made as to whether the frame rate of the received video signal is approximately equal to 24 Hz (such as 24 Hz or 23.97 Hz). If the answer to the question at step 310 is negative, the routine 300 proceeds to step 312 where the frame rate of the received video signal is tripled. That is, in step 312, the controller 200 causes the frame rate converter to increase the frame rate of the input video signal from about 24 Hz to about 72 Hz. This method avoids the trouble caused by the 3: 2 pull-up normally associated with converting a video signal of 24 frames per second into a video signal of, for example, 30 Hz or 60 Hz frame rate.
[0051]
The embodiments of the present invention described so far present a method and apparatus for avoiding display animation defects due to 3: 2 conversion of 24 Hz video source video. There are other format-related functions that can be used to optimize this operation, such as a multiple video format DTV receiver. For example, a multi-format video signal processing system operating with a display device timing system that generates synchronized video and timing signals suitable for use in a fixed horizontal scan frequency display device is disclosed in US patent application filed on the same day as this application. No. 09/001952 (patent attorney number 12713), which is described in more detail in the present application as a reference. Another example is a video processing system that automatically adjusts video processor operations such as horizontal peaking, vertical peaking, and colorimetric parameters depending on the format of the received video signal, which is the same as this application. This is described in more detail in filed US patent application Ser. No. 09/001620 (patent attorney docket 12669), which is hereby incorporated by reference in its entirety.
[0052]
While various embodiments incorporating the subject matter of the present invention have been shown and described herein, those skilled in the art can readily devise many other various embodiments incorporating these subject matter.
[Brief description of the drawings]
FIG. 1 is a high level block diagram of a DTV receiver according to the present invention.
FIG. 2 is a high level block diagram of a DTV receiver including a light valve display according to the present invention.
FIG. 3 is a flowchart of a video signal processing method according to the present invention.

Claims (12)

An apparatus for processing an input digital video signal including a video image associated with at least one of a plurality of transmission display formats to generate an output video signal suitable for presentation on a display device,
Each of the transmission display formats has a corresponding horizontal size and a corresponding vertical size;
The display device is associated with a single predetermined frame rate,
A horizontal resizer (150) adapted to adapt a horizontal size of the input digital video signal in response to a first control signal to generate a digital video signal resized in the horizontal direction;
A vertical resizer (140) adapted to adapt a vertical size of the input digital video signal in response to a second control signal to generate a vertically resized digital video signal;
Depending on the third control signal, the horizontal direction and the frame rate of the resized digital video signal in the vertical direction to adapt under the horizontal scanning frequency of the fixed frame rate of the input digital video signal is 24Hz An adaptive frame rate equal to the single predetermined frame rate when the frame rate of the input digital video signal is three times the frame rate of the input digital video signal and the frame rate of the input digital video signal is not 24 Hz. A frame rate converter (160) for generating a frame rate adaptive digital video signal having:
A controller (200) for transmitting the first, second, and third control signals according to the transmission display format of the video image included in the input digital video signal,
Said controller, wherein the horizontal resizer, the horizontal size of the input digital video signal is set to adapt to the size there is the display device compatible,
The controller is configured to cause the vertical resizer to adapt the vertical size of the input digital video signal to a size compatible with the display device ;
When the frame rate of the input digital video signal is 24 Hz, the adapted vertical size of the input digital video signal is the vertical size of the input digital video signal when the frame rate of the input digital video signal is not 24 Hz. Equal to the product of the ratio of the single predetermined frame rate to the adaptive frame rate,
The controller is configured to cause the input frame buffer (162) to receive the resized digital video signal in the horizontal and vertical directions ;
The controller is configured to cause an output frame buffer (164) to generate the frame rate adaptive digital video signal (S8);
An apparatus wherein the controller is configured to swap the input frame buffer and the output frame buffer when the input frame buffer receives a complete frame. A deinterlacer (130) for converting the interlaced digital video signal into a progressive scan digital video signal;
The apparatus of claim 1, wherein the deinterlacer processes the digital video signal prior to the horizontal resizer, the vertical resizer, and the frame rate converter. The frame rate converter (160), said an input frame buffer (162), the input frame buffer, the digital video signal is resized to the horizontal and vertical directions in accordance with a first addressing rate The apparatus of claim 2 configured to receive.   4. The apparatus of claim 3, further comprising a display clock for providing a timing signal suitable for use in deriving horizontal and vertical deflection signals suitable for use in the display device.   The apparatus of claim 4, further comprising a raster generator in combination with the display clock for generating horizontal and vertical deflection signals suitable for use in the display device. The display device has a transmission display format of p pixels in h lines and a predetermined fixed line scan rate ,
The controller (200) causes the adaptive frame rate to be greater than or equal to the single predetermined frame rate;
The apparatus of claim 1, wherein the controller (200) causes the vertical resizer (140) to change the number of lines per frame of the digital video signal to be compatible with the fixed line scan rate. The number p of pixels per line of the display device is different from the number of pixels per line of the digital video signal,
The apparatus of claim 6, wherein the controller (200) causes the horizontal resizer to change the number of pixels per line of the digital video signal to be compatible with the number of pixels per line of the display device. The display device has a non-interlaced format;
The apparatus of claim 6 or 7, further comprising a deinterlacer (130) for a deinterlaced digital video signal having an interlaced format. 9. The relationship of the format of the digital video signal to the format of the digital signal when displayed on the display device is set in any of the following Tables 2, 3, 4, or 5. Any device.
  The apparatus according to any one of claims 1, 6, 7, and 8, wherein the integer is any one of 1, 2, and 3.   The apparatus of claim 1, wherein the display device comprises any one of a light valve, DMD, or LCD display device. A method of processing a digital video signal including a video image associated with at least one of a plurality of transmission display formats to produce an output video signal suitable for presentation on a display device, comprising:
Each of the transmission display formats has a corresponding horizontal size and a corresponding vertical size;
The display device is associated with a single predetermined frame rate,
A step in which the input adapts the horizontal size of the digital video signal to produce a digital video signal is resized in a horizontal direction is the display device compatible,
Adapting a vertical size of the input digital video signal to generate a vertically resized digital video signal compatible with the display device ;
Depending on the third control signal, the horizontal direction and the frame rate of the resized digital video signal in the vertical direction to adapt under the horizontal scanning frequency of the fixed frame rate of the input digital video signal is 24Hz An adaptive frame rate equal to the single predetermined frame rate when the frame rate of the input digital video signal is three times the frame rate of the input digital video signal and the frame rate of the input digital video signal is not 24 Hz. Generating a frame rate adaptive digital video signal having:
Storing the resized digital video signal in the horizontal and vertical directions in an input frame buffer;
Generating the frame rate adaptive digital video signal (S8) from an output frame buffer;
Swapping the input frame buffer and the output frame buffer when the input frame buffer receives a complete frame;
And when the input digital video signal has a frame rate of 24 Hz, the adapted vertical size of the input digital video signal is the input digital video signal when the frame rate of the input digital video signal is not 24 Hz. A vertical size equal to the product of the ratio of the single predetermined frame rate to the adaptive frame rate .