JP4584096B2 - Motor drive circuit - Google Patents

Description

  The present invention relates to a motor drive circuit having a redundant configuration in a computer unit or the like of an automobile electronic control system.

  2. Description of the Related Art Conventionally, for example, in an electronic control system for automobiles, a motor drive circuit of a computer unit has a redundant configuration, so that even if one motor drive circuit fails, the other motor drive circuit operates normally. The method is known. (For example, refer nonpatent literature 1).

  FIG. 4 is a diagram showing a conventional motor drive circuit employing a fully parallel redundant configuration. In FIG. 4, the motor drive circuit includes an A circuit 10 using the IG1 signal as a primary power supply and a B circuit 20 using the IG2 signal as a primary power supply. The IG1 signal is a signal that becomes High when the driver operates the IG (Ignition) switch and is in the “ON” position, and the IG2 signal is when the engine is in the starting (driving) state. It is a signal that becomes High.

  One A circuit 10 of the completely parallel system performs amplification at an A circuit power source 101 using IG1 as a primary power source, an A circuit CPU (Central Processing Unit) 102 that performs main control in the A circuit, and a stage before the motor driver. The A circuit pre-driver 103, a parallel FET (Field Effect Transistor) 104 that drives the motor 30, and an FET 105 are configured. The other B circuit 20 in the completely parallel system has the same configuration, and the motor 30 is energized by both the A circuit 10 and the B circuit 20.

The A circuit 10 and the B circuit 20 operate independently without interfering with each other, and during normal operation, the four FETs FET 104, FET 105, FET 204, and FET 205 function as final stage FETs that drive the motor 30. If any of the four FETs fails, the motor 30 is energized by the remaining FETs.
Hiroshi Shiomi, “Revised Third Edition, Introduction to Reliability Engineering”, Maruzen Co., Ltd., November 20, 1982, p. 106-120

  However, since the conventional motor drive circuit has a redundant configuration of a completely parallel system, the final stage FET requires two in each of the circuits of the completely parallel system, and a total of four FETs are required. . In the conventional configuration, since the motor can be driven as long as all four FETs do not fail, the FETs are not diagnosed.

Therefore, for example, diagnose a failure (which eventually causes the battery to run out) that does not turn off when the FET should originally be turned off due to a circuit failure but consumes battery power and continues to energize the motor. The power supply to the motor could not be stopped.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a low-cost and highly reliable motor drive circuit.

  In order to solve the above problems and achieve the object, the motor drive circuit of the present invention according to claim 1 inputs a drive signal (for example, input signals to the gates of the FET 7 and FET 8 in the embodiment). Driving means for driving the motor (for example, the FET 7 and FET 8 in the embodiment), a first control circuit for outputting the driving signal (for example, the main CPU 2 and the main pre-driver 3 in the embodiment), and the driving signal The second control circuit to output (for example, the backup CPU 4 and the backup pre-driver 5 in the embodiment), the first control circuit, or the second control circuit is selected and the drive signal is sent to the drive means. Switching means (for example, the switches Pri1-1, Pri1-2, Pri2-1 and Pri in the embodiment) -2), energization determining means for determining whether or not the motor is energized (for example, the main CPU 2 in the embodiment), and when the motor is driven, the first control circuit and the second The control circuit is energized to the motor, and when the energization determining means determines that either the first control circuit or the second control circuit is not energized, the other control circuit is Motor drive control circuit selection means (for example, processing of the main CPU 2 that performs the diagnosis shown in the timing chart of FIG. 2 in the embodiment) selected by the switching means.

  According to the motor drive circuit having the above-described configuration, the control circuit that inputs the drive signal to the drive means is always selected from the first control circuit and the second control circuit as the optimal control circuit for driving the motor, and the motor is reliably Can be driven.

  Furthermore, the motor drive circuit according to the present invention described in claim 2 is the motor drive circuit according to claim 1, wherein the motor drive control circuit selection means includes the first control circuit and the second control circuit. The motor is energized by shifting the output timing of both drive signals.

  Furthermore, the motor drive circuit of the present invention according to claim 3 is the motor drive circuit according to claim 1, wherein when the motor is not driven, the stop function by the first control circuit and the second control circuit. Motor stop control circuit selection means (for example, FIG. 3 in the embodiment) that selects the control circuit determined by the power supply determination means that the power supply to the motor is normally stopped by the switching means. The main CPU 2 performs the diagnosis shown in the timing chart of FIG.

  According to the motor drive circuit having the above-described configuration, it is possible to select an optimal control circuit from the first control circuit and the second control circuit when the motor is stopped, and to reliably stop energization of the motor.

  Furthermore, the motor drive circuit of the present invention described in claim 4 is the motor drive circuit according to claim 3, wherein the stop function by the first control circuit and the second control circuit in the motor stop control circuit selection means. The confirmation is performed by shifting the confirmation timing.

  According to the motor drive circuit of the present invention as set forth in claims 1 and 2, the control circuit for inputting a drive signal to the drive means is always optimal for driving the motor from the first control circuit and the second control circuit. It is possible to select an appropriate control circuit and drive the motor reliably. Therefore, it is not necessary to make the drive means redundant as in the prior art, and a low-cost and highly reliable motor drive circuit can be provided.

  Further, according to the motor drive circuit of the present invention described in claim 3 and claim 4, when the motor is stopped, the optimum control circuit is selected from the first control circuit and the second control circuit, and the motor drive circuit is surely supplied. Therefore, it is possible to further improve the reliability by preventing the failure that the power is continuously supplied even when the motor is stopped.

A motor drive circuit according to an embodiment of the present invention will be described below with reference to FIGS.
FIG. 1 is a block diagram showing a configuration of a motor drive circuit according to an embodiment of the present invention. The first control circuit described in the claims refers to the main CPU 2 and the main pre-driver 3 in FIG. 1, and the second control circuit refers to the backup CPU 4 and the backup pre-driver 5 in FIG.

  In FIG. 1, a monitoring IC 1 is an IC (Integrated Circuit) that diagnoses the main CPU 2 and supplies power to the main CPU 2 and the main pre-driver 3. The main CPU 2 diagnoses the monitoring IC 1 and instructs the main pre-driver 3 to output a drive signal. The main pre-driver 3 inputs an instruction from the main CPU 2 from the DRI2 terminal, and outputs a drive signal from the DRO2a terminal and the DRO2b terminal according to the instruction. The main pre-driver 3 can output drive signals separately from the DRO2a terminal and the DRO2b terminal, or can simultaneously output drive signals from both.

  The drive signal output from the DRO2a terminal is input to the gate of the final stage FET 7 via the switch Pri1-1 and the diode D1. On the other hand, the drive signal output from the DRO2b terminal is input to the gate of the final-stage FET 8 via the switch Pri1-2 and the diode D2.

  Further, when the main CPU 2 outputs a drive signal from the backup pre-driver 5, the main CPU 2 outputs a MOT_req signal from the MOT_req_out terminal. When the backup CPU 4 inputs the MOT_req signal from the main CPU 2 from the MOT_req_in terminal, the backup CPU 4 instructs the backup pre-driver 5 to output a drive signal from the OUT1 terminal and the OUT2 terminal.

  The backup pre-driver 5 inputs an instruction from the backup CPU 4 at the IN1 terminal and the IN2 terminal, and outputs a drive signal from the VGS1 terminal and the VGS2 terminal according to the instruction.

  The drive signal output from the VGS1 terminal is input to the gate of the final stage FET 7 via the switch Pri2-1 and the diode D3. On the other hand, the drive signal output from the VGS2 terminal is input to the gate of the final stage FET 8 via the switch Pri2-2 and the diode D4.

  The main CPU 2 monitors the voltage at the point X in FIG. 1 at the MCK terminal (energization determining means). When the FET 7 or FET 8 is turned on by the input of each drive signal described above, the voltage at the point X becomes a high level voltage, and it can be confirmed by the main CPU 2 that the motor 9 is energized. On the other hand, when both FET 7 and FET 8 are turned OFF, the voltage at the point X becomes Low, and it can be confirmed by the main CPU 2 that the motor 9 is not energized.

Next, a procedure for switching the switches Pri1-1, Pri1-2, Pri2-1 and Pri2-2 will be described.
One of the two input terminals of the OR circuit 6 is connected to the inh1 terminal and the inh2 terminal of the monitoring IC 1, and the other input terminal is connected to the inh3 terminal of the main CPU 2.

  When the monitoring IC 1 diagnoses that the main CPU 2 is not operating normally, it sets the inh1 terminal and the inh2 terminal to High and outputs them. Here, since two terminals of the inh1 terminal and the inh2 terminal are used, even if the connection between one of the terminals and the OR circuit 6 is cut off, the other terminal can be input to the OR circuit 6 as usual. .

  On the other hand, when it is necessary to select a drive signal from the backup pre-driver 5, the main CPU 2 sets the inh3 terminal to High and outputs it (hereinafter, the output of the inh3 terminal is referred to as a pseudo inh signal). The OR circuit 6 outputs High when any of the inh1 terminal, inh2 terminal, and inh3 terminal is High, and outputs Low when all the terminals are Low.

  An output of the OR circuit 6 (hereinafter referred to as an inh signal) is branched into two, one of which is a switching signal for the switches Pri1-1 and Pri1-2 via the NOT circuit 5, and the other is a direct switch Pri2-1. And Pri2-2 switching signal.

  The switches Pri1-1, Pri1-2, Pri2-1, and Pri2-2 are switches that are turned on when the switching signal is at a high level and turned off when the switching signal is at a low level. Therefore, when the inh signal is low, the switches Pri1-1 and Pri1-2 are turned on, the switches Pri2-1 and Pri2-2 are turned off, and the drive signal from the main pre-driver 3 is selected and output to the FET7 and FET8. The

  On the other hand, when the inh signal is high, the switches Pri1-1 and Pri1-2 are turned off and the switches Pri2-1 and Pri2-2 are turned on, and the drive signal from the backup pre-driver 5 is selected and output to the FET7 and FET8. Is done.

  That is, by the above four switches, the drive signal from the backup pre-driver 5 is selected when any of the inh1, inh2, and inh3 terminals is High, and the drive from the main pre-driver 3 is performed only when all the terminals are Low. A signal is selected.

  Next, a diagnostic test performed before starting the drive control of the motor 9 will be described with reference to the timing chart of FIG. In the present embodiment, the main CPU 2 energizes the motor 9 for diagnosis of the motor drive circuit for a short time before starting drive control of the motor 9.

  In FIG. 2, (1) and (2) show the logic of the VGS1 terminal and the VGS2 terminal which are output terminals of the backup pre-driver 5. (3) and (4) show the logic of the DRO2a terminal and the DRO2b terminal which are output terminals of the main pre-driver 3.

  (5) shows the logic of the pseudo inh signal output from the inh3 terminal of the main CPU2. (6) shows the expected value of logic at the MCK terminal when the motor drive circuit of FIG. 1 is operating normally when each terminal is in the state shown in (1) to (5).

  At the time of ON test 1 shown in FIG. 2, both outputs of the backup predriver 5 are High, both outputs of the main predriver 3 are Low, and the pseudo inh signal is High, and the output on the backup predriver 5 side is selected. ing. At this time, if the path from the backup pre-driver 3 to the FETs 7 and 8 is normal, High is detected at the MCK terminal.

  At the time of the ON test 2, both the output terminals of the backup pre-driver 5 and the DRO 2b terminal of the main pre-driver 3 are Low, the DRO 2a terminal of the main pre-driver 3 is High, and the pseudo inh signal is Low, and the output on the main pre-driver 3 side is low. Is selected. At this time, if the path from the DRO2a terminal of the main pre-driver 3 to the FET 7 is normal, High is detected at the MCK terminal.

  At the time of the ON test 3, both the output terminals of the backup predriver 5 and the DRO2a terminal of the main predriver 3 are Low, the DRO2b terminal of the main predriver 3 is High, and the pseudo inh signal is Low, and the output on the main predriver 3 side is low. Is selected. At this time, if the path from the DRO2b terminal of the main pre-driver 3 to the FET 8 is normal, High is detected at the MCK terminal.

  That is, if the result of the ON test 1 is as expected, it can be determined that at least one of the paths from the backup pre-driver 5 to the FET 7 or FET 8 is normal. Similarly, if the result of the ON test 2 is as expected, the path from the DRO2a terminal of the main predriver 3 to the FET 7 is normal, and if the result of the ON test 3 is as expected, the DRO2b of the main predriver 3 It can be determined that the path from the terminal to the FET 8 is normal.

  (7) to (10) show logical values of the MCK terminal when an abnormality is confirmed in the ON tests 1 to 3. In (7), only the result of the ON test 1 is different from the normal expected value, and it is determined that there is an abnormality in the path from the backup pre-driver 5 to the FET 7 and FET 8.

  In this case, when the motor is driven after diagnosis, the main CPU 2 sets the pseudo inh signal to Low and uses both the DRO2a terminal and the DRO2b terminal of the main pre-driver 3 so that the FET7 and FET8 are chopped by PWM (Pulse Width Modulation). To drive.

  In (8), only the result of the ON test 2 is different from the normal expected value, and it is determined that there is an abnormality in the path from the DRO2a terminal of the main pre-driver 3 to the FET 7. In this case, when the motor is driven after diagnosis, the main CPU 2 sets the pseudo inh signal to Low and drives the FET 8 using only the DRO2b terminal of the main pre-driver 3.

  However, unlike (7), the motor 9 is driven by a single FET 8, so ON / OFF switching occurs frequently, and not linearly driven by DC (Direct Current) current instead of a strict thermal chopping method. Use the method.

  In (9), only the result of the ON test 3 is different from the normal expected value, and it is determined that there is an abnormality in the path from the DRO2b terminal of the main pre-driver 3 to the FET 8. In this case, when the motor is driven after diagnosis, the main CPU 2 sets the pseudo inh signal to Low, and drives the FET 7 by the linear drive method using only the DRO2a terminal of the main pre-driver 3.

  In (10), the results of the ON test 2 and the ON test 3 are different from the expected values at the normal time, and it is determined that there is an abnormality in the path from the main pre-driver 3 to the FET 7 and FET 8. In this case, when the motor is driven after diagnosis, the main CPU 2 sets the pseudo inh signal to High, and drives the FET 7 and FET 8 using both the VGS1 terminal and the VGS2 terminal of the backup predriver 5.

  In addition, since it cannot be confirmed from the result of the ON test 1 whether both paths from the VGS1 terminal and the VGS2 terminal are normal, a linear drive system capable of driving the motor 9 without any problem with only one of the FET7 and the FET8 is used. Use.

  As described above, the diagnosis of the ON test 1 to the ON test 3 is performed before the motor 9 is driven, so that even if a failure occurs in a part of the circuit that drives the two FETs 7 and 8 in the final stage, it is normal. In addition, it is possible to appropriately select a path capable of driving the motor 9. Therefore, a highly reliable motor drive circuit can be provided without making the final stage FET redundant.

  Next, a diagnostic test performed when the drive control of the motor 9 is finished will be described with reference to the timing chart of FIG. In this embodiment, when the drive control of the motor 9 is stopped, it is tested whether or not the motor 9 is continuously energized.

  In FIG. 3, (1) and (2) show the logic of the DRO2a terminal and the DRO2b terminal which are output terminals of the main pre-driver 3. (3) and (4) show the logic of the VGS1 terminal and the VGS2 terminal which are the output terminals of the backup pre-driver 5.

  (5) shows the logic of the pseudo inh signal output from the inh3 terminal of the main CPU2. (6) shows the expected value of logic at the MCK terminal when the motor drive circuit of FIG. 1 is operating normally when each terminal is in the state shown in (1) to (5).

  At the time of the OFF test 1 shown in FIG. 3, both outputs of the main pre-driver 3 are Low, both outputs of the backup pre-driver 5 are Low, and the pseudo inh signal is Low and the output on the main pre-driver 3 side is selected. Yes. At this time, if the path from the main pre-driver 3 to the FETs 7 and 8 is normal, Low is detected at the MCK terminal.

  At the time of the OFF test 2, both outputs of the main pre-driver 3 are Low, both outputs of the backup pre-driver 5 are Low, and the pseudo inh signal is High, and the output on the backup pre-driver 5 side is selected. At this time, if the path from the backup pre-driver 5 to the FETs 7 and 8 is normal, Low is detected at the MCK terminal.

  At the time of the OFF test 3, both outputs of the main predriver 3 are Low, both outputs of the backup predriver 5 are High, and the pseudo inh signal is Low, and the output on the main predriver 3 side is selected. At this time, if the path from the main pre-driver 3 to the FETs 7 and 8 is normal, Low is detected at the MCK terminal.

  At the time of the OFF test 4, both outputs of the main pre-driver 3 are High, both outputs of the backup pre-driver 5 are Low, and the pseudo inh signal is High, and the output on the backup pre-driver 5 side is selected. At this time, if the path from the backup pre-driver 5 to the FETs 7 and 8 is normal, Low is detected at the MCK terminal.

  (7) to (10) show logical values of the MCK terminal when an abnormality is confirmed in the OFF tests 1 to 4. In (7), only the result of the OFF test 1 matches the expected value at the normal time. In this case, when the motor is stopped after diagnosis, the main CPU 2 selects to stop in the OFF test 1 state. In 8), only the result of the OFF test 2 coincides with the expected value at the normal time. In this case, when the motor is stopped after the diagnosis, the main CPU 2 selects to stop in the OFF test 2 state.

  In (9), only the result of the OFF test 3 matches the expected value at the normal time. In this case, when the motor is stopped after diagnosis, the main CPU 2 selects to stop in the state of the OFF test 3. In (10), only the result of the OFF test 4 matches the expected value at the normal time. In this case, the main CPU 2 selects to stop in the state of the OFF test 4 when the motor is stopped after the diagnosis.

  As described above, the main CPU 2 performs a test of the motor drive circuit while stopping the driving of the motor, and selects to stop in a state determined to be normal in the OFF tests 1 to 4. Even if a failure occurs in a part of the circuit that drives the two FETs 7 and 8 in the final stage, it is possible to prevent the FET 9 and the FET 8 from being always turned off and continuing to energize the motor 9.

  As described above, in this embodiment, the motor drive circuit for driving the motor has a redundant configuration, and it is possible to select an optimum path (circuit) before driving the motor. Further, when the motor is stopped, the motor is energized. It is possible to select the state to stop.

  Therefore, it is possible to provide a low-cost and highly reliable motor drive circuit without using a redundant configuration up to the final stage FET as a completely parallel redundant system as in the prior art. Furthermore, it is possible to prevent a dark current from flowing from the battery while the motor is stopped, and to prevent the battery from running out.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.

  The present invention is suitable for use in a redundant motor drive circuit in a computer unit of an automotive electronic control system.

It is a block diagram which shows the structure of the motor drive circuit concerning one Embodiment of this invention. It is a timing chart of the test which determines whether motor energization is performed at the start of motor drive control. It is a timing chart of the test which determines the motor energization stop performed while the motor drive is stopped. It is a block diagram which shows the structure of the redundant structure motor drive circuit of a complete parallel system in a prior art.

Explanation of symbols

1 ... Monitoring IC
2 ... Main CPU (energization determination means)
3 ... Main pre-driver 4 ... Backup CPU
5 ... Backup pre-driver 7, 8 ... FET (drive means)
9 ... Motors Pri1-1, Pri1-2, Pri2-1, Pri2-2 ... Switches (switching means)

Claims (3)

Driving means for inputting a driving signal and driving the motor;
A first control circuit for outputting the drive signal;
A second control circuit for outputting the drive signal;
Switching means for selecting either the first control circuit or the second control circuit and outputting the drive signal to the drive means;
Energization determining means for determining whether the motor is energized;
When the motor is driven, the motor is energized from the first control circuit and the second control circuit, and the energization determining means energizes either the first control circuit or the second control circuit. Motor drive control circuit selection means for selecting the other control circuit with the switching means when it is determined that the control circuit is not performed ;
When the motor is not driven, the stop function is confirmed by the first control circuit and the second control circuit, and the control for determining that the power supply to the motor is normally stopped by the power supply determination means Motor stop control circuit selection means for selecting a circuit by the switching means;
A motor drive circuit comprising:   2. The power supply to the motor from the first control circuit and the second control circuit in the motor drive control circuit selection unit is performed by shifting the output timing of both drive signals. Motor drive circuit. 3. The confirmation of the stop function by the first control circuit and the second control circuit in the motor stop control circuit selection unit is performed by shifting the confirmation timing. Motor drive circuit.

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