JP4574261B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having an inverted staggered thin film transistor having a crystalline semiconductor film.

  In recent years, a flat panel display (FPD) typified by a liquid crystal display (LCD) or an EL display has attracted attention as a display device that replaces a conventional CRT. In particular, the development of large-screen liquid crystal televisions equipped with large liquid crystal panels driven by an active matrix has become an important issue for LCD panel manufacturers to focus on. In recent years, a large screen EL television has been developed following the liquid crystal television.

  In a conventional liquid crystal device or EL display device (hereinafter referred to as a light emitting display device), a thin film transistor (hereinafter referred to as TFT) using amorphous silicon is used as a semiconductor element for driving each pixel.

  On the other hand, in the conventional liquid crystal television, the blur of the image due to the limitation of the viewing angle characteristic and the limitation of the high-speed operation due to the liquid crystal material and the like has been a defect. In recent years, the OCB mode is a new display mode that solves this. It has been proposed (Non-Patent Document 1).

Nagahiro Yasuaki et al., “Nikkei Microdevices separate volume flat panel display 2002”, Nikkei BP, October 2001, P102-109

  However, when a TFT using an amorphous semiconductor film is DC-driven, the threshold value tends to shift and TFT characteristic variation tends to occur accordingly. For this reason, luminance unevenness occurs in a light-emitting display device in which a TFT using an amorphous semiconductor film is used for pixel switching. Such a phenomenon becomes more conspicuous as a large screen TV having a diagonal of 30 inches or more (typically 40 inches or more), and the deterioration of image quality is a serious problem.

  On the other hand, there is a need for a switching element that can operate at high speed in order to improve the image quality of the LCD. However, a TFT using an amorphous semiconductor film has a limit. For example, it is difficult to realize an OCB mode liquid crystal display device.

  The present invention has been made in view of such a situation, and provides a method for manufacturing a semiconductor device having a TFT with a small number of photomasks that is unlikely to cause a threshold shift and can operate at high speed. In addition, a method for manufacturing a semiconductor device which can display with high switching characteristics and excellent contrast is provided.

  The gist of the present invention is to form a crystalline semiconductor film by adding a catalytic element to an amorphous semiconductor film and heating it, and then forming an inverted staggered TFT after removing the catalytic element from the crystalline semiconductor film. To do.

Further, a catalytic element is added to the amorphous semiconductor film and heated to form a crystalline semiconductor film, and the crystalline semiconductor film includes a semiconductor film having a Group 5 element (Group 15 element) or a semiconductor film having a rare gas element. After forming and heating to remove the catalytic element from the crystalline semiconductor film, the gist is to form an inverted staggered TFT. Note that in the case where a semiconductor film including a Group 5 element (Group 15 element) is formed in the crystalline semiconductor film, a semiconductor film including a Group 5 element (Group 15 element) is used as a source region and a drain region, so that an n-channel type is formed. A TFT is formed. Further, a p-channel TFT is formed by adding a group 3 element (group 13 element) to a semiconductor film having a group 5 element (group 15 element).
Further, when a semiconductor film containing a rare gas element is formed, the semiconductor film containing the rare gas element is removed after heating, and a source region and a drain region are formed, so that an n-channel TFT or a p-channel TFT is formed. To do.

  According to another aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region catalytic element is formed. After adding and heating to form a second semiconductor region having an impurity element over the first semiconductor region, the first semiconductor region and the second semiconductor region are heated, and the second semiconductor region is etched. In this method, a source region and a drain region are formed, and a source electrode and a drain electrode in contact with the source region and the drain region are formed.

  According to another aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region catalytic element is formed. After adding and heating to form a second semiconductor region having an impurity element over the first semiconductor region, the first semiconductor region and the second semiconductor region are heated and the source is in contact with the second semiconductor region In this method, a source region and a drain region are formed by etching an exposed portion of a heated second semiconductor region after forming an electrode and a drain electrode.

  The impurity element is an element selected from phosphorus, nitrogen, arsenic, antimony, and bismuth.

  According to another embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and a catalytic element is formed in the first semiconductor region. Is added and heated to form a second semiconductor region having the first impurity element over the first semiconductor region, and then the first semiconductor region and the second semiconductor region are heated to form a second semiconductor region Is formed, a source region and a drain region having a second impurity element are formed in contact with the first semiconductor region, and a source electrode and a drain electrode in contact with the source region and the drain region are formed. .

  According to another aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region catalytic element is formed. After adding and heating to form a second semiconductor region having an impurity element over the first semiconductor region, the first semiconductor region and the second semiconductor region are heated, and the source electrode in contact with the second semiconductor region Then, after forming the drain electrode and the drain electrode, the exposed portion of the second semiconductor region is etched to form a source region and a drain region.

  Note that the first impurity element is one or more selected from He, Ne, Ar, Kr, and Xe, and the second impurity element is one or more selected from phosphorus, nitrogen, arsenic, antimony, and bismuth. It is a seed.

  According to another aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region catalytic element is formed. After adding and heating to form a second semiconductor region and a third semiconductor region having the first impurity element over the first semiconductor region, the first semiconductor region to the third semiconductor region are heated. Covering the second semiconductor region with the first mask and covering a part of the third semiconductor region with the second mask and adding a second impurity element; and a part of the second semiconductor region; and In this method, a region covered with a mask of a second semiconductor region is etched to form a source region and a drain region, and a source electrode and a drain electrode in contact with the source region and the drain region are formed.

  According to another aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region catalytic element is formed. After adding and heating to form a second semiconductor region and a third semiconductor region having the first impurity element over the first semiconductor region, the first semiconductor region to the third semiconductor region are heated. The second semiconductor region is covered with a first mask, and a part of the third semiconductor region is covered with the second mask, and a second impurity element is added, and the source electrode is in contact with the second semiconductor region And the source electrode and the drain electrode in contact with the third semiconductor region to which the second impurity element is added and the exposed portion of the second semiconductor region and the second impurity element are added. Etch the exposed part of the third semiconductor region A method for manufacturing a semiconductor device for forming a source region and a drain region grayed.

    According to one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region and a second semiconductor region are formed over the gate insulating film, The first semiconductor region is added and heated to form a first mask that covers each of the first semiconductor region and the second semiconductor region, and then the first impurity element is added and heated to form the first semiconductor. A second mask covering the region and a third mask covering a part of the second semiconductor region are formed; a second impurity element is added to the second region; and the first mask of the first semiconductor region This is a method for manufacturing a semiconductor device in which first and second source and drain electrodes are formed in contact with a region to which an impurity element is added and a region to which a second impurity element is added in a semiconductor region, respectively.

  According to one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region and a second semiconductor region are formed over the gate insulating film, A catalytic element is added to the semiconductor region and the second semiconductor region and heated to form a third semiconductor region having a rare gas element over the first semiconductor region, and the first to third semiconductor regions are formed. After heating, the third semiconductor region is removed, a first impurity element is added to the first semiconductor region, a second impurity element is added to the second semiconductor region, and the first semiconductor region This is a method for manufacturing a semiconductor device in which first and second source and drain electrodes are formed in contact with a region to which a first impurity element is added and a region to which a second impurity element is added in a semiconductor region, respectively.

    According to one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region and a second semiconductor region are formed over the gate insulating film, The third semiconductor region and the fourth semiconductor region having the first impurity element on the first semiconductor region and the second semiconductor region are heated by adding a catalyst element to the semiconductor region and the second semiconductor region. And heating, adding a second impurity element to the fourth semiconductor region, and etching the third semiconductor region and the fourth semiconductor region to form first and second source regions and drain regions. And a method of manufacturing a semiconductor device in which first and second source electrodes and drains in contact with the first and second source regions and the drain region, respectively, are formed.

    According to one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region and a second semiconductor region are formed over the gate insulating film, A catalytic element is added to the semiconductor region and the second semiconductor region and heated, and a third semiconductor region and a fourth semiconductor region having the first impurity element are formed on the first semiconductor region and the second semiconductor region. Forming and heating; adding a second impurity element to the fourth semiconductor region; and a first source electrode and a drain electrode in contact with the third semiconductor region; a second source electrode in contact with the fourth semiconductor region; In this method, the drain electrode is formed and then the exposed portions of the third semiconductor region and the fourth semiconductor region are etched to form the first and second source regions and the drain region.

    Note that the first impurity element is one or more selected from phosphorus, nitrogen, arsenic, antimony, and bismuth, and the second impurity element is boron.

    The catalytic element is one or more selected from botungsten, molybdenum, zirconia, hafnium, bismuth, niobium, tantalum, chromium, cobalt, nickel, and platinum.

  Another embodiment of the present invention is a liquid crystal television or an EL television including the semiconductor device.

  In the present invention, examples of the semiconductor device include an integrated circuit including a semiconductor element, a display device, a wireless tag, and an IC tag. Typical examples of the display device include a liquid crystal display device, a light emitting display device, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display). And display devices such as electrophoretic display devices (electronic paper).

  In the present invention, the display device refers to a device using a display element, that is, an image display device. In addition, a connector, for example, a module in which a flexible printed wiring (FPC), TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) is attached to the display panel, a printed wiring board at the end of the TAB tape or TCP is provided. It is assumed that the display device includes all provided modules or modules in which an IC (Integrated Circuit) or a CPU is directly mounted on a display element by a COG (Chip On Glass) method.

  According to the present invention, an inverted staggered TFT having a crystalline semiconductor film can be formed. Therefore, a TFT can be formed with a small number of masks. In addition, since the TFT formed according to the present invention is formed using a crystalline semiconductor film, it has higher mobility than an inverted staggered TFT formed using an amorphous semiconductor film. In addition, the source region and the drain region include a catalyst element in addition to the acceptor element or the donor element. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured. Typically, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, in comparison with an EL display device using a TFT formed of an amorphous semiconductor film as a switching element, display unevenness can be reduced and a highly reliable semiconductor device can be manufactured. It is.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. For this reason, it is possible to improve contrast by providing such a TFT in a switching element of a display device, for example, a liquid crystal display device.

  Further, a liquid crystal television and an EL television each including the semiconductor device formed by the above manufacturing process can be manufactured with high throughput and yield at low cost.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a manufacturing process of an inverted staggered TFT having a crystalline semiconductor film is described with reference to FIGS.

  As shown in FIG. 1A, a first conductive layer 102 is formed over a substrate 101, and a first insulating film 103 and a second insulating film 104 are formed over the first conductive layer. Next, a first semiconductor film 105 is formed over the second insulating film 104, and a catalytic element layer is formed over the first semiconductor film 105.

  As the substrate 101, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as ceramic such as alumina, a silicon wafer, a metal plate, or the like can be used. Further, as the substrate 101, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm can be used.

  The first conductive layer 102 can be formed by forming a first conductive film, forming a mask over the second conductive film by a photolithography process, and etching using the mask. preferable. The first conductive film is preferably formed using a high melting point material by a known method such as a printing method, an electroplating method, a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), or an evaporation method. By using a high melting point material, a later heating step is possible. High melting point materials include tungsten (W), molybdenum (Mo), zirconia (Zr), hafnium (Hf), bismuth (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co) A metal such as nickel (Ni) or platinum (Pt), an alloy thereof, or a metal nitride thereof can be used as appropriate. Further, a plurality of these layers may be stacked. Typically, a tantalum nitride film may be stacked on the substrate surface, and a tungsten film may be stacked thereon. In addition, LRTA (Lamp Rapid Thermal Anneal) method in which the subsequent heating process is performed by radiation from one or more kinds selected from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. When using a GRTA (Gas Rapid Thermal Anneal) method using an inert gas such as nitrogen or argon as a heating medium, aluminum (Al), silver (Ag), and gold (Cu ) May be used to form the first conductive film.

  The first insulating film 103 and the second insulating film 104 function as a gate insulating film. The first insulating film 103 and the second insulating film include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like. Can be used as appropriate. Further, the first conductive layer 102 may be anodized to form an anodized film instead of the first insulating layer. Note that in order to prevent diffusion of impurities and the like from the substrate side, the first insulating film 103 is preferably formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), or the like. In addition, the second insulating film may be formed using silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) because of interface characteristics with the first semiconductor film 105 to be formed later. desirable. However, the present invention is not limited to this step, and it is formed of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like. It may be formed of a single layer. Note that the second insulating film contains hydrogen.

  As the first semiconductor film 105, an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed (also referred to as SAS), and crystal grains of 0.5 nm to 20 nm are formed in the amorphous semiconductor. A film having any state selected from a microcrystalline semiconductor and a crystalline semiconductor that can be observed is formed. In particular, a microcrystalline state in which grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal (μc). In any case, a semiconductor film having silicon, silicon germanium (SiGe), or the like as a main component can be used in a thickness of 10 to 200 nm, preferably 50 to 100 nm.

Note that in order to obtain a semiconductor film having a high-quality crystal structure by subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the first semiconductor film 105 is set to 5 × 10 ¹⁸ / cm ³ (hereinafter referred to as “the semiconductor film”). All concentrations are shown as atomic concentrations measured by secondary ion mass spectrometry (SIMS). These impurities are likely to react with the catalytic element, hinder subsequent crystallization, and increase the density of capture centers and recombination centers even after crystallization.

  As a method for forming the layer 105 having a catalytic element, a thin film of a catalytic element or a silicide of the catalytic element is formed on the surface of the semiconductor film 105 by a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), a vapor deposition method, or the like. And a method of applying a solution containing a catalytic element to the surface of the semiconductor film 105. As catalyst elements, tungsten (W), molybdenum (Mo), zirconia (Zr), hafnium (Hf), bismuth (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), It can be formed using one or more of nickel (Ni), platinum (Pt), and the like. Further, the catalyst element may be directly added to the semiconductor film by an ion doping method or an ion implantation method. Further, the surface of the semiconductor film may be subjected to plasma treatment using an electrode formed of the above catalytic element. Here, the catalytic element is an element that promotes or promotes crystallization of the semiconductor film.

  Next, the first semiconductor film is heated to form a first crystalline semiconductor film 111 as shown in FIG. In this case, in crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Here, after the heat treatment for dehydrogenation, heat treatment for crystallization (at 550 ° C. to 650 ° C. for 4 to 24 hours) is performed. Further, crystallization may be performed by RTA or GRTA. Here, by performing crystallization without laser light irradiation for heating, variation in crystallinity can be reduced, and variation in TFTs to be formed later can be suppressed.

Next, a channel doping process for adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the TFT is performed entirely or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron is added by an ion doping method in which plasma excited without mass separation of diborane (B ₂ H _6). Note that an ion implantation method in which mass separation is performed may be used. Note that the channel doping step may be performed before the crystallization step.

Next, a second semiconductor film 112 containing a Group 3 element (Group 13 element, hereinafter referred to as a donor-type element) is formed over the first crystalline semiconductor film 111. The film may be formed by a plasma CVD method in which a gas containing a donor element such as phosphorus or arsenic is added to a silicide gas. By forming the second semiconductor film by such a method, an interface between the first crystalline semiconductor film and the second semiconductor film is formed. In addition, the second semiconductor film 112 containing a donor-type element is formed by forming a semiconductor film similar to the first semiconductor film and then adding the donor-type element by an ion doping method or an ion implantation method. Can do. In this case, the second semiconductor film 112 preferably has a phosphorus concentration of 1 × 10 ^{19 to} 3 × 10 ²¹ / cm ³ .

  FIG. 9 shows the impurity profile of the second semiconductor film containing the donor element at this time. FIG. 9A shows a donor-type element profile 140a when a second semiconductor film containing a donor-type element is formed on the first crystalline semiconductor film 111 by a plasma CVD method. A donor-type element having a constant concentration is distributed in the depth direction of the film.

On the other hand, FIG. 9B illustrates a case where a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed over the first crystalline semiconductor film 111. A donor-type element profile 140b is shown when a second semiconductor film is formed by forming and adding a donor-type element to the semiconductor film by ion doping or ion implantation. As shown in FIG. 9B, the donor-type element concentration is relatively high in the vicinity of the surface of the second semiconductor film. A region having a donor element concentration of 1 × 10 ¹⁹ / cm ³ or more is referred to as an n + region 134a. On the other hand, as the first crystalline semiconductor film 131 is approached, the donor-type element concentration is relatively decreased. A region having a donor element concentration of 5 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ is referred to as an n-region 134b. The n + region 134a functions as a source region and a drain region later, and the n− region 134b functions as an LDD region. Note that there is no interface between the n + region and the n− region, and the interface varies depending on the relative donor type element concentration. As described above, the second semiconductor film containing the donor element formed by the ion doping method or the ion implantation method can control the concentration profile depending on the addition conditions, and the film thicknesses of the n + region and the n− region. Can be appropriately controlled.

Next, the first crystalline semiconductor film 111 and the second semiconductor film 122 are heated, and the catalyst element contained in the first crystalline semiconductor film 111 is added to the first crystalline semiconductor film 111 as indicated by an arrow in FIG. The catalyst element is moved to the second semiconductor film 122 to getter the catalyst element. By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 10 ¹⁷ / cm ^3. It can be as follows. Such a film is referred to as a second crystalline semiconductor film 121. Further, since the second semiconductor film to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is referred to as a third crystalline semiconductor film 122. In the present embodiment, the donor-type element in the third crystalline semiconductor film 122 is activated together with the gettering step.

Next, as illustrated in FIG. 1D, the third crystalline semiconductor film 122 and the second crystalline semiconductor film are etched using a mask formed by a photolithography process, so that the first semiconductor region is etched. 132 and the second semiconductor region 131 are formed. The third crystalline semiconductor film and the second crystalline semiconductor film are made of chlorine-based gas such as Cl ₂ , BCl ₃ , SiCl _4, or CCl ₄ , CF ₄ , SF ₆ , NF ₃ , CHF _3, etc. Etching can be performed using a representative fluorine-based gas or O ₂ .

  Note that in the photolithography processes of the following embodiments and examples, an insulating film having a thickness of about several nm is preferably formed on the surface of the semiconductor film 122 before applying a resist. By this step, it is possible to avoid direct contact between the semiconductor film and the resist, and impurities can be prevented from entering the semiconductor film. Note that examples of a method for forming the insulating film include a method of applying an oxidizing solution such as ozone water, a method of irradiating oxygen plasma, ozone plasma, and the like.

  Next, a second conductive film is formed. Next, a mask is formed over the second conductive film by a photolithography process. Next, the second conductive film 133 is formed by etching the second conductive film into a desired shape using the mask. The second conductive layer 133 functions as a source electrode and a drain electrode.

  In the conductive film forming process of the embodiment and the example below, when an insulating film is formed on the surface of the semiconductor film during the photolithography process, it is preferable to etch the insulating film before forming the conductive film.

  As a material of the second conductive film, a metal such as Al, Ti, Mo, W, or an alloy thereof can be used. Moreover, you may form as these single layer or multilayer structure. Typically, a laminated structure of Ti / Al / Ti and Mo / Al / Mo may be used.

    Next, as illustrated in FIG. 1E, the exposed portion of the first semiconductor region is etched using the second conductive layer 133 as a mask, so that the source region and the drain region 142 are formed. At this time, a part of the first semiconductor region 131 may be over-etched. The over-etched second semiconductor region at this time is referred to as a third semiconductor region 141. The third semiconductor region 141 functions as a channel formation region.

  Next, it is preferable to form a passivation film over the surfaces of the second conductive layer 133 and the fourth semiconductor region 141. The passivation film is formed using a thin film formation method such as plasma CVD or sputtering, and silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN) and other insulating materials can be used. Note that the passivation film may be a single layer or a laminated structure. Here, it is preferable to form silicon oxide or silicon oxynitride as the third insulating film 140 from the interface characteristics of the fourth semiconductor region 141. The fourth insulating film 144 is preferably formed using silicon nitride or silicon nitride oxide in order to prevent impurities from the outside from entering the semiconductor element.

  Thereafter, the fourth semiconductor region is preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that in the case of heating in a nitrogen atmosphere, an insulating film containing hydrogen is preferably formed in the third insulating film or the fourth insulating film.

  Through the above steps, an inverted staggered TFT having a crystalline semiconductor film can be formed. Since the TFT formed in this embodiment is formed of a crystalline semiconductor film, the mobility is higher than that of a TFT formed of an amorphous semiconductor film. In addition, the source region and the drain region include a catalyst element in addition to the acceptor element or the donor element. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured. Typically, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, in comparison with an EL display device using a TFT formed of an amorphous semiconductor film as a switching element, display unevenness can be reduced and a highly reliable semiconductor device can be manufactured. It is.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. For this reason, it is possible to improve contrast by providing such a TFT in a switching element of a display device, for example, a liquid crystal display device.

(Embodiment 2)
In this embodiment, a process for forming a TFT by gettering a catalytic element using a semiconductor film containing a rare gas element instead of a semiconductor film containing a donor element will be described with reference to FIGS.

  As shown in FIGS. 2A and 2B, a first crystalline semiconductor film 111 is formed by a process similar to that of Embodiment Mode 1. After this, a channel doping process may be performed. Next, an oxide film with a thickness of 1 to 5 nm may be formed on the surface of the first crystalline semiconductor film. Here, ozone water is applied to the surface of the crystalline semiconductor film to form an oxide film.

  Next, a second semiconductor film 212 containing a rare gas element is formed over the first crystalline semiconductor film 111 by a known method such as a PVD method or a CVD method. The second semiconductor film 212 is preferably an amorphous semiconductor film.

Next, the first crystalline semiconductor film 111 and the second semiconductor film 212 are heated by a method similar to that of Embodiment Mode 1, and the first crystalline semiconductor film is indicated by an arrow in FIG. The catalytic element contained in 111 is moved to the second semiconductor film 212 to getter the catalytic element. By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics as in the first embodiment, that is, the concentration of the catalytic element in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably It can be 1 × 10 ¹⁷ / cm ³ or less. Such a film is referred to as a second crystalline semiconductor film 221. Further, since the second semiconductor film to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is referred to as a third crystalline semiconductor film 222.

  Next, as shown in FIG. 2D, after the third crystalline semiconductor film 222 is removed, a conductive second semiconductor film 223 is formed. Here, the second semiconductor film is formed by a plasma CVD method in which a gas containing a group 13 or group 15 element such as boron, phosphorus, or arsenic is added to a silicide gas. Note that the second semiconductor film may be formed using a film having any state selected from an amorphous semiconductor, a SAS, a crystalline semiconductor, and μc. Note that in the case where the second semiconductor film is any one of a conductive amorphous semiconductor film, SAS, and μc, heat treatment for activating impurities is performed thereafter. On the other hand, when the second semiconductor film is a crystalline semiconductor having conductivity, heat treatment is not necessarily performed. Here, an amorphous silicon film containing phosphorus with a thickness of 100 nm is formed by plasma CVD, and then heated at 550 ° C. for 2 hours to activate the impurities.

  Next, as illustrated in FIG. 2E, a first semiconductor region 232 and a second semiconductor region 231 are formed by the same process as that in the first embodiment.

Next, as illustrated in FIG. 2F, a source electrode and a drain electrode 143 are formed.
Through a process similar to that in Embodiment 1, the first semiconductor region can be etched, so that the source and drain regions 242 and the third semiconductor region 241 functioning as a channel formation region can be formed.

  Thereafter, an inverted staggered TFT can be formed by the same process as in the first embodiment. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

(Embodiment 3)
In this embodiment, the step of forming the n-channel TFT and the p-channel TFT on the same substrate is formed using FIG.

  As shown in FIG. 3A, first conductive layers 301 and 302 are formed over a substrate 101 as in the first embodiment, and the first insulating film 103 and the second insulating layer are formed over the first conductive layer. A film 104 is formed. Next, by a process similar to that in Embodiment 1, a first crystalline semiconductor film and a second semiconductor film containing a donor element are formed thereon. Next, using the mask formed by a photolithography process, the first crystalline semiconductor film is etched into a desired shape to form a first semiconductor region, and the second semiconductor film is formed into a desired shape. Etching forms a second semiconductor region.

  Next, the first semiconductor region and the second semiconductor region are heated to move the catalytic element included in the second semiconductor region to the first semiconductor region as indicated by arrows in FIG. And gettering the catalytic element. Here, the first semiconductor region in which the metal catalyst after gettering has moved is referred to as third semiconductor regions 312, 313, and the second semiconductor region in which the metal element concentration is reduced is fourth semiconductor regions 313, 314. It shows. Note that the third semiconductor region and the fourth semiconductor region are each crystallized by heating in the gettering step.

  In this embodiment, the gettering process is performed after forming each semiconductor region, but after the gettering process of each semiconductor film is performed as in Embodiment 1, the semiconductor film is etched into a desired shape, Each semiconductor region may be formed.

  Next, after an oxide film is formed on the surfaces of the third semiconductor regions 313 and 314 and the fourth semiconductor regions 311 and 312, masks 321 and 322 are formed by a photolithography process as illustrated in FIG. To do. The mask 321 covers all of the third semiconductor region 313 and the fourth semiconductor region 311 that will be n-channel TFTs later. On the other hand, the mask 322 covers a part of the third semiconductor region 314 to be a p-channel TFT later. At this time, the first mask 322 is preferably narrower than the channel length of a p-channel TFT to be formed later.

Next, a Group 3 element (Group 13 element, hereinafter referred to as an acceptor element) is added to the exposed portion of the third semiconductor region 314 to form a p-type impurity region 324. At this time, the region covered with the first mask 322 remains as the n-type impurity region 325.

  Next, after the first masks 321 and 322 are removed, the third semiconductor region 313 and the first semiconductor region 314 to which one acceptor element is added are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 1 hour.

  Next, as illustrated in FIG. 3C, second conductive layers 331 and 332 are formed as in the first embodiment. Next, source and drain regions 343 and 344 are formed using the second conductive layers 331 and 332 as masks. Next, it is preferable to form passivation films 140 and 144 on the surfaces of the second conductive layers 331 and 332 and the fifth semiconductor regions 341 and 342.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. In addition, it is possible to form a CMOS that can be driven at a lower voltage than a drive circuit formed of a single channel TFT. Furthermore, since the acceptor element (e.g., boron) has a smaller atomic radius than the donor element (e.g., phosphorus), the acceptor element is added to the semiconductor film at a relatively low acceleration voltage and concentration. Is possible. In this embodiment, since only the acceptor element is added to the semiconductor film, it can be manufactured in a shorter time and with less energy compared with the manufacturing process of the conventional COMS circuit. As a result, the cost can be reduced. Is possible.

(Embodiment 4)
In this embodiment, an n-channel TFT and a p-channel manufacturing process including a crystalline semiconductor film formed by a gettering process different from that in Embodiment 3 will be described with reference to FIGS.

  In accordance with Embodiment Mode 1, first conductive layers 301 and 302 are formed over the substrate 101. Next, in accordance with Embodiment 1, after forming a first crystalline semiconductor film having a catalytic element as shown in FIG. 1B, an insulating film having a thickness of several nm is formed on the surface of the first crystalline semiconductor film. To do. Next, a first mask is formed by a photolithography process, and the first crystalline semiconductor film is etched into a desired shape, so that first semiconductor regions 401 and 402 are formed.

  Next, as illustrated in FIG. 4B, a second mask is formed over the first semiconductor regions 401 and 402 by a photolithography process, and then a donor-type element is formed in an exposed portion of the first semiconductor region. Add. At this time, regions to which the donor element is added are denoted as n-type impurity regions 406 and 407. Here, phosphorus is added by an ion doping method. Note that the first semiconductor region covered with the second mask does not contain phosphorus but contains a catalytic element.

  Next, the first semiconductor region is heated, and the catalyst element contained in the first semiconductor region is moved to the n-type impurity regions 406 and 407 as shown by arrows in FIG. Gettering elements. Here, the first semiconductor region to which the metal catalyst after gettering has moved is referred to as a source region and drain regions 413 and 414, and the first semiconductor region in which the metal element concentration is reduced is referred to as a channel formation region 411. Note that the third semiconductor region and the fourth semiconductor region are each crystallized by heating in the gettering step, and the donor-type element contained in the n-type impurity regions 406 and 407 is activated. Yes.

  Next, as shown in FIG. 4D, third masks 421 and 422 are formed by a photolithography process. The third mask 421 covers all of the channel formation region 411 and the n-type impurity region 413 that will later become n-channel TFTs. On the other hand, the third mask 422 covers part or all of the channel formation region 412 to be a p-channel TFT later. At this time, the third mask 422 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, an acceptor element is added to the exposed portions of the n-type impurity region 414 and the channel formation region 412 to form a p-type impurity region 424. At this time, a p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the n-type impurity region 414.

  Next, after the third masks 421 and 422 are removed, the n-type impurity region 414 and the p-type impurity region 424 are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 1 hour.

  Next, as illustrated in FIG. 4D, second conductive layers 331 and 332 are formed as in the first embodiment. Thereafter, part of the channel formation regions 411 and 412 may be etched. Next, it is preferable to form passivation films 140 and 144 on the surfaces of the second conductive layers 331 and 332 and the channel formation regions 411 and 412.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Further, since the number of film formation steps can be reduced as compared with Embodiment Mode 3, throughput can be improved.

(Embodiment 5)
In the present embodiment, a step of forming an n-channel TFT and a p-channel TFT on the same substrate using the crystalline semiconductor film subjected to the gettering step using Embodiment Mode 2 is formed using FIG.

  First conductive layers 301 and 302 are formed over the substrate 101 in accordance with the steps of Embodiment Mode 1. Next, a first crystalline semiconductor film and a second semiconductor film containing a rare gas element are formed according to the steps of Embodiment Mode 2. Next, the first crystalline semiconductor film and the second semiconductor film are heated by a method similar to that in Embodiment 1 and are included in the first crystalline semiconductor film as indicated by arrows in FIG. The catalytic element is moved to the second semiconductor film to getter the catalytic element. The first crystalline semiconductor film in which the catalytic element is gettered is referred to as a second crystalline semiconductor film 501. In addition, since the second semiconductor film to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is referred to as a third crystalline semiconductor film 502.

  Next, as shown in FIG. 6B, after the third crystalline semiconductor film 502 is etched, an insulating film having a thickness of several nm is formed on the surface of the second crystalline semiconductor film 501. Next, a first mask is formed by a photolithography process, and the second crystalline semiconductor film is etched to form first semiconductor regions 511 and 512. Next, second masks 513 and 514 are formed by a photolithography process. The second mask 513 covers a portion that later becomes a channel formation region of the n-channel TFT. On the other hand, the second mask 514 covers the entire first semiconductor region 512 that will later become a p-channel TFT. Next, a donor-type element is added to the exposed portion of the first semiconductor region 511. At this time, a region to which the donor element is added is referred to as an n-type impurity region 516. The region covered with the second mask 513 functions as a channel formation region 517.

  Next, after the second masks 513 and 514 are etched, new third masks 521 and 522 are formed. The third mask 521 covers all of the channel formation region 411 and the n-type impurity region 413 that will be n-channel TFTs later. On the other hand, the third mask 422 covers a region to be a channel formation region of the p-channel TFT later.

  Next, an acceptor element is added to the exposed portion of the semiconductor region 512 to form a p-type impurity region 524. Further, the region covered with the third mask 522 functions as a channel formation region 525. Next, after removing the third masks 521 and 522, the n-type impurity region 516 and the p-type impurity region 524 are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate.

  Next, as illustrated in FIG. 5D, second conductive layers 331 and 332 are formed as in Embodiment 1. Thereafter, part of the channel formation regions 517 and 525 may be etched. Next, it is preferable to form passivation films 140 and 144 on the surfaces of the second conductive layers 331 and 332 and the channel formation regions 411 and 412.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

(Embodiment 6)
In this embodiment, a process of forming an n-channel TFT and a p-channel TFT on the same substrate using a modification of the third embodiment is formed using FIG.

  According to Embodiment 3, as shown in FIG. 6A, third semiconductor regions 313 and 314 and fourth semiconductor regions 311 and 312 having a catalyst element and a donor element are formed. Next, as illustrated in FIG. 6B, after the first mask 321 is formed, an acceptor element is added to the third semiconductor region 314 to form a p-type impurity region 601. At this time, a p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the n-type impurity region 314. Further, when boron is used as the acceptor element, the molecular radius is small, so that it is added deeper than the third semiconductor region. For this reason, boron is added to the upper portion of the fourth semiconductor region depending on the addition conditions. Thereafter, the third semiconductor region 313 and the p-type impurity region 601 are heated to activate the acceptor-type element and the donor-type element.

  Next, second conductive layers 311 and 312 are formed according to the third embodiment. Next, the exposed portions of the third semiconductor region 313 and the p-type impurity region 601 are etched using the second conductive layers 311 and 312 as a mask to form a source region and a drain region 343 as shown in FIG. 622 and fifth semiconductor regions 341 and 611 functioning as channel formation regions can be formed. After that, it is preferable to form passivation films 140 and 144 on the surfaces of the second conductive layers 331 and 332 and the channel formation regions 411 and 412.

Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Furthermore, since only the acceptor-type element is added to the semiconductor film as in the third embodiment, it can be manufactured in a shorter time and with less energy compared to the manufacturing process of the conventional COMS circuit. As a result, the cost can be reduced.

(Embodiment 7)
In this embodiment, the positional relationship between the end portions of the gate electrode, the source electrode, and the drain electrode, that is, the relationship between the width of the gate electrode and the size of the channel length in the above embodiment is described with reference to FIGS. To do.

  In FIG. 7A, the end portions of the source electrode and the drain electrode are overlapped on the gate electrode 102 by z1. Here, a region where the gate electrode 102 overlaps with the source electrode and the drain electrode is referred to as an overlap region. That is, the width y1 of the gate electrode is larger than the channel length x1. The width z1 of the overlap region is represented by (y1−x1) / 2. An n-channel TFT having such an overlap region preferably has an n + region and an n − region as shown in FIG. 9B between the source and drain electrodes and the semiconductor region. With this structure, the effect of relaxing the electric field is increased, and hot carrier resistance can be increased.

    In FIG. 7B, the end portion of the gate electrode 102 is aligned with the end portions of the source electrode and the drain electrode. That is, the gate electrode width y2 is equal to the channel length x2.

  In FIG. 7C, the gate electrode 102 and the end portions of the source electrode and the drain electrode are separated by z3. Here, a region where the gate electrode 102 is separated from the source electrode and the drain electrode is referred to as an offset region. That is, the width y3 of the gate electrode is smaller than the channel length x3. The width z3 of the offset area is represented by (x3-y3) / 2. Since the TFT having such a structure can reduce off-state current, contrast can be improved when the TFT is used as a switching element of a display device.

  In FIG. 8A, the width y4 of the gate electrode is larger than the channel length x4. In addition, the first end portion of the gate electrode 102 and one end portion of the source electrode or the drain electrode coincide with each other, and the second end portion of the gate electrode 102 and the other end portion of the source electrode or the drain electrode correspond to z4. Only overlap. The width z4 of the overlap region is represented by (y4-x4).

  In FIG. 8B, the width y5 of the gate electrode is larger than the channel length x5. In addition, the first end portion of the gate electrode 102 and one end portion of the source electrode or the drain electrode coincide with each other, and the second end portion of the gate electrode 102 and the other end portion of the source electrode or the drain electrode become z5. Just away. The width z5 of the offset area is represented by (x5-y5). By using the electrode having the first end portion and the end portion of the gate electrode 102 as the source electrode and the electrode having the offset region as the drain electrode, electric field relaxation in the vicinity of the drain electrode can be achieved.

  In FIG. 8C, the first end portion of the gate electrode 102 overlaps with one end portion of the source electrode or the drain electrode by z6, and the second end portion of the gate electrode 102 and the other end of the source electrode or drain electrode overlap with each other. Is separated by z7. By using the electrode having the overlap region of the gate electrode 102 as the source electrode and the electrode having the offset region as the drain electrode, electric field relaxation in the vicinity of the drain electrode can be achieved.

  Further, a TFT having a so-called multi-gate structure in which the semiconductor region covers a plurality of gate electrodes may be used. A TFT having such a structure can also reduce off-state current.

(Embodiment 8)
In Embodiments 1 to 3 and 6, the semiconductor film containing a donor-type element includes a semiconductor film 145 containing a low-concentration donor-type element and a high-concentration donor-type element as shown in FIG. A two-layer structure of the semiconductor film 142 may be used. With such a stacked structure, a TFT having an LDD region 145 can be formed as shown in FIG. As a result, the effect of relaxing the electric field is increased, and it is possible to form a TFT with improved hot carrier resistance.

(Embodiment 9)
In the above embodiment, the source electrode and the drain electrode having end portions perpendicular to the surface of the channel formation region are shown; however, the present invention is not limited to this structure. As shown in FIG. 26 (A), it may be an end portion that is greater than 90 degrees and less than 180 degrees, preferably 95 to 135 degrees with respect to the channel formation region surface. Further, if the angle between the source electrode and the channel formation region surface is θ1, and the angle between the drain electrode and the channel formation region surface is θ2, θ1 and θ2 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a dry etching method.

  On the other hand, as shown in FIG. 26 (B), it may be an end portion that is larger than 0 degree and smaller than 90 degrees, preferably 45 to 85 degrees with respect to the channel formation region surface. Further, if the angle between the source electrode and the channel formation region surface is θ3, and the angle between the drain electrode and the channel formation region surface is θ4, θ3 and θ4 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a wet etching method.

(Embodiment 10)
In this embodiment, a semiconductor film crystallization process applicable to the above embodiment will be described with reference to FIGS. As shown in FIG. 27A, a semiconductor film may be crystallized by forming a mask 2701 formed of an insulating film over the semiconductor film 106 and selectively forming a catalytic element layer 2705. When the semiconductor film is heated, crystal growth occurs in a direction parallel to the surface of the substrate from a contact portion between the catalytic element layer and the semiconductor film, as indicated by an arrow in FIG. Note that crystallization is not performed in a portion considerably away from the catalyst element layer 2705, and an amorphous portion remains.

  Alternatively, as shown in FIG. 28A, the crystallization may be performed by selectively forming a catalytic element layer 2805 by a droplet discharge method without using a mask. FIG. 28B is a top view of FIG. FIG. 28D is a top view of FIG. When the semiconductor film is crystallized, crystal growth occurs in the direction parallel to the surface of the substrate from the contact portion between the catalytic element layer and the semiconductor film, as shown in FIGS. Again, crystallization is not performed at a portion far away from the catalyst element layer 2705, and an amorphous portion 2807 remains.

Thus, crystal growth in a direction parallel to the substrate is referred to as lateral growth or lateral growth.
Since large crystal grains can be formed by lateral growth, a TFT having higher mobility can be formed.

  Next, a method for manufacturing an active matrix substrate and a display device having the active matrix substrate will be described with reference to FIGS. In this embodiment, a liquid crystal display device is used as a display device. FIGS. 14 and 29 are plan views of the active matrix substrate. FIGS. 11 to 13 schematically show longitudinal sectional structures corresponding to the drive circuit portion A-A ′ and the pixel portion B-B ′.

  As shown in FIG. 11A, a first conductive film with a thickness of 100 to 200 nm is formed over a substrate 800. Here, a glass substrate is used as the substrate 800, and a 150-nm-thick tungsten film is formed as a first conductive film over the surface by a sputtering method. Next, using the first photomask, the first conductive film is etched to form first conductive layers 801 to 804. Here, the tungsten film is etched by a dry etching method to form a tungsten layer which is the first conductive layers 801 to 804. Note that the first conductive layer functions as a gate electrode.

  Next, a first insulating film is formed over the surface of the substrate 800 and the first conductive layers 801 to 804. Here, as the first insulating film, a 50 nm-thickness 100 nm silicon nitride film 805 and a silicon oxynitride film (SiON (O> N) 806) are stacked by a CVD method. The insulating film functions as a gate insulating film, and at this time, it is preferable that the silicon nitride film and the silicon oxynitride film be continuously formed only by switching the source gas without being released to the atmosphere.

  Next, an amorphous semiconductor film 807 with a thickness of 10 to 100 nm is formed over the first insulating film. Here, an amorphous silicon film with a thickness of 100 nm is formed by a CVD method. Next, a solution 808 containing a catalytic element is applied over the surface of the amorphous semiconductor film 807. Here, a solution containing 100 ppm of nickel catalyst is applied by spin coating. Next, the amorphous semiconductor film 807 is heated to form a crystalline semiconductor film 811 as shown in FIG. Note that the crystalline semiconductor film 811 contains a catalyst element. Here, using an electric furnace, the semiconductor film is dehydrogenated by heating at 500 ° C. for 1 hour, and then heated at 550 ° C. for 4 hours to form a crystalline silicon film containing nickel. Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the subsequent TFT is performed over the entire surface or selectively.

  Next, a semiconductor film 812 containing a donor-type element with a thickness of 100 nm is formed over the surface of the crystalline semiconductor film 811 containing the catalyst element. Here, an amorphous silicon film containing phosphorus is formed using silane gas and 0.5% phosphine gas (flow ratio silane / phosphine is 10/17).

Next, the crystalline semiconductor film 811 and the semiconductor film 812 containing a donor element are heated to getter the catalytic element and activate the donor element. That is, the catalyst element in the crystalline semiconductor film 811 containing a catalyst element is moved to the semiconductor film 812 containing a donor-type element. A crystalline semiconductor film in which the concentration of the catalytic element is reduced is indicated by 813 in FIG. Here, a crystalline silicon film is formed. In addition, a semiconductor film containing a donor element to which the catalyst element has moved also becomes a crystalline semiconductor film by heating. That is, a crystalline semiconductor film containing a catalytic element and a donor element is obtained. This is indicated by 814 in FIG. Here, a crystalline silicon film containing nickel and phosphorus is formed.

  Next, the crystalline semiconductor film 814 containing a catalytic element and a donor element and the crystalline semiconductor film 813 are etched into a desired shape using a second photomask. At this time, the etched crystalline semiconductor film containing the catalytic element and the donor element is referred to as first semiconductor regions 824 to 826, and the etched crystalline semiconductor film 813 is referred to as second semiconductor regions 821 to 823.

  Next, in the driver circuit, one of the first insulating film 805 and the second insulating film 806 is formed using a third photomask in order to connect the gate electrode and the source electrode or the drain electrode of some TFTs. The portion is etched to form a contact hole 850 as shown in FIG.

  Next, as illustrated in FIG. 12B, a second conductive layer 851 functioning as a pixel electrode is formed over the first insulating film 806 formed over the substrate. Here, after the second conductive film is formed, the second conductive film 851 is formed by etching the second conductive film using a fourth photomask. As a material for the second conductive layer, a light-transmitting conductive film or a reflective conductive film can be given. As a material for the light-transmitting conductive film, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide, or the like Is mentioned. In addition, as a material for the conductive film having reflectivity, a metal such as aluminum (Al), titanium (Ti), silver (Ag), and tantalum (Ta), or a concentration less than the stoichiometric composition ratio with the metal is used. Examples thereof include a metal material containing nitrogen, or titanium nitride (TiN), tantalum nitride (TaN) which is a nitride of the metal, or aluminum containing 1 to 20% nickel. Further, as a method for forming the second conductive film, a sputtering method, a vapor deposition method, a CVD method, a coating method, or the like is appropriately used. Here, indium tin oxide (ITO) containing silicon oxide with a thickness of 110 nm is formed and etched into a desired shape, so that the second conductive layer 851 is formed.

  Next, a third conductive film with a thickness of 100 to 300 nm is formed so as to be in contact with the first semiconductor regions 824 to 826, the second conductive layer 851, and the first conductive layer 802. Here, a molybdenum film with a thickness of 200 nm is formed by a sputtering method. Next, using the fifth photomask, the third conductive film is etched into a desired shape, so that third conductive layers 831 to 835 are formed. Here, the third conductive layer is formed by etching the molybdenum film by wet etching using aluminum mixed acid. Note that the third conductive layers 831 to 835 function as a source electrode and a drain electrode.

  Next, the first semiconductor regions 824 to 826 are etched using the third conductive layers 831 to 835 as masks to form source and drain regions 835 to 837. At this time, part of the second semiconductor regions 821 to 823 is also etched. The etched semiconductor regions function as third channel regions 840 to 842 as channel formation regions.

  Next, as illustrated in FIG. 12C, a second insulating film 852 and a third insulating film 853 are formed over the surface of the third conductive layer and the third semiconductor region. Here, a 150-nm-thick silicon oxynitride film (SiON (O> N) containing hydrogen is formed by a CVD method as the second insulating film, and a 200-nm-thick silicon nitride film is formed as the third insulating film. The silicon nitride film functions as a protective film that blocks impurities from the outside.

  Next, although not shown, the silicon nitride film and the silicon oxynitride film formed on the wiring in the connection terminal portion are etched to expose the wiring surface so as to be connected to the external terminal.

  Next, the third semiconductor regions 835 to 837 are heated and hydrogenated. Here, by performing heating at 410 ° C. for 1 hour in a nitrogen atmosphere, hydrogen contained in the second insulating film 852 is added to the third semiconductor regions 835 to 837 and hydrogenated.

  Note that a planar structure of the vertical cross-sectional structure B-B ′ of the pixel portion in FIG. 12C is shown in FIG.

  Through the above steps, an active matrix substrate of a liquid crystal display device including a driver circuit formed using n-channel TFTs 861 and 862 and a pixel portion including an n-channel TFT 862 having a double gate 803 can be formed. . In this embodiment, since the drive circuit is formed of n-channel TFTs, it is not necessary to form p-channel TFTs, and the number of processes can be reduced.

  Next, as illustrated in FIG. 13, an insulating film is formed by a printing method or a spin coating method so as to cover the silicon nitride film 853, and an alignment film 871 is formed by rubbing. Note that by forming the alignment film 871 by an oblique deposition method, the alignment film 871 can be formed at a low temperature, and the alignment film can be formed over a plastic having low heat resistance.

  A second pixel electrode (counter electrode) 873 and an alignment film 874 are formed over the counter substrate 872. Next, a closed loop sealing material is formed over the counter substrate 872. At this time, the sealing material is formed in a region around the pixel portion using a droplet discharge method. Next, a liquid crystal material is dropped inside the closed loop formed of the sealing material by a dispenser type (dropping type).

    A filler may be mixed in the sealing material, and a color filter, a shielding film (black matrix), or the like may be formed on the counter substrate 872.

  Next, the counter substrate 872 provided with the alignment film 874 and the second pixel electrode (counter electrode) 873 and the active matrix substrate are bonded to each other in a vacuum, and ultraviolet curing is performed, so that a liquid crystal filled with a liquid crystal material is obtained. Layer 875 is formed. Note that as a method for forming the liquid crystal layer 875, a dip type (pumping type) in which a liquid crystal material is injected using a capillary phenomenon after the counter substrate is bonded can be used instead of the dispenser type (dropping type).

  Through the above process, a liquid crystal display panel can be manufactured. Note that a protection circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring (gate wiring) or in the pixel portion. In this case, the TFT can be manufactured in the same process as the above TFT, and can be operated as a diode by connecting the gate wiring layer of the pixel portion and the drain or source wiring layer of the diode.

  Through the above process, a liquid crystal display device can be formed. Note that any of Embodiment Modes 1 to 10 can be applied to this example.

  In this embodiment, the appearance of a liquid crystal display device panel, which is one embodiment of the semiconductor device of the present invention, will be described with reference to FIG. FIG. 15A is a top view of a panel in which a space between the first substrate 1600 and the second substrate 1604 is sealed with the first sealant 1605 and the second sealant 1606. FIG. FIG. 15B corresponds to a cross-sectional view taken along lines AA ′ and BB ′ in FIG. The active matrix substrate formed in Embodiment 1 can be used for the first substrate 1600.

  In FIG. 15A, 1602 indicated by a dotted line is a pixel portion, and 1603 is a scanning line driver circuit. Reference numeral 1601 indicated by a solid line is a signal line (gate line) drive circuit. In this embodiment, the pixel portion 1602 and the scan line driver circuit 1603 are in a region sealed with the first sealant and the second sealant. Reference numeral 1601 denotes a signal line (source line) driver circuit, and a chip-like signal line driver circuit is provided on the first substrate 1600.

  Reference numeral 1600 denotes a first substrate, 1604 denotes a second substrate, and 1605 and 1606 denote a first sealant and a second sealant each containing a gap material for maintaining a space between the sealed spaces. is there. The first substrate 1600 and the second substrate 1604 are sealed with a first sealant 1605 and a second sealant 1606, and a liquid crystal material is filled therebetween.

  Next, a cross-sectional structure will be described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1600 and have a plurality of semiconductor elements typified by TFTs. A color filter 1621 is provided on the surface of the second substrate 1604. A scan line driver circuit 1603 and a pixel portion 1602 are shown as driver circuits. Note that as the scan line driver circuit 1603, a CMOS circuit in which an n-channel TFT 1612 and a p-channel TFT 1613 are combined is formed. Note that the drive circuit may be formed of a single channel TFT as in the first embodiment.

  In this embodiment, the scanning line driving circuit and the TFT of the pixel portion are formed on the same substrate. For this reason, the volume of the display device can be reduced.

  In the pixel portion 1601, a plurality of pixels are formed, and a liquid crystal element 1615 is formed in each pixel. The liquid crystal element 1615 is a portion where the first electrode 1616, the second electrode 1618, and the liquid crystal material 1619 filled therebetween overlap. A first electrode 1616 included in the liquid crystal element 1615 is electrically connected to the TFT 1611 through a wiring 1617. Although the first electrode 1615 is formed after the wiring 1617 is formed here, the wiring 1617 may be formed after the first electrode 1616 is formed as shown in Embodiment 1. The second electrode 1618 of the liquid crystal element 1615 is formed on the second substrate 1604 side. In addition, alignment films 1630 and 1631 are formed on the surface of each pixel electrode.

  Reference numeral 1622 denotes a columnar spacer, which is provided to control the distance (cell gap) between the first electrode 1616 and the second electrode 1618. The insulating film is formed by etching into a desired shape. A spherical spacer may be used. Various signals and potentials supplied to the signal line driver circuit 1601 or the pixel portion 1601 are supplied from the FPC 1609 through the connection wiring 1623. Note that the connection wiring 1623 and the FPC are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1627. Note that a conductive paste such as solder may be used instead of the anisotropic conductive film or the anisotropic conductive resin.

  Although not illustrated, a polarizing plate is fixed to one or both surfaces of the first substrate 1600 and the second substrate 1604 with an adhesive. Note that a circularly polarizing plate or an elliptically polarizing plate provided with a retardation plate may be used as the polarizing plate.

  Next, a method for manufacturing an active matrix substrate and a display device having the active matrix substrate will be described with reference to FIGS. In this embodiment, a light-emitting display device is used as the display device. FIG. 19 is a plan view of the active matrix substrate, and a vertical cross-sectional structure corresponding to B-B ′ of the pixel portion is schematically shown in FIGS. 17 and 18. Although not shown in the plan view, the longitudinal sectional structure of the drive circuit is schematically shown in A-A ′ of FIGS. 17 and 18.

  As shown in FIG. 17A, a first conductive film having a thickness of 100 to 200 nm is formed over a substrate 900 and etched to form first conductive layers 901 to 904 as in Example 1. . Note that the first conductive layer functions as a gate electrode.

  Next, first insulating films 905 and 906 are formed on the surface of the substrate 900 and the first conductive layers 901 to 904.

  Next, an amorphous semiconductor film with a thickness of 10 to 100 nm is formed over the first insulating film, and a solution containing a catalytic element is applied over the surface of the amorphous semiconductor film. Next, the amorphous semiconductor film is heated to form a crystalline semiconductor film. Note that the crystalline semiconductor film contains a catalytic element. Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the subsequent TFT is performed over the entire surface or selectively.

  Next, a semiconductor film 908 containing a donor-type element with a thickness of 100 nm is formed over the surface of the crystalline semiconductor film 907 containing a catalytic element. Next, the crystalline semiconductor film and the semiconductor film 812 containing a donor element are heated to getter the catalyst element and activate the donor element. That is, the catalyst element in the crystalline semiconductor film 907 containing the catalyst element is moved to the semiconductor film containing the donor element. A crystalline semiconductor film in which the concentration of the catalytic element at this time is reduced is indicated by reference numeral 907 in FIG. In addition, a semiconductor film containing a donor element to which the catalyst element has moved also becomes a crystalline semiconductor film by heating. That is, a crystalline semiconductor film containing a catalytic element and a donor element is obtained. This is indicated by reference numeral 908 in FIG.

  Next, the crystalline semiconductor film 907 and the crystalline semiconductor film 908 containing a catalyst element and a donor element are etched into a desired shape using a second photomask. At this time, the etched crystalline semiconductor film 908 containing the catalytic element and the donor-type element is referred to as a first semiconductor region 915 to 918, and the etched crystalline semiconductor film 907 is referred to as a second semiconductor region 911 to 914.

  Next, as illustrated in FIG. 17C, first masks 920 to 923 are formed using a third photomask. The first mask 920 covers the entire first semiconductor region 915 and the second semiconductor region 911. Further, the first mask 921 covers the entire first semiconductor region 917 and the second semiconductor region 913. These semiconductor regions later function as n-channel TFTs. The first masks 922 and 923 cover parts of the first semiconductor regions 916 and 918, respectively. At this time, the first masks 922 and 923 are preferably narrower than the channel length of a TFT to be formed later. Note that the first semiconductor regions 916 and 918 and the second semiconductor regions 912 and 914 covered by the first semiconductor regions 916 and 918 later function as p-channel TFTs.

  Next, an acceptor element is added to the exposed portions of the first semiconductor regions 912 and 914 to form p-type impurity regions 925, 926, 928, and 930. At this time, regions covered with the first masks 922 and 923 remain as n-type impurity regions 927 and 923.

  Next, after the first masks 920 to 923 are removed, the first semiconductor regions 915 and 917 and the first semiconductor regions 916 and 918 to which the acceptor element is added are heated to activate the impurity elements. . Here, heating is performed at 550 degrees for 1 hour.

  Through the above steps, the pixel circuit includes a driver circuit formed of an n-channel TFT 952 and a p-channel TFT 953, a switching TFT 954 formed of an n-channel TFT, and a driver TFT 955 formed of a p-channel TFT. An active matrix substrate of a light emitting display device can be formed.

  Next, a second conductive film is formed. As the second conductive film, a reflective conductive film and a transparent conductive film are stacked. Here, a titanium nitride film and ITO containing silicon oxide are stacked by a sputtering method. Next, the second conductive film is etched using the fourth photomask to form a second conductive layer 951 functioning as a pixel electrode.

  Next, although not shown, a part of the first insulating films 905 and 906 formed on the surface of the first conductive layer 904 in FIG. 19 is etched using a fifth photomask to form a contact hole 909. At the same time, a part of the first conductive layer 904 is exposed.

    Next, as shown in FIG. 18A, after forming a third conductive film as in Example 1, the third conductive film was etched into a desired shape using a sixth photomask, and the third conductive film was etched. Conductive layers 931 to 938 are formed. The second conductive layer 936 is connected to the first conductive layer 904. Note that the third conductive layers 931 to 948 function as a source electrode and a drain electrode.

    Next, the first semiconductor region is etched using the third 931 to 948 as a mask to form source and drain regions 941 to 948. At this time, a part of the second semiconductor region is also etched. The third semiconductor region which is the etched second semiconductor region functions as a channel formation region.

  Next, as illustrated in FIG. 12C, a fourth insulating film 852 and a fifth insulating film 853 are formed over the second conductive layer, the third conductive layer, and the surface of the third semiconductor region. . Here, a 150-nm-thick silicon oxynitride film (SiON (O> N) containing hydrogen is formed by a CVD method as the fourth insulating film, and a 200-nm-thick silicon nitride film is formed as the fifth insulating film. The silicon nitride film functions as a protective film that blocks impurities from the outside.

  Next, the third semiconductor region is heated and hydrogenated. Here, by heating at 410 ° C. for 1 hour in a nitrogen atmosphere, hydrogen contained in the third insulating film is added to the third semiconductor region and hydrogenated.

    Next, after a fifth insulating film is formed over the entire surface, the fifth insulating film, the fourth insulating film, and the third insulating film are etched using a seventh photomask, and the fifth insulating film is etched. The insulating layer 961, the fourth insulating layer 953, and the third insulating layer 952 are formed. In the case of forming the third insulating layer to the fifth insulating layer, the first pixel electrode 667 and the connection terminal portion are processed so as to be exposed.

  As a material for the fifth insulating film, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride and other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, or polyimide ( Among the compounds consisting of silicon, oxygen and hydrogen formed from a heat-resistant polymer such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane polymer material typified by silica glass, Si— Hydrogen on silicon typified by inorganic siloxane polymer containing O-Si bond, alkylsiloxane polymer, alkylsilsesquioxane polymer, hydrogenated silsesquioxane polymer, hydrogenated alkylsilsesquioxane polymer is methyl or phenyl. It may be an organic siloxane polymer based insulating material which is substituted by an organic group such as. As a forming method, a known method such as a CVD method, a coating method, or a printing method is used. Note that the surface of the second insulating layer can be planarized by being formed by a coating method. Note that by using an organic material in which a material that absorbs visible light, such as a black pigment or a dye, is used as the fifth insulating layer, stray light absorption of a light-emitting element to be formed later can be prevented from occurring in the fifth insulating layer. It is absorbed by the layer, and the contrast of each pixel can be improved. Further, it is preferable to form the fifth insulating layer using a photosensitive material because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off. Here, the fifth insulating film is formed by applying and baking an acrylic resin by a coating method.

  Through the above steps, an active matrix substrate of a light-emitting display device can be formed.

  Next, a layer 963 containing a light-emitting substance is formed over the surface of the second conductive layer 951 and the end portion of the fifth insulating layer 961 by an evaporation method, a coating method, a droplet discharge method, or the like. After that, a fourth conductive layer 964 that functions as a second pixel electrode is formed over the layer 963 containing a light-emitting substance. Here, ITO containing silicon oxide is formed by a sputtering method. As a result, a light-emitting element can be formed using the second conductive layer, the layer containing a light-emitting substance, and the fourth conductive layer. The materials of the conductive layer and the layer containing a light-emitting substance that constitute the light-emitting element are appropriately selected, and the thicknesses of the layers are also adjusted.

Note that before the layer 963 containing a light-emitting substance is formed, heat treatment is performed at 200 to 350 ° C. in atmospheric pressure to remove moisture adsorbed in or on the surface of the fifth insulating layer 961. Further, heat treatment is performed at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and the layer 963 containing a light-emitting substance is not exposed to the air as it is. Furthermore, it is preferable to form by a coating method or the like.

  The layer 963 containing a light-emitting substance is formed using a charge injecting and transporting substance containing an organic compound or an inorganic compound and a light-emitting material, and based on the number of molecules thereof, a low molecular organic compound or a medium molecular organic compound (not sublimable, An organic compound having a molecular length of 10 μm or less, typically a dendrimer, an oligomer, etc.), and one or a plurality of types of layers selected from high molecular organic compounds. You may combine with the inorganic compound of a hole injection transport property.

Among the charge injecting and transporting materials, materials having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (5-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), quinoline skeleton or benzoquinoline Examples thereof include metal complexes having a skeleton.

As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: Aromatic amine systems such as TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, benzene ring— Compound having a nitrogen bond).

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transport property such as Alq3 and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injecting and transporting materials, materials having a high hole injecting property include, for example, molybdenum oxide (MoO _x ), vanadium oxide (VO _x ), ruthenium oxide (RuO _x ), and tungsten oxide (WO _x ). And metal oxides such as manganese oxide (MnO _x ). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPc) can be given.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, by providing a filter (colored layer) that transmits light in the emission wavelength band on the light emission side of the pixel, the color purity is improved and the pixel portion is mirrored (reflected). Prevention can be achieved. By providing the filter (colored layer), it is possible to omit a circularly polarized plate that has been considered necessary in the past, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various materials for the light emitting material forming the light emitting layer. Among the low molecular weight organic light emitting materials, 4-dicyanomethylene-2-methyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran (abbreviation: DCJT), 4- Dicyanomethylene-2-t-butyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran (abbreviation: DPA), perifuranthene, 2,5-dicyano-1, 4-bis (10-methoxy-1,1,7,7-tetramethyljulolidyl-9-enyl) benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8 - quinolinolato) aluminum (abbreviation: Alq _3), 9,9'-bianthryl, 9,10-diphenyl anthracene (abbreviation: DPA) and 9,10-bis (2-naphthyl) anthracene ( Abbreviations: DNA) and the like can be used. Other substances may also be used.

  On the other hand, the high molecular organic light emitting material has higher physical strength than the low molecular weight material, and the durability of the device is high. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of the light emitting element using the polymer organic light emitting material is basically the same as that when the low molecular weight organic light emitting material is used, and is a layer / anode containing a cathode / light emitting substance. However, when forming a layer containing a light emitting material using a high molecular weight organic light emitting material, it is difficult to form a layered structure as in the case of using a low molecular weight organic light emitting material, and in many cases two layers are formed. It becomes a structure. Specifically, the structure is cathode / light-emitting layer / hole transport layer / anode.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  Examples of the polyparaphenylene vinylene include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for _{example, Alq 3, Alq 3, Alq} 3 doped with Nile Red which is partly red light emitting pigment, p-EtTAZ, by TPD (aromatic diamine) evaporation A white color can be obtained by sequentially laminating. Moreover, when forming a light emitting layer by the apply | coating method using spin coating, after apply | coating, it is preferable to bake by vacuum heating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then the luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

  The substances forming the layer containing the light-emitting substance listed above are examples, such as a hole injecting and transporting layer, a hole transporting layer, an electron injecting and transporting layer, an electron transporting layer, a light emitting layer, an electron blocking layer, and a hole blocking layer. A light-emitting element can be formed by appropriately stacking functional layers. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, it is possible to provide a modification with an electrode for this purpose or a dispersed light-emitting material. Can be permitted without departing from the spirit of the present invention.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved.

  Next, a transparent protective layer 964 that covers the light-emitting element and prevents moisture from entering is formed. As the transparent protective layer 964, a silicon nitride film, a silicon oxide film, a silicon oxynitride film (SiNO film (composition ratio N> O) or SiON film (composition ratio N <O)) obtained by sputtering or CVD, carbon A thin film (for example, a DLC film or a CN film) whose main component is can be used.

  Through the above process, a light-emitting display panel can be manufactured. Note that a protective circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring layer (gate wiring layer) or in the pixel portion. In this case, the TFT can be manufactured in the same process as the above-described TFT, and can be operated as a diode by connecting the gate wiring layer of the pixel portion and the drain wiring layer or the source wiring layer of the diode.

  Note that any of Embodiment Modes 1 to 10 can be applied to this example. Further, in the first and second embodiments, the liquid crystal display device and the light-emitting display device have been described as examples in the first and second embodiments. However, the present invention is not limited to this, and a DMD (Digital Micromirror Device) may be used. The present invention can be appropriately applied to an active display panel such as a plasma display panel (PDP), a field emission display (FED), and an electrophoretic display device (electronic paper).

  A mode of a light-emitting element applicable in the above embodiment will be described with reference to FIGS.

  In FIG. 21A, the first pixel electrode 11 is formed using a light-transmitting conductive film having a high work function, and the second pixel electrode 17 is formed using a conductive film having a low work function. It is an example. The first pixel electrode 11 is formed of a light-transmitting oxide conductive material, and is typically formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. A layer 16 containing a light emitting material in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked is provided thereon. The second pixel electrode 17 is formed of a first electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or MgAg and a second electrode layer 34 formed of a metal material such as aluminum. A pixel having this structure can emit light from the first pixel electrode 11 side as indicated by an arrow in the figure.

  In FIG. 21B, the first pixel electrode 11 is formed using a conductive film having a high work function, and the second pixel electrode 17 is formed using a light-transmitting conductive film having a low work function. It is an example. The first pixel electrode 11 includes a first electrode layer 35 formed of a metal material such as aluminum or titanium, or a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio of the metal, and silicon oxide 1-15. It is formed in a stacked structure with the second electrode layer 32 formed of an oxide conductive material containing at a concentration of atomic%. A layer 16 containing a light emitting material in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked is provided thereon. The second pixel electrode 17 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF and a fourth electrode layer 34 formed of a metal material such as aluminum. By setting any layer of the second electrode to a thickness of 100 nm or less so that light can be transmitted, it is possible to emit light from the second electrode 17 as indicated by an arrow in the figure. Become.

  FIG. 23E illustrates an example in which light is emitted from both directions, that is, the first electrode and the second electrode. A conductive film having a light-transmitting property and a high work function is formed on the first pixel electrode 11. In addition, a conductive film having translucency and a small work function is used for the second pixel electrode 17. Typically, the first pixel electrode 11 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, and the second pixel electrode 17 is formed of LiF having a thickness of 100 nm or less. As shown by the arrows in the figure, the third electrode layer 33 containing an alkali metal or alkaline earth metal such as CaF or the like and the fourth electrode layer 34 formed of a metal material such as aluminum are used. Light can be emitted from both sides of the first pixel electrode 11 and the second electrode 17.

  In FIG. 21C, the first pixel electrode 11 is formed using a light-transmitting conductive film having a low work function, and the second pixel electrode 17 is formed using a conductive film having a high work function. It is an example. A structure in which a layer containing a light emitting substance is laminated in the order of an electron transport layer or electron injection layer 43, a light emitting layer 42, a hole injection layer or a hole transport layer 41 is shown. The second pixel electrode 17 includes a second electrode layer 32 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic% from the side of the layer 16 containing a light emitting substance, a metal such as aluminum or titanium, Alternatively, the first electrode layer 35 is formed using a stacked structure of a metal material containing nitrogen at a concentration equal to or less than the stoichiometric composition ratio to the metal. The first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF and a fourth electrode layer 34 formed of a metal material such as aluminum. By setting the layer to a thickness of 100 nm or less and allowing light to pass therethrough, light can be emitted from the first pixel electrode 11 as indicated by an arrow in the figure.

  In FIG. 21D, the first pixel electrode 11 is formed using a conductive film having a low work function, and the second pixel electrode 17 is formed using a light-transmitting conductive film having a high work function. It is an example. A structure in which a layer containing a light emitting substance is laminated in the order of an electron transport layer or electron injection layer 43, a light emitting layer 42, a hole injection layer or a hole transport layer 41 is shown. The first pixel electrode 11 has a structure similar to that in FIG. 23A and is formed to have a thickness enough to reflect light emitted from a layer containing a light-emitting substance. The second pixel electrode 17 is made of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. In this structure, the hole injection layer 41 is formed of an inorganic metal oxide (typically molybdenum oxide or vanadium oxide), so that oxygen introduced when the second electrode layer 32 is formed is supplied. Thus, the hole injection property is improved, and the driving voltage can be lowered. In addition, by forming the second pixel electrode 17 with a light-transmitting conductive layer, light can be emitted from both sides of the second electrode 17 as indicated by arrows in the drawing. .

  FIG. 21F illustrates an example in which light is emitted from both directions, that is, the first pixel electrode and the second pixel electrode, and the first pixel electrode 11 has a light-transmitting property and has a small work function. A film is used, and a conductive film having translucency and a large work function is used for the second pixel electrode 17. Typically, the first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF having a thickness of 100 nm or less and a metal material such as aluminum. And the second pixel electrode 17 may be formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%.

  A pixel circuit of the light-emitting display panel described in the above embodiment and an operation configuration thereof will be described with reference to FIGS. There are two types of operation configurations of the light-emitting display panel in which a video signal input to a pixel is defined by a voltage and a current is defined by a current in a display device in which a video signal is digital. There are two types of video signals defined by voltage, one having a constant voltage applied to the light emitting element (CVCV) and one having a constant current applied to the light emitting element (CVCC). In addition, a video signal is defined by current, there are a constant voltage applied to the light emitting element (CCCV) and a constant current applied to the light emitting element (CCCC). In this embodiment, a pixel that performs CVCV operation will be described with reference to FIGS. A pixel that performs the CVCC operation will be described with reference to FIGS.

  In the pixel shown in FIGS. 22A and 22B, a signal line 3710 and a power supply line 3711 are arranged in the column direction, and a scanning line 3714 is arranged in the row direction. In addition, the pixel includes a switching TFT 3701, a driving TFT 3703, a capacitor element 3702, and a light emitting element 3705.

  Note that the switching TFT 3701 and the driving TFT 3703 operate in a linear region when turned on. The driving TFT 3703 has a role of controlling whether or not a voltage is applied to the light emitting element 3705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. In this embodiment, the switching TFT 3701 is an n-channel TFT and the driving TFT 3703 is a p-channel TFT. The driving TFT 3703 may be a depletion type TFT as well as an enhancement type. The ratio (W / L) of the channel width W to the channel length L (W / L) of the driving TFT 3703 is preferably 1 to 1000 depending on the mobility of the TFT. The larger the W / L, the better the electrical characteristics of the TFT.

  In the pixels shown in FIGS. 22A and 22B, a switching TFT 3701 controls input of a video signal to the pixel. When the switching TFT 3701 is turned on, a video signal is input into the pixel. Then, the voltage of the video signal is held in the capacitor 3702.

  22A, in the case where the power supply line 3711 is Vss and the counter electrode of the light emitting element 3705 is Vdd, that is, in FIGS. 21C and 21D, the counter electrode of the light emitting element is an anode, and the driving TFT 3703 The electrode connected to is a cathode. In this case, luminance unevenness due to characteristic variations of the driving TFT 3703 can be suppressed.

  22A, in the case where the power supply line 3711 is Vdd and the counter electrode of the light emitting element 3705 is Vss, that is, in FIGS. 21A and 21B, the counter electrode of the light emitting element is a cathode, and the driving TFT 3703 The electrode connected to is the anode. In this case, when a video signal having a voltage higher than Vdd is input to the signal line 3710, the voltage of the video signal is held in the capacitor 3702, and the driving TFT 3703 operates in a linear region. It is possible to improve.

  The pixel shown in FIG. 22B has the same pixel structure as that shown in FIG. 24A except that a TFT 3706 and a scanning line 3715 are added.

  The TFT 3706 is controlled to be turned on or off by a newly arranged scanning line 3715. When the TFT 3706 is turned on, the charge held in the capacitor 3702 is discharged, and the TFT 3703 is turned off. That is, the arrangement of the TFT 3706 can forcibly create a state in which no current flows through the light emitting element 3705. Therefore, the TFT 3706 can be called an erasing TFT. Therefore, the structure in FIG. 24B can improve the light emission duty ratio because the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels. Is possible.

  In the pixel having the above operation configuration, the current value of the light-emitting element 3705 can be determined by the driving TFT 3703 that operates in a linear region. With the above structure, variation in TFT characteristics can be suppressed, and luminance unevenness of a light-emitting element due to variation in TFT characteristics can be improved, so that a display device with improved image quality can be provided.

  Next, a pixel that performs the CVCC operation will be described with reference to FIGS. A pixel illustrated in FIG. 22C is provided with a power supply line 3712 and a current control TFT 3704 in the pixel configuration illustrated in FIG.

  The pixel shown in FIG. 22E is different from the pixel shown in FIG. 22C in that the gate electrode of the driving TFT 3703 is connected to the power supply line 3712 arranged in the row direction. It is a configuration. That is, both pixels shown in FIGS. 22C and 22E show the same equivalent circuit diagram. However, in the case where the power supply line 3712 is arranged in the row direction (FIG. 22C) and in the case where the power supply line 3712 is arranged in the column direction (FIG. 22E), each power supply line has a different layer. It is formed of a conductive film. Here, attention is paid to the wiring to which the gate electrode of the driving TFT 3703 is connected, and FIGS. 22C and 22E are shown separately to show that the layers for manufacturing these are different.

  Note that the switching TFT 3701 operates in a linear region, and the driving TFT 3703 operates in a saturation region. The driving TFT 3703 has a role of controlling a current value flowing through the light emitting element 3705, and the current controlling TFT 3704 has a role of operating in a saturation region and controlling supply of current to the light emitting element 3705.

  The pixels shown in FIGS. 22D and 22F are the same as those shown in FIGS. 22C and 22E, respectively, except that an erasing TFT 3706 and a scanning line 3715 are added. The pixel configuration is the same as that shown in E).

Note that the CVCC operation can also be performed in the pixels shown in FIGS. 22A and 22B. In addition, in the pixel having the operation configuration shown in FIGS. 22C to 22F, Vdd and Vss are appropriately changed depending on the direction of current flow of the light-emitting element, as in FIGS. 22A and 22B. Is possible.

  In the pixel having the above structure, since the current control TFT 3704 operates in a linear region, a slight change in Vgs of the current control TFT 3704 does not affect the current value of the light emitting element 3705. That is, the current value of the light emitting element 3705 can be determined by the driving TFT 3703 operating in the saturation region. With the above structure, it is possible to provide a display device in which luminance unevenness of a light-emitting element due to variation in TFT characteristics is improved and image quality is improved.

  In particular, in the case of forming a thin film transistor having an amorphous semiconductor or the like, it is preferable to increase the area of the semiconductor film of the driving TFT because the variation of the TFT can be reduced. Therefore, the pixel shown in FIGS. 22A and 22B can increase the aperture ratio because the number of TFTs is small.

  Note that although a structure including the capacitor 3702 is shown, the present invention is not limited to this, and the capacitor 3702 is not provided in the case where the capacity for holding a video signal can be covered by a gate capacitor or the like. May be.

  In addition, when the semiconductor region of the thin film transistor is formed using an amorphous semiconductor film, a threshold value is likely to shift. Therefore, a circuit for correcting the threshold value is preferably provided in the pixel or the periphery of the pixel portion.

  Such an active matrix light-emitting device is considered to be advantageous because it can be driven at a low voltage because a TFT is provided in each pixel when the pixel density is increased. On the other hand, a passive matrix light-emitting device in which a TFT is provided for each column can be formed. A passive matrix light-emitting device has a high aperture ratio because a TFT is not provided for each pixel.

  In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

  As described above, various pixel circuits can be employed.

  In this embodiment, mounting of a driver circuit on the display panel described in the above embodiment will be described with reference to FIGS.

  As shown in FIG. 23A, a signal line driver circuit 1402 and scan line driver circuits 1403a and 1403b are mounted around the pixel portion 1401. In FIG. 23A, as a signal line driver circuit 1402 and scan line driver circuits 1403a and 1403b, a mounting method using a known anisotropic conductive adhesive and anisotropic conductive film, a COG method, wire bonding, and the like. The IC chip 1405 is mounted on the substrate 1400 by a method, a reflow process using a solder bump, or the like. Here, the COG method is used. Then, an IC chip and an external circuit are connected via an FPC (flexible printed circuit) 1406. Further, a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted with an IC chip.

  Further, as shown in FIG. 23B, when a semiconductor element typified by a TFT such as a SAS or a crystalline semiconductor is formed, the pixel portion 1401 and the scan line driver circuits 1403a and 1403b are integrally formed over the substrate. In some cases, the signal line driver circuit 1402 or the like is separately mounted as an IC chip. In FIG. 23B, an IC chip 1405 is mounted on a substrate 1400 as a signal line driver circuit 1402 by a COG method. Then, the IC chip and an external circuit are connected through the FPC 1406. Further, a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted with an IC chip.

  Further, as shown in FIG. 23C, the signal line driver circuit 1402 and the like may be mounted by a TAB method instead of the COG method. Then, the IC chip and an external circuit are connected through the FPC 1406. In FIG. 23C, the signal line driver circuit is mounted by a TAB method; however, the scan line driver circuit may be mounted by a TAB method. Further, a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted with an IC chip.

  When the IC chip is mounted by the TAB method, a pixel portion can be provided larger than the substrate, and a narrow frame can be achieved.

  The IC chip is formed using a silicon wafer, but an IC (hereinafter referred to as a driver IC) in which an IC is formed on a glass substrate may be provided instead of the IC chip. Since an IC chip is taken out from a circular silicon wafer, the shape of the base substrate is limited. On the other hand, the driver IC has a mother substrate made of glass and has no restriction in shape, so that productivity can be improved. Therefore, the shape of the driver IC can be set freely. For example, when the length of the long side of the driver IC is 15 to 80 mm, the required number can be reduced as compared with the case where the IC chip is mounted. As a result, the number of connection terminals can be reduced, and the manufacturing yield can be improved.

  The driver IC can be formed using a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiation with continuous wave laser light. A semiconductor film obtained by irradiation with continuous wave laser light has few crystal defects and large crystal grains. As a result, a transistor having such a semiconductor film has favorable mobility and response speed, can be driven at high speed, and is suitable for a driver IC.

  In this embodiment, a display module will be described. Here, a liquid crystal module is shown as an example of a display module with reference to FIG.

  An active matrix substrate 1601 and a counter substrate 1602 are fixed to each other with a sealant 1600, and a pixel portion 1603 and a liquid crystal layer 1604 are provided therebetween to form a display region.

  The colored layer 1605 is necessary when performing color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Polarizers 1606 and 1607 are disposed outside the active matrix substrate 1601 and the counter substrate 1602. In addition, a protective film 1616 is formed on the surface of the polarizing plate 1606 to reduce external impact.

  A wiring board 1610 is connected to a connection terminal 1608 provided on the active matrix substrate 1601 through an FPC 1609. The wiring board 1610 incorporates a pixel drive circuit (IC chip, driver IC, etc.), an external circuit 1612 such as a control circuit and a power supply circuit.

  The cold cathode tube 1613, the reflecting plate 1614, and the optical film 1615 are backlight units, which serve as light sources and project light onto the liquid crystal display panel. A liquid crystal panel, a light source, a wiring board, an FPC, and the like are held and protected by a bezel 1617.

  Note that any of Embodiment Modes 1 to 10 can be applied to this example.

  In this embodiment, as an example of a display panel, the appearance of a light-emitting display panel will be described with reference to FIG. FIG. 20A is a top view of a panel in which a space between a first substrate and a second substrate is sealed with a first sealant 1205 and a second sealant 1206. FIG. ) Corresponds to cross-sectional views taken along lines AA ′ and BB ′ in FIG.

  In FIG. 20A, 1202 indicated by a dotted line is a pixel portion, and 1203 is a scanning line (gate line) driving circuit. In this embodiment, the pixel portion 1202 and the scanning line driver circuit 1203 are in a region sealed with a first sealing material and a second sealing material. Reference numeral 1201 denotes a signal line (source line) drive circuit, and a chip-like signal line drive circuit is provided on the first substrate 1200. As the first sealing material, it is preferable to use a highly viscous epoxy resin containing a filler. As the second sealing material, it is preferable to use an epoxy resin having a low viscosity. In addition, the first sealing material 1205 and the second sealing material are desirably materials that do not transmit moisture and oxygen as much as possible.

Further, a desiccant may be provided between the pixel portion 1202 and the sealant 1205. Further, in the pixel portion, a desiccant may be provided on the scan line or the signal line. As the desiccant, it is preferable to use a substance that adsorbs water (H ₂ O) by chemical adsorption such as an oxide of an alkaline earth metal such as calcium oxide (CaO) or barium oxide (BaO). However, the present invention is not limited to this, and a substance that adsorbs water by physical adsorption such as zeolite or silica gel may be used.

  In addition, the resin can be fixed to the second substrate 1204 in a state where a highly moisture-permeable resin contains a granular material of a desiccant. Here, examples of the highly moisture-permeable resin include acrylic resins such as ester acrylate, ether acrylate, ester urethane acrylate, ether urethane acrylate, butadiene urethane acrylate, special urethane acrylate, epoxy acrylate, amino resin acrylate, and acrylic resin acrylate. Can be used. In addition, bisphenol A type liquid resin, bisphenol A type solid resin, bromine-containing epoxy resin, bisphenol F type resin, bisphenol AD type resin, phenol type resin, cresol type resin, novolac type resin, cyclic aliphatic epoxy resin, epibis type Epoxy resins such as epoxy resins, glycidyl ester resins, glycidylamine resins, heterocyclic epoxy resins, and modified epoxy resins can be used. Further, other substances may be used. Further, for example, inorganic substances such as siloxane polymer, polyimide, PSG (phosphorus glass), BPSG (phosphorus boron glass), and the like may be used.

  You may provide a desiccant in the area | region which overlaps with a scanning line. Furthermore, you may fix to the 2nd board | substrate in the state which included the granular substance of the desiccant in resin with high moisture permeability. By providing these desiccants, it is possible to suppress the intrusion of moisture into the display element and the deterioration caused thereby without reducing the aperture ratio. For this reason, it is possible to suppress variations in deterioration of the light emitting elements in the peripheral portion and the central portion of the pixel portion 1202.

  Note that reference numeral 1210 denotes a connection wiring for transmitting signals input to the signal line driver circuit 1201 and the scanning line driver circuit 1203, from an FPC (flexible printed wiring) 1209 serving as an external input terminal via a connection wiring 1208. Receive video and clock signals.

  Next, a cross-sectional structure will be described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1200, and includes a plurality of semiconductor elements typified by TFTs. A signal line driver circuit 1201 and a pixel portion 1202 are shown as driver circuits. Note that as the signal line driver circuit 1201, a CMOS circuit in which an n-channel TFT 1221 and a p-channel TFT 1222 are combined is formed.

  In this embodiment, the scanning line driving circuit and the TFT of the pixel portion are formed on the same substrate. For this reason, the volume of the light emitting display device can be reduced.

  The pixel portion 1202 is formed of a plurality of pixels including a switching TFT 1211, a driving TFT 1212, and a first pixel electrode (anode) 1213 made of a reflective conductive film electrically connected to the drain thereof. .

  In addition, insulators (called banks, partition walls, barriers, banks, or the like) 1214 are formed at both ends of the first pixel electrode (anode) 1213. In order to improve the coverage (coverage) of the film formed over the insulator 1214, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 1214. The surface of the insulator 1214 may be covered with a protective film formed of an aluminum nitride film, an aluminum nitride oxide film, a thin film containing carbon as its main component, or a silicon nitride film. Further, by using an organic material obtained by dissolving or dispersing a material that absorbs visible light, such as a black pigment or a dye, as the insulator 1214, stray light from a light-emitting element to be formed later can be absorbed. As a result, the contrast of each element is improved.

  Further, an organic compound material is deposited on the first pixel electrode (anode) 1213 to selectively form a layer 1215 containing a light-emitting substance. Further, a second pixel electrode (cathode) is formed over the layer 1215 containing a light-emitting substance.

  For the layer 1215 containing a light-emitting substance, the structure shown in Embodiment 3 can be used as appropriate.

  In this manner, a light-emitting element 1217 including the first pixel electrode (anode) 1213, the layer 1215 containing a light-emitting substance, and the second pixel electrode (cathode) 1216 is formed. The light-emitting element 1217 emits light toward the second substrate 1204 side.

In addition, a protective stack 1218 is formed in order to seal the light emitting element 1217. The protective laminate includes a laminate of a first inorganic insulating film, a stress relaxation film, and a second inorganic insulating film. Next, the protective laminate 1218 and the second substrate 1204 are bonded with the first sealant 1205 and the second sealant 1206. Note that the second sealant is preferably dropped using a device for dropping the sealant. After the sealing material is dropped or discharged from the dispenser to apply the sealing material onto the active matrix substrate, the second substrate and the active matrix substrate are bonded together in a vacuum and then cured by ultraviolet curing. it can.

  Note that an antireflection film 1226 is provided on the surface of the second substrate 1204 to prevent external light from being reflected by the substrate surface. One or both of a polarizing plate and a retardation plate may be provided between the second substrate and the antireflection film. By providing the retardation plate and the polarizing plate 1225, it is possible to prevent external light from being reflected by the pixel electrode. Note that the first pixel electrode 1213 and the second pixel electrode 1216 are formed using a light-transmitting conductive film or a semi-transparent conductive film, and the interlayer insulating film 1214 absorbs visible light, or When an organic material formed by dissolving or dispersing a material that absorbs visible light is used, external light is not reflected by each pixel electrode, so that a retardation plate and a polarizing plate may not be used.

  The connection wiring 1208 and the FPC 1209 are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1227. Furthermore, it is preferable that the connection portion between each wiring layer and the connection terminal is sealed with a sealing resin. With this structure, moisture from the cross section can be prevented from entering and deteriorating the light emitting element.

  Note that a space filled with an inert gas such as nitrogen gas may be provided between the second substrate 1204 and the protective laminate 1218 instead of the second sealant 1206. It is possible to enhance prevention of moisture and oxygen from entering.

In addition, a colored layer can be provided between the second substrate and the polarizing plate 1225. In this case, a full color display can be performed by providing a light emitting element capable of emitting white light in the pixel portion and separately providing a colored layer showing RGB. Further, full color display can be performed by providing a light emitting element capable of emitting blue light in the pixel portion and separately providing a color conversion layer or the like. Furthermore, each pixel portion, a light emitting element that emits red, green, and blue light can be formed, and a colored layer can be used. Such a display module has high color purity of each RBG and enables high-definition display.

  Alternatively, the light-emitting display module may be formed using one of the first substrate 1200 and the second substrate 1204, or a substrate such as a film or resin. When sealing is performed without using the counter substrate in this manner, the weight, size, and thickness of the display device can be improved.

  Furthermore, an IC chip such as a controller, a memory, and a pixel driver circuit may be provided on the surface or end of an FPC (flexible printed wiring) 1209 that serves as an external input terminal to form a light emitting display module.

  Note that any of Embodiment Modes 1 to 10 can be applied to this example. Moreover, although the example of the liquid crystal display module and the light emission display module was shown as a display module, it is not restricted to this, DMD (Digital Micromirror Device; Digital micromirror device), PDP (Plasma Display Panel; Plasma display panel), The present invention can be appropriately applied to display modules such as FED (Field Emission Display) and electrophoretic display devices (electronic paper).

  As an electronic device in which the display device described in the above embodiment is incorporated in a housing, a television device (also simply referred to as a television or a television receiver), a digital camera, a digital video camera, a mobile phone device (simply a mobile phone or a mobile phone) Also, a portable information terminal such as a PDA, a portable game machine, a computer monitor, a computer, an audio reproduction device such as a car audio, and an image reproduction device including a recording medium such as a home game machine. A specific example will be described with reference to FIG.

  A portable information terminal illustrated in FIG. 24A includes a main body 9201, a display portion 9202, and the like. As the display portion 9202, any of those shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a portable information terminal capable of high-quality display can be provided at low cost.

  A digital video camera shown in FIG. 24B includes a display portion 9701, a display portion 9702, and the like. As the display portion 9701, any of those shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a digital video camera capable of high-quality display can be provided at low cost.

  A portable terminal illustrated in FIG. 24C includes a main body 9101, a display portion 9102, and the like. As the display portion 9102, the display modes in Embodiment Modes 1 to 10 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a portable terminal capable of high-quality display can be provided at low cost.

  A portable television device shown in FIG. 24D includes a main body 9301, a display portion 9302, and the like. As the display portion 9302, the display portions shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a portable television device capable of high-quality display can be provided at low cost. Such a television device can be widely applied from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). .

  A portable computer shown in FIG. 24E includes a main body 9401, a display portion 9402, and the like. As the display portion 9402, any of those shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a portable computer capable of high-quality display can be provided at low cost.

  A television device illustrated in FIG. 24F includes a main body 9501, a display portion 9502, and the like. As the display portion 9502, the display portions shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a television device capable of high-quality display can be provided at low cost.

  Among the electronic devices listed above, those using a secondary battery can extend the usage time of the electronic device as much as power consumption is reduced, and can save the trouble of charging the secondary battery.

8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. Sectional drawing explaining the element profile in the semiconductor film of the semiconductor device which concerns on this invention. Sectional drawing explaining the element profile in the semiconductor film of the semiconductor device which concerns on this invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 6 is a plan view illustrating a structure of a semiconductor device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating the structure of a semiconductor device according to the invention. Sectional drawing explaining the structure of the liquid crystal display module which concerns on this invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 6 is a plan view illustrating a structure of a semiconductor device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating the structure of a semiconductor device according to the invention. 4A and 4B each illustrate a mode of a light-emitting element that can be applied to the present invention. 4A and 4B each illustrate a circuit of a light-emitting element that can be applied to the present invention. 4A and 4B illustrate a mounting method of a drive circuit applicable to the present invention. 10A and 10B each illustrate an example of an electronic device. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. Sectional drawing explaining the crystallization process applicable to this invention. Sectional drawing and top view explaining the crystallization process applicable to this invention. The top view explaining the drive circuit applicable to this invention.

Claims (6)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Adding a catalytic element to the first semiconductor film and then heating to form a first crystalline semiconductor film;
After forming a second semiconductor film having an impurity element over the first crystalline semiconductor film, the first crystal semiconductor film and the second semiconductor film are heated , whereby the first crystal Moving the catalytic element contained in the crystalline semiconductor film to the second semiconductor film, forming a second crystalline semiconductor film and a third crystalline semiconductor film,
Etching the second crystalline semiconductor film and the third crystalline semiconductor film to form a first semiconductor region and a second semiconductor region;
Forming a source electrode and a drain electrode in contact with the second semiconductor region;
A method for manufacturing a semiconductor device, wherein the exposed portion of the second semiconductor region is etched using the source electrode and the drain electrode as a mask to form a source region and a drain region.   2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity element is an element selected from phosphorus, nitrogen, arsenic, antimony, and bismuth. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Adding a catalytic element to the first semiconductor film and then heating to form a first crystalline semiconductor film;
After the second semiconductor film containing a rare gas element is formed over the first crystalline semiconductor film, the first crystalline semiconductor film and the second semiconductor film are heated, whereby the first crystalline semiconductor film and the second semiconductor film are heated . Moving the catalytic element contained in the crystalline semiconductor film to the second semiconductor film, forming a second crystalline semiconductor film and a third crystalline semiconductor film;
Removing the third crystalline semiconductor film;
Forming a conductive third semiconductor film on the second crystalline semiconductor film;
Etching the second crystalline semiconductor film and the third semiconductor film to form a first semiconductor region and a second semiconductor region;
Forming a source electrode and a drain electrode in contact with the second semiconductor region;
A method for manufacturing a semiconductor device, wherein the exposed portion of the second semiconductor region is etched using the source electrode and the drain electrode as a mask to form a source region and a drain region.   4. The method for manufacturing a semiconductor device according to claim 3, wherein the third semiconductor film having conductivity includes a group 13 element or a group 15 element. 5. The method for manufacturing a semiconductor device according to claim 3 , wherein the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe. In any one of claims 1 to 5, wherein the catalyst element, characterized tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, and that it is one or more selected from platinum A method for manufacturing a semiconductor device.

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