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JP4573412B2 - Semiconductor device - Google Patents

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Publication number
JP4573412B2
JP4573412B2 JP2000264782A JP2000264782A JP4573412B2 JP 4573412 B2 JP4573412 B2 JP 4573412B2 JP 2000264782 A JP2000264782 A JP 2000264782A JP 2000264782 A JP2000264782 A JP 2000264782A JP 4573412 B2 JP4573412 B2 JP 4573412B2
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Prior art keywords
semiconductor device
substrate
wiring pattern
semiconductor
chip
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JP2002076160A (en
Inventor
修 宮田
一郎 岸本
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【０００１】
【産業上の利用分野】
この発明は、半導体装置および基板に関し、特にたとえばモールド樹脂によりパッケージされる、半導体装置およびそのような半導体装置に適用される基板に関する。
【０００２】
【従来の技術】
図１２（Ａ）に示すこの種の従来の半導体装置１では、配線パターン２が形成された基板３上にメッキ用のレジスト４が形成され、配線パターン２の所定箇所にＮｉメッキおよびＡｕメッキが施され、レジスト４上にダイボンディングシート５を介して半導体チップ６がダイボンディングされていた。そして、半導体チップ６の上面電極６ａと配線パターン２のボンディングパッド２ａとが金線７によりワイヤボンディングされ、半導体チップ６および金線７等がモールド樹脂８により封止されていた。
【０００３】
【発明が解決しようとする課題】
従来技術では、耐パッケージクラック性が低く、このパッケージクラック性を向上させるためには、レジスト４をなくし、基板３の貫通孔から圧力を逃す必要ががあった。そこで、図１２（Ｂ）に示すように、レジスト４を除去し、基板３にベントホール３ａを設けている。ただし、この場合には、ダイボンディングシート５の下に配線パターン２の厚さに応じた隙間９が生じ、この隙間９にモールド樹脂８が入り込むため、半導体チップ６が基板３から剥離されるおそれがあったり、圧力を逃すためのベントホール３ａを埋めてしまうおそれがあった。
【０００４】
それゆえに、この発明の主たる目的は、半導体チップの剥離を生じることなく高信頼性を保つことができる、半導体装置および基板を提供することである。
【０００５】
【課題を解決するための手段】
この発明は、複数の配線パターンが形成されたチップエリアを有する基板と、チップエリア内において基板に形成された複数のベントホールと、チップエリア上にダイボンディングシートを用いてダイボンディングされた半導体チップと、半導体チップを封止するモールド樹脂とを備える、半導体装置において、平面視におけるベントホールが形成された領域と半導体チップの外形線との間において、全ての隣り合う配線パターンどうしの間隔がそれぞれ０．１７５ｍｍ以下の箇所を有することを特徴とする、半導体装置である。
【０００７】
【作用】
基板の配線パターン上にダイボンディングシート等を介して半導体チップがダイボンディングされ、半導体チップがモールド樹脂により封止される。平面視におけるベントホールが形成された領域と半導体チップの外形線との間において、全ての隣り合う配線パターンどうしの間隔がそれぞれ０．１７５ｍｍ以下の箇所を有するので、配線パターンの間から半導体チップの下にモールド樹脂が入り込む心配はない。なお、「０．１７５ｍｍ以下」という条件は、モールド樹脂が入り込まない条件として、発明者が実験により求めたものである。
【０００８】
【発明の効果】
この発明によれば、基板上にレジストを形成することなく、半導体チップの下にモールド樹脂が入り込むのを防止できる。したがって、半導体チップの剥離を生じることなく製造コストを低減できる。
【０００９】
この発明の上述の目的，その他の目的，特徴および利点は、図面を参照して行う以下の実施例の詳細な説明から一層明らかとなろう。
【００１０】
【実施例】
図１に示すこの実施例の半導体装置１０は、基板１２の上面にダイボンディングシート１４を介してダイボンディングされた半導体チップ１６をモールド樹脂１８によりパッケージしたものであり、いわゆるＢＧＡ（Ball Grid Array ）型と称されるものである。
【００１１】
基板１２は、ポリイミド，ガラスエポキシまたはセラミック等のような絶縁材料からなり、この基板１２のダイボンディングエリア１２ａには、複数のスルーホール２０が行列状に形成され、チップエリア１２ｂには、複数のベントホール２２が行列状に形成される。ここで、原則として、「ダイボンディングエリア（１２ａ）」とは、異なるサイズの複数の半導体チップ１６が選択的にダイボンディングされる領域をいい、「チップエリア（１２ｂ）」とは、ダイボンディングエリア１２ａ内において半導体チップ１６が実際にダイボンディングされる領域をいうものとする。
【００１２】
そして、基板１２の上面には、図２および図３に示すように、複数の配線パターン２４および複数の流入阻止部２６が形成される。なお、図２は、配線パターン１４の中間部分を省略して示したものであり、図３は、図２の１／４の範囲を拡大して示したものである。
【００１３】
配線パターン２４は、Ｃｕ等のような導電性金属からなり、各配線パターン２４の一端はスルーホール２０の上端を閉塞するように配置され、他端は基板１２の周縁部に配置され、この他端がボンディングパッド２４ａとされる。
【００１４】
配線パターン２４上に半導体チップ１６をダイボンディングしたとき、半導体チップ１６の外形線近傍にある配線パターン２４どうしの間隔Ａ（図３）が広過ぎると、そこから半導体チップ１６の下にモールド樹脂１８が入り込んで半導体チップ１６が剥離されるおそれがある。そして、発明者の実験によれば、図４に示すように、間隔Ａが０．１７５ｍｍより広いときに剥離による不良が発生することが分かった。そこで、この実施例では、半導体チップ１６の下にモールド樹脂１８が入り込むのを阻止するために、ダイボンディングエリア１２ａにおける配線パターン２４の間隔Ａが０．１７５ｍｍ以下に設定される。ただし、安全率を考慮すると、間隔Ａは０．１７０ｍｍ以下であることが望ましい。
【００１５】
流入阻止部２６は、ベントホール２２へモールド樹脂１８が流入するのを阻止するとともに、モールド１８ａ内の空気や水をベントホール２２へ導くためのものであり、図５に示すように、ベントホール２２の周囲に配線パターン２４と同じ厚さで環状に形成される。そして、流入阻止部２６において、チップエリア１２ｂの中央側すなわちモールド樹脂１８の流れの下流側に位置する部分には、その内側領域と外側領域とを連通する２つの切欠２８ａが形成される。切欠２８ａの形成位置は、モールド樹脂１８の流れを阻止する機能と空気や水を放出する機能とのバランスを考慮して、流入阻止部２６の形成位置に応じて設定される。また、切欠２８ａの幅も、モールド樹脂１８の流れを阻止するためには、０．１７５ｍｍ以下に設定される。
【００１６】
そして、これらの配線パターン２４および流入阻止部２６の上に、ダイボンディングシート１４を介して半導体チップ１６がダイボンディングされ、半導体チップ１６の上面電極１６ａと配線パターン２４のボンディングパッド２４ａとが金線２８を介してワイヤボンディングされ、半導体チップ１６および各金線２８がモールド樹脂１８により封止される。
【００１７】
さらに、基板１２の下面に開口された各スルーホール２０には、ボール状の外部端子３０が取り付けられ、各外部端子３０と配線パターン２４とが電気的に接続される。
【００１８】
半導体装置１０を製造する際には、まず、図６に示すように、ポリイミド等からなる帯状のキャリアフィルム３２を準備し、キャリアフィルム３２の表面に配線パターン２４および流入阻止部２６を形成する。つまり、キャリアフィルム３２の表面にＣｕ箔を形成し、このＣｕ箔上に配線パターン２４および流入阻止部２６の形状に応じてエッチング用のレジストを形成し、Ｃｕ箔の不要部分をエッチングにより除去する。
【００１９】
そして、レジストを除去した後、キャリアフィルム３２のダイボンディングエリア１２ａにスルーホール２０を形成し、チップエリア１２ｂに形成された流入阻止部２６の内側にベントホール２２を形成する。
【００２０】
そして、チップエリア１２ｂにダイボンディングシート１４を介して半導体チップ１６をダイボンディングし、半導体チップ１６の上面電極１６ａと配線パターン２４のボンディングパッド２４ａとを金線２８を用いてワイヤボンディングする。
【００２１】
その後、半導体チップ１６および金線２８等をモールド樹脂１８で封止し、各スルーホール２０に外部端子３０を装着し、キャリアフィルム３２を切断分割して半導体装置１０を得る。
【００２２】
モールド工程では、キャリアフィルム３２（基板１２）の上面とダイボンディングシート１４の下面との間に配線パターン２４の厚さに応じた隙間が生じるが、上述したように、配線パターン２４どうしの間隔Ａは０．１７５ｍｍ以下に設定されているので、その隙間にモールド樹脂１８が入り込む心配はない。また、たとえ入り込んだとしても、そのモールド樹脂１８は流入阻止部２６により阻止されるので、ベントホール２２が閉塞される心配はない。
【００２３】
この実施例によれば、半導体チップ１６が基板１２から剥離されるのを防止できる。また、ベントホール２２がモールド樹脂１８により塞がれるのを防止できるとともに、モールド１８ａ内に溜まった空気や水をベントホール２２から外部へ放出できるので、これらの空気や水が熱膨張することによるパッケージクラックの発生を防止できる。
【００２４】
なお、チップエリア１２ｂの範囲は半導体チップ１６のサイズに応じて適宜変更可能であり、たとえば図７に示すように、より小さい半導体チップ１６に対応させて、より狭い範囲をチップエリア１２ｂとして設定してもよい。
【００２５】
また、基板１２に対して半導体チップ１６が１種類のみ適用される場合には、ダイボンディングエリア１２ａとチップエリア１２ｂとが一致するが、この場合には、たとえば図８および図９に示すように、チップエリア１２ｂ（ダイボンディングエリア１２ａ）の全域における配線パターン２４どうしの間隔Ａを０．１７５ｍｍ以下に設定してもよいし、たとえば図１０および図１１に示すように、半導体チップ１６の外形線近傍における配線パターン２４どうしの間隔Ａのみを０．１７５ｍｍ以下に設定してもよい。つまり、この発明の特徴は、少なくとも半導体チップ１６の外形線近傍における配線パターン２４どうしの間隔Ａを０．１７５ｍｍ以下に設定した点にある。
【００２６】
そして、各流入阻止部２６における切欠２８ａの数は適宜変更されてもよいし、各流入阻止部２６の形成位置はより広い範囲に設定されてもよい。また、チップエリア１２ｂ内に存在する任意の流入阻止部２６についてのみベントホール２２を形成してもよい。
【００２７】
さらに、配線パターン２４どうしの間隔Ａを０．１７５ｍｍ以下に設定することにより、半導体チップ１６の下にモールド樹脂１８が入り込むのを確実に阻止できるのであれば、流入阻止部２６は形成されなくてもよい。
【図面の簡単な説明】
【図１】この発明の一実施例を示す図解図である。
【図２】配線パターンおよび流入阻止部を示す図解図である。
【図３】図２の部分拡大図である。
【図４】配線パターンの間隔Ａと不良発生率との関係を示すグラフである。
【図５】流入阻止部を示す図解図である。
【図６】半導体装置の製造方法を示す図解図である。
【図７】より小さい半導体チップを用いた状態を示す図解図である。
【図８】この発明の他の実施例を示す図解図である。
【図９】図８の部分拡大図である。
【図１０】この発明の他の実施例を示す図解図である。
【図１１】図１０の部分拡大図である。
【図１２】従来技術を示す図解図である。
【符号の説明】
１０ …半導体装置
１２ …基板
１４ …ダイボンディングシート
１６ …半導体チップ
１８ …モールド樹脂
２０ …スルーホール
２２ …ベントホール
２４ …配線パターン
２６ …流入阻止部[0001]
[Industrial application fields]
The present invention relates to a semiconductor device and a substrate, and more particularly to a semiconductor device packaged by, for example, a mold resin and a substrate applied to such a semiconductor device.
[0002]
[Prior art]
In this type of conventional semiconductor device 1 shown in FIG. 12A, a resist 4 for plating is formed on a substrate 3 on which a wiring pattern 2 is formed, and Ni plating and Au plating are applied to predetermined portions of the wiring pattern 2. The semiconductor chip 6 was die-bonded on the resist 4 via the die-bonding sheet 5. Then, the upper surface electrode 6a of the semiconductor chip 6 and the bonding pad 2a of the wiring pattern 2 are wire-bonded by the gold wire 7, and the semiconductor chip 6 and the gold wire 7 are sealed by the mold resin 8.
[0003]
[Problems to be solved by the invention]
In the prior art, the package crack resistance is low, and it was necessary to eliminate the resist 4 and release the pressure from the through hole of the substrate 3 in order to improve the package crack resistance. Therefore, as shown in FIG. 12B, the resist 4 is removed, and a vent hole 3 a is provided in the substrate 3. However, in this case, a gap 9 corresponding to the thickness of the wiring pattern 2 is formed under the die bonding sheet 5, and the mold resin 8 enters the gap 9, so that the semiconductor chip 6 may be peeled off from the substrate 3. There is a risk that the vent hole 3a for releasing pressure may be filled.
[0004]
Therefore, a main object of the present invention is to provide a semiconductor device and a substrate that can maintain high reliability without causing peeling of a semiconductor chip.
[0005]
[Means for Solving the Problems]
The present invention relates to a substrate having a chip area in which a plurality of wiring patterns are formed, a plurality of vent holes formed in the substrate in the chip area, and a semiconductor chip die-bonded on the chip area using a die bonding sheet. And a mold resin for sealing the semiconductor chip, in the semiconductor device, between the region where the vent hole is formed in plan view and the outline of the semiconductor chip, the spacing between all adjacent wiring patterns is respectively It is a semiconductor device characterized by having a portion of 0.175 mm or less.
[0007]
[Action]
A semiconductor chip is die-bonded on a wiring pattern of the substrate via a die bonding sheet or the like, and the semiconductor chip is sealed with a mold resin. Between the outline of the region and the semiconductor chip which vent hole is formed in plan view, the interval between every adjacent wiring patterns having a respective 0.175mm or less locations, from between the wiring pattern of the semiconductor chip There is no worry about the mold resin getting underneath. The condition “0.175 mm or less” was obtained by the inventors through experiments as a condition that the mold resin does not enter.
[0008]
【The invention's effect】
According to the present invention, the mold resin can be prevented from entering under the semiconductor chip without forming a resist on the substrate. Therefore, the manufacturing cost can be reduced without causing the semiconductor chip to peel off.
[0009]
The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
[0010]
【Example】
A semiconductor device 10 of this embodiment shown in FIG. 1 is obtained by packaging a semiconductor chip 16 die-bonded on an upper surface of a substrate 12 via a die bonding sheet 14 with a mold resin 18, so-called BGA (Ball Grid Array). It is called a type.
[0011]
The substrate 12 is made of an insulating material such as polyimide, glass epoxy, or ceramic. A plurality of through holes 20 are formed in a matrix in the die bonding area 12a of the substrate 12, and a plurality of through holes 20 are formed in the chip area 12b. The vent holes 22 are formed in a matrix. Here, in principle, the “die bonding area (12a)” refers to an area where a plurality of semiconductor chips 16 having different sizes are selectively die bonded, and the “chip area (12b)” refers to a die bonding area. 12a is a region where the semiconductor chip 16 is actually die-bonded.
[0012]
As shown in FIGS. 2 and 3, a plurality of wiring patterns 24 and a plurality of inflow blocking portions 26 are formed on the upper surface of the substrate 12. 2 shows the wiring pattern 14 with an intermediate portion omitted, and FIG. 3 shows an enlarged range of ¼ of FIG.
[0013]
The wiring pattern 24 is made of a conductive metal such as Cu, and one end of each wiring pattern 24 is disposed so as to close the upper end of the through hole 20, and the other end is disposed on the peripheral edge of the substrate 12. The end is a bonding pad 24a.
[0014]
When the semiconductor chip 16 is die-bonded on the wiring pattern 24, if the distance A (FIG. 3) between the wiring patterns 24 in the vicinity of the outline of the semiconductor chip 16 is too wide, the mold resin 18 is placed under the semiconductor chip 16 from there. May enter and the semiconductor chip 16 may be peeled off. According to the experiment by the inventor, as shown in FIG. 4, it was found that a defect due to peeling occurred when the distance A was wider than 0.175 mm. Therefore, in this embodiment, in order to prevent the mold resin 18 from entering under the semiconductor chip 16, the distance A between the wiring patterns 24 in the die bonding area 12a is set to 0.175 mm or less. However, considering the safety factor, the interval A is desirably 0.170 mm or less.
[0015]
The inflow blocking portion 26 is for blocking the mold resin 18 from flowing into the vent hole 22 and for guiding air and water in the mold 18a to the vent hole 22. As shown in FIG. An annular shape is formed around the periphery of the wire 22 with the same thickness as the wiring pattern 24. In the inflow blocking portion 26, two notches 28a that connect the inner region and the outer region are formed in a portion located on the center side of the chip area 12b, that is, on the downstream side of the flow of the mold resin 18. The formation position of the notch 28a is set according to the formation position of the inflow blocking portion 26 in consideration of the balance between the function of blocking the flow of the mold resin 18 and the function of discharging air and water. The width of the notch 28a is also set to 0.175 mm or less in order to prevent the flow of the mold resin 18.
[0016]
Then, the semiconductor chip 16 is die-bonded on the wiring pattern 24 and the inflow blocking portion 26 via the die bonding sheet 14, and the upper surface electrode 16a of the semiconductor chip 16 and the bonding pad 24a of the wiring pattern 24 are gold wires. The semiconductor chip 16 and the gold wires 28 are sealed with the mold resin 18 through wire bonding through the resin 28.
[0017]
Further, ball-like external terminals 30 are attached to the through holes 20 opened on the lower surface of the substrate 12, and the external terminals 30 and the wiring pattern 24 are electrically connected.
[0018]
When manufacturing the semiconductor device 10, first, as shown in FIG. 6, a band-shaped carrier film 32 made of polyimide or the like is prepared, and the wiring pattern 24 and the inflow blocking portion 26 are formed on the surface of the carrier film 32. That is, a Cu foil is formed on the surface of the carrier film 32, an etching resist is formed on the Cu foil in accordance with the shape of the wiring pattern 24 and the inflow blocking portion 26, and unnecessary portions of the Cu foil are removed by etching. .
[0019]
Then, after removing the resist, a through hole 20 is formed in the die bonding area 12a of the carrier film 32, and a vent hole 22 is formed inside the inflow blocking portion 26 formed in the chip area 12b.
[0020]
Then, the semiconductor chip 16 is die-bonded to the chip area 12b via the die bonding sheet 14, and the upper surface electrode 16a of the semiconductor chip 16 and the bonding pad 24a of the wiring pattern 24 are wire-bonded using the gold wire 28.
[0021]
Thereafter, the semiconductor chip 16 and the gold wire 28 are sealed with the mold resin 18, the external terminals 30 are attached to the respective through holes 20, and the carrier film 32 is cut and divided to obtain the semiconductor device 10.
[0022]
In the molding process, a gap corresponding to the thickness of the wiring pattern 24 is generated between the upper surface of the carrier film 32 (substrate 12) and the lower surface of the die bonding sheet 14, but as described above, the spacing A between the wiring patterns 24 is as follows. Is set to 0.175 mm or less, there is no concern that the mold resin 18 enters the gap. Even if it enters, the mold resin 18 is blocked by the inflow blocking portion 26, so there is no concern that the vent hole 22 is blocked.
[0023]
According to this embodiment, the semiconductor chip 16 can be prevented from being peeled from the substrate 12. Further, the vent hole 22 can be prevented from being blocked by the mold resin 18 and the air and water accumulated in the mold 18a can be discharged from the vent hole 22 to the outside, so that the air and water are thermally expanded. Generation of package cracks can be prevented.
[0024]
The range of the chip area 12b can be appropriately changed according to the size of the semiconductor chip 16. For example, as shown in FIG. 7, a narrower range is set as the chip area 12b corresponding to the smaller semiconductor chip 16. May be.
[0025]
In addition, when only one type of semiconductor chip 16 is applied to the substrate 12, the die bonding area 12a and the chip area 12b coincide with each other. In this case, for example, as shown in FIGS. The interval A between the wiring patterns 24 in the entire chip area 12b (die bonding area 12a) may be set to 0.175 mm or less. For example, as shown in FIGS. 10 and 11, the outline of the semiconductor chip 16 Only the interval A between the wiring patterns 24 in the vicinity may be set to 0.175 mm or less. That is, the present invention is characterized in that the distance A between the wiring patterns 24 in the vicinity of the outline of the semiconductor chip 16 is set to 0.175 mm or less.
[0026]
And the number of the notches 28a in each inflow prevention part 26 may be changed suitably, and the formation position of each inflow prevention part 26 may be set in a wider range. Further, the vent hole 22 may be formed only for an arbitrary inflow blocking portion 26 existing in the chip area 12b.
[0027]
Further, if the interval A between the wiring patterns 24 is set to 0.175 mm or less, and the mold resin 18 can be surely prevented from entering under the semiconductor chip 16, the inflow prevention portion 26 is not formed. Also good.
[Brief description of the drawings]
FIG. 1 is an illustrative view showing one embodiment of the present invention;
FIG. 2 is an illustrative view showing a wiring pattern and an inflow blocking portion.
FIG. 3 is a partially enlarged view of FIG. 2;
FIG. 4 is a graph showing a relationship between a wiring pattern interval A and a defect occurrence rate.
FIG. 5 is an illustrative view showing an inflow blocking portion.
FIG. 6 is an illustrative view showing a method for manufacturing a semiconductor device;
FIG. 7 is an illustrative view showing a state in which a smaller semiconductor chip is used.
FIG. 8 is an illustrative view showing another embodiment of the present invention.
9 is a partially enlarged view of FIG.
FIG. 10 is an illustrative view showing another embodiment of the present invention.
11 is a partially enlarged view of FIG.
FIG. 12 is an illustrative view showing a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Board | substrate 14 ... Die bonding sheet 16 ... Semiconductor chip 18 ... Mold resin 20 ... Through hole 22 ... Vent hole 24 ... Wiring pattern 26 ... Inflow prevention part

Claims (27)

複数の配線パターンが形成されたチップエリアを有する基板と、前記チップエリア内において前記基板に形成された複数のベントホールと、前記チップエリア上にダイボンディングシートを用いてダイボンディングされた半導体チップと、前記半導体チップを封止するモールド樹脂とを備える、半導体装置において、
平面視における前記ベントホールが形成された領域と前記半導体チップの外形線との間において、全ての隣り合う配線パターンどうしの間隔がそれぞれ０．１７５ｍｍ以下の箇所を有することを特徴とする、半導体装置。A substrate having a chip area in which a plurality of wiring patterns are formed; a plurality of vent holes formed in the substrate in the chip area; and a semiconductor chip die-bonded on the chip area using a die bonding sheet; In a semiconductor device comprising a mold resin for sealing the semiconductor chip,
Between the region where the vent hole is formed in plan view and the outline of the semiconductor chip, wherein the interval between every adjacent wiring patterns having a respective 0.175mm following locations, the semiconductor device . 前記基板は異なるサイズの少なくとも２つの前記半導体チップが選択的にダイボンディングされるダイボンディングエリアを有し、前記ダイボンディングエリアの全域において前記間隔を０．１７５ｍｍ以下にしたことを特徴とする、請求項１記載の半導体装置。The substrate has a die bonding area in which at least two semiconductor chips of different sizes are selectively die-bonded, and the interval is 0.175 mm or less in the entire area of the die bonding area. Item 14. A semiconductor device according to Item 1 . 前記半導体装置がＢＧＡ半導体装置であることを特徴とする、請求項１または２記載の半導体装置。Characterized in that said semiconductor device is a BGA semiconductor device, a semiconductor device according to claim 1 or 2 wherein. 前記基板が絶縁材料からなることを特徴する、請求項１ないし３のいずれかに記載の半導体装置。To characterized in that said substrate is made of an insulating material, a semiconductor device according to any one of claims 1 to 3. 前記絶縁材料がポリイミド、ガラスエポキシおよびセラミックのいずれかを含むことを特徴する、請求項４記載の半導体装置。The semiconductor device according to claim 4 , wherein the insulating material includes any one of polyimide, glass epoxy, and ceramic. 前記配線パターンが導電性金属からなることを特徴する、請求項１ないし５のいずれかに記載の半導体装置。The wiring pattern is characterized by comprising a conductive metal, a semiconductor device according to any one of claims 1 to 5. 前記導電性金属がＣｕを含むことを特徴する、請求項６記載の半導体装置。The semiconductor device according to claim 6 , wherein the conductive metal contains Cu. 前記基板がスルーホールを有することを特徴する、請求項１ないし７のいずれかに記載の半導体装置。To wherein the substrate has a through hole, the semiconductor device according to any one of claims 1 to 7. 前記配線パターンの一端が前記スルーホールの上端を閉塞することを特徴する、請求項８記載の半導体装置。9. The semiconductor device according to claim 8 , wherein one end of the wiring pattern closes an upper end of the through hole. 前記配線パターンの他端が前記基板の周縁部に配置されることを特徴する、請求項９記載の半導体装置。The semiconductor device according to claim 9 , wherein the other end of the wiring pattern is disposed on a peripheral portion of the substrate. 前記配線パターンの他端がボンディングパッドであることを特徴する、請求項１０記載の半導体装置。The semiconductor device according to claim 10 , wherein the other end of the wiring pattern is a bonding pad. 前記間隔が０．１７０ｍｍ以下であることを特徴する、請求項１ないし１１のいずれかに記載の半導体装置。To characterized in that said spacing is less than 0.170 mm, the semiconductor device according to any one of claims 1 to 11. 前記スルーホールが行列状に形成されていることを特徴する、請求項８記載の半導体装置。The semiconductor device according to claim 8 , wherein the through holes are formed in a matrix. 前記スルーホールが前記基板の下面に開口されていることを特徴する、請求項８記載の半導体装置。The semiconductor device according to claim 8 , wherein the through hole is opened on a lower surface of the substrate. 前記スルーホールがボール状の外部端子を有することを特徴する、請求項１４記載の半導体装置。The semiconductor device according to claim 14 , wherein the through hole has a ball-shaped external terminal. 前記外部端子が前記配線パターンと電気的に接続されることを特徴する、請求項１５記載の半導体装置。The semiconductor device according to claim 15 , wherein the external terminal is electrically connected to the wiring pattern. 前記ベントホールが行列状に形成されていることを特徴する、請求項１ないし１６のいずれかに記載の半導体装置。To characterized in that said vent holes are formed in a matrix, a semiconductor device according to any one of claims 1 to 16. 前記ベントホールの周囲に複数の流入阻止部を形成したことを特徴する、請求項１ないし１７のいずれかに記載の半導体装置。To characterized by forming a plurality of inlet blocking portion around the vent hole, the semiconductor device according to any one of claims 1 to 17. 前記流入阻止部が前記配線パターンと同じ厚みに形成されることを特徴する、請求項１８記載の半導体装置。The semiconductor device according to claim 18 , wherein the inflow blocking portion is formed to have the same thickness as the wiring pattern. 前記流入阻止部が環状に形成されることを特徴する、請求項１８または１９記載の半導体装置。To characterized in that the inflow preventing part is formed in an annular shape, the semiconductor device according to claim 18 or 19 wherein. 前記流入阻止部が内側領域と外側領域とを連通する切欠きを有することを特徴する、請求項２０記載の半導体装置。21. The semiconductor device according to claim 20 , wherein the inflow blocking portion has a notch communicating the inner region and the outer region. 前記切欠きが２つ以上形成されることを特徴する、請求項２１記載の半導体装置。The semiconductor device according to claim 21 , wherein two or more notches are formed. 前記切欠きの幅が０．１７５ｍｍ以下であることを特徴する、請求項２１または２２記載の半導体装置。The semiconductor device according to claim 21 or 22 , wherein a width of the notch is 0.175 mm or less. 前記半導体チップの上面電極と前記ボンディングパッドとが電気的に接続されることを特徴する、請求項１１記載の半導体装置。12. The semiconductor device according to claim 11 , wherein an upper surface electrode of the semiconductor chip and the bonding pad are electrically connected. 前記半導体チップの上面電極と前記ボンディングパッドとが金線で接続されることを特徴する、請求項２４記載の半導体装置。25. The semiconductor device according to claim 24 , wherein the upper surface electrode of the semiconductor chip and the bonding pad are connected by a gold wire. 前記ボンディングパッドの長手方向と、最も内側に形成される配線パターンの長手方向とが同じであることを特徴する、請求項１ないし２５のいずれかに記載の半導体装置。The longitudinal direction of the bonding pad, the most in the longitudinal direction of the inner wiring pattern to be formed is characterized in that the same, a semiconductor device according to any one of claims 1 to 25. 前記半導体装置の辺から角に近づくにつれて、前記ボンディングパッドの長手方向と前記半導体装置の辺とのなす角度が変化することを特徴する、請求項１ないし２６のいずれかに記載の半導体装置。The closer to the corner from the side of the semiconductor device and wherein the angle between the sides of the longitudinal direction and the semiconductor device of the bonding pad varies semiconductor device according to any one of claims 1 to 26.
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