JP4345201B2 - Wireless communication apparatus having synchronization tracking function - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a radio communication apparatus (base station and terminal), and more particularly to a communication apparatus having a synchronization tracking function used in a code division multiple access (CDMA) mobile communication system.
[0002]
[Prior art]
A conventional CDMA receiver configuration is shown in FIG. The receiver includes a wireless unit 102 and a receiving unit 103 that receive radio waves propagated from the antenna 101 through the wireless propagation path. In the receiving unit 103, first, synchronization of the received signal is established by the synchronization system 105, and despreading, detection processing, and the like by the demodulation system 106 are performed according to the path timing established by the synchronization system 105. After detection, the transmission power control unit 109 determines the bit of the power control bit, and instructs the transmission system 104 to up / down the transmission power. On the other hand, the post-detection data is decoded and detected by the error control system 107, and finally decoded data is transmitted to an upper layer or the like via the interface 108.
[0003]
In a receiver in the CDMA system, it is necessary to establish spreading code synchronization from a spread received signal and perform synchronization tracking in accordance with movement of a terminal or a change in path position.
[0004]
FIG. 2 shows details of the receiver configuration necessary for establishing synchronization and tracking synchronization. In the figure, 201 is a baseband received signal, 202 is a despreading unit in the synchronous system, 203 is an intensity calculating unit in the synchronous system, 204 is a slot averaging unit in the synchronous system, and 205 is a peak in the synchronous system. Detecting unit 206, first finger configuration of demodulating system, 207 second demodulating finger, 208 I-th finger of demodulating system, 209 despreading unit in each finger (On-time, early timing) , Late timing), 210 a detector in each finger, 211 an early timing intensity calculator, 212 a late timing intensity calculator, 213 a difference calculator between the early timing and late timing intensity calculations, and 214 Slot averaging unit, 215 is a timing tracking control (DLL) determination unit, 216 is a timing tracking control unit (DLL control unit), 2 Reference numeral 17 denotes a RAKE combining unit.
[0005]
First, the received signal is despread by the despreading unit 202 of the synchronization system 105. Here, a correlation between the received signal and the spreading code is taken for each received signal sampled in order to find the reception timing. As a result, the profile spread profile of the path in the searched range is output from the despreading unit 202. Next, in order to increase the accuracy of the delay profile, the intensity calculation unit 203 performs in-phase addition. In-phase addition can be performed in a section with a small amount of phase rotation.
[0006]
Further, the slot averaging unit 204 performs power addition between the slots to average the noise. FIG. 4 shows how the power is added. In FIG. 4, when the delay profile at a certain time is 401, high correlation values are output at two points 403 and 404, and there is a possibility that these two points are determined as path timings. When the delay profile at the next certain time is 402, a high correlation value is output at one point 405, and this one point may be determined as a path timing.
[0007]
When power is added to the above two profiles, the dispersion of the correlation value due to noise is averaged, and 404 that was seen as one of the path candidates is just a high correlation value due to the influence of noise. Deviate from the candidates. Therefore, it is possible to increase the probability of finding a correct path by performing power addition.
[0008]
From the profile thus obtained, one or a plurality of paths are extracted by the peak detection unit 205 in accordance with a predetermined algorithm, and the extracted path timing is notified to the despreading unit 209 of the demodulation system finger 206. . When a plurality of paths are extracted, the path timing is notified to each finger 206, 207, 208. Note that the update timing of these path timings is assumed to be about 10 frames and 100 ms.
[0009]
In each demodulation system finger 206, 207, 208, the despreading unit 209 is operated according to the timing of the path extracted in the synchronous system to perform despreading. Further, propagation path estimation is performed to estimate the amount of phase rotation, and the detection unit 210 performs detection based on this value. The post-detection data of each finger is combined at the maximum ratio in the RAKE combining unit 217. Each demodulating finger 206, 207, 208 has a DLL function unit 216 that detects and corrects finger path movement in addition to data demodulation.
[0010]
FIG. 3 shows the configuration of the DLL function. In the figure, 301 is an adder of the slot averaging unit in the DLL control unit, 302 is a delay element of the slot averaging unit in the DLL control unit, and 303 is an example of a DLL determination algorithm.
[0011]
The DLL function unit 216 first despreads 209 and 210 at the timing when the 0.5 chip phase is advanced (early) and the timing when the 0.5 chip phase is delayed (late) with respect to the path timing notified by the synchronous system, respectively. And in-phase addition 211 and 212 is performed. In-phase addition is performed for the number of pilot symbols in one slot.
[0012]
Further, subtraction 213 of the respective in-phase addition results is performed for each slot. If there is no noise, the timing notified in the synchronous system is accurate, and the path does not move, the subtraction result should be zero. On the other hand, when the path moves, the subtraction result is output as a positive or negative value according to the moving direction of the path.
[0013]
Since noise is actually added, the subtraction result is affected by noise. Accordingly, the slot averaging unit 214 performs cumulative averaging for a plurality of slots. The value “DATA” output after the accumulation is input to the DLL control phase shift determination unit 215, and is compared with a preset threshold “TH”.
[0014]
When the accumulated value “DATA” is larger than the threshold value “TH”, this indicates that the (early) component is larger than the (late) component, and the timing of the next despreading is set so that the accumulated value approaches 0. Control to advance the "A" chip is performed (303). On the other hand, when the accumulated value “DATA” is smaller than the minus value “−TH” of the threshold value, this indicates that the (early) component is smaller than the (late) component, so that the accumulated value approaches 0. Next, control is performed to delay the timing of the next despreading by "A" chips (303). Here, “A” is a phase shift amount, and for example, a value of A = 0.25 is used. When the accumulated value “DATA” is other than the above, that is, when the expression “−TH <DATA <TH” is satisfied, it is not necessary to shift the despreading timing. In this case, it is determined that the path has not moved, and the current path timing is maintained (303).
[0015]
These phase shift determinations are performed once per frame. These operations are described as time elapses as shown in FIG. In FIG. 5, the difference 505 between the (early) and (late) in-phase addition results calculated for each slot is added by the power for “S” slots (504, 506), and one frame (501, 502) is based on the addition result. , 503), the DLL determination 507 is performed.
[0016]
[Problems to be solved by the invention]
In a wireless communication system using a code division multiple access method, in order to follow synchronization, it is necessary to accurately update the path timing so as not to cause loss of synchronization.
[0017]
In the conventional example shown in FIG. 2, synchronous tracking is performed by using path timing update for every 10 frames by the synchronous system and timing tracking control by the DLL function, but it is necessary to mount a DLL function for each finger. In addition, since the despreading unit and the like are often configured with hardware for high-speed operation at the chip speed, there is a problem that the circuit scale increases. Furthermore, as shown in FIG. 2, since it is necessary to operate this DLL function for each finger, there is a problem from the viewpoint of power consumption.
[0018]
An object of the present invention is to reduce the scale of a circuit necessary for the communication apparatus for code division multiple access communication without degrading the synchronization tracking characteristic and to reduce power consumption.
[0019]
[Means for Solving the Problems]
In order to solve the above problem, the communication device of the present invention has only one despreading block and an intensity calculation block for performing in-phase addition, and shares this in the course of a plurality of processes, and processes in time division It is characterized by.
[0020]
In order to solve the above problem, the communication device of the present invention has only one despreading block and an intensity calculation block for performing in-phase addition, which is shared by a plurality of fingers and processed in a time division manner. Timing follow-up control DLL control for a plurality of fingers is performed.
[0021]
In order to solve the above problem, the communication device of the present invention has only one despreading block and an intensity calculation block that performs in-phase addition, and a plurality of reception units that process a plurality of antenna patterns when the transmission diversity technique is applied. This is shared by machines, and the timing tracking control DLL control for a plurality of antennas is performed by processing in time division.
[0022]
In order to solve the above problem, the communication device of the present invention has only one despreading block and an intensity calculation block for performing in-phase addition, and when the base station side communication device is sectorized by a directional antenna. The receivers of each of one or a plurality of sectors are used in common, and timing tracking control DLL control for a plurality of channels of one or a plurality of sectors is performed by processing in a time division manner.
[0023]
In order to solve the above problem, the communication apparatus of the present invention has only one despreading block and an intensity calculation block for performing in-phase addition, and when the reception diversity technique is applied to the mobile station side communication apparatus, This is shared by a plurality of receivers that respectively demodulate signals received by a plurality of antennas, and is processed in a time division manner to perform timing tracking control DLL control for a plurality of antennas.
[0024]
In order to solve the above problem, the communication apparatus of the present invention lowers the accuracy of the path position detected and updated in the synchronous system when the timing tracking control DLL control is performed. In order to solve the above problem, the despreading result at a certain timing is calculated in the synchronous system, and the timing follow-up control DLL control is performed using this result.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
If it is assumed that the chip speed is 4.096 Mcps and moving at a speed of 200 km per hour, this corresponds to the movement of the path position by about 0.75 chips between 1 second = 100 frames. The conventional DLL function has a function of making a DLL determination once per frame and moving the path timing by ± 0.25 chip, but the actual path movement is about 0.25 chip movement to 33 frames. It will be.
[0026]
Therefore, in the present invention, as shown in FIG. 6, the power consumption is reduced by performing DLL determination and control only once for a plurality of frames. According to the above calculation, it is possible to follow the path sufficiently by performing DLL determination only once in 33 frames, but FIG. 6 shows a state where DLL determination is performed once in 15 frames as an example.
[0027]
In order to realize the DLL follow-up accuracy equivalent to the method of determining the number of power additions necessary for the DLL determination from the addition result for “S” slots shown in 504 of FIG. 5 in the conventional example, the DLL determination cycle Even in the case of the present invention in which the length is increased to once every N frames, the number of slots to be added may be “S”.
[0028]
That is, in the prior art, 1 frame = 15 slots out of 15 slots included in one frame and “S” power is added, but in the present invention, “15 × N” slots included in N frames. The power is added for “S” slots.
[0029]
In FIG. 6, in order to improve fading and improve the effect of averaging due to noise, the slots to be added are not concentrated in time, and the (early) component and (late) component of one slot are once per frame. The difference is calculated (604, 605, 606), and this is added for 15 slots, and DLL determination (608) is performed once every 15 frames.
[0030]
When operated in this way, the DLL control unit only performs despreading and in-phase addition for one slot during one frame, and does not operate for the remaining 14 slots.
[0031]
In the present invention, using the free time for 14 slots, the DLL control block has only one despreading block and in-phase addition block, and these blocks are shared between processes at a plurality of timings. Process by division.
[0032]
According to the present invention, the hardware scale can be reduced without degrading the accuracy of the timing follow-up control DLL control.
[0033]
(Example 2)
In this embodiment, the despreading block and the intensity calculation block of the DLL control unit are time-divided into (early) component and (late) component, and an inter-slot averaging block and DLL determination block are also provided in the receiver. Shared by fingers and used for time division.
[0034]
FIG. 7 shows an operation concept of this embodiment. In the figure, reference numerals 604, 605, and 606 denote differences resulting from the in-phase addition of the despread outputs of the early timing and late timing in a slot, 608 denotes a DLL determination unit, and 701 denotes a strength calculation result difference in the first finger. Processing up to calculation, 702 is processing up to difference calculation of strength calculation result in second finger, 703 is processing up to difference calculation of strength calculation result in third finger, 704 is to switch slot averaging result of each finger Selector 705, storage means for holding the slot averaged result of the first finger, 706, storage means for holding the slot averaged result of the second finger, and 707, the slot averaged result of the third finger. The storage means to hold, 708 is an early tag for each finger. Despreading and in-phase addition processing in the timing, 709 denotes a despreading and in-phase addition processing in (. Late) timing of each finger.
[0035]
In FIG. 7, the idle time obtained by adopting the first embodiment is utilized, and finger # 1 (701), finger # 2 (702), finger # 3 (703)... The difference 604 between the (early) component and the (late) component is calculated in a time-sharing manner, and the results accumulated between a plurality of slots for each finger are sequentially stored in the storage means 705, 706, and 707. After the inter-slot averaging is completed, the finger accumulation results are further switched by the selector 704 and read sequentially, and the DLL determination is performed (608), whereby the DLL determination unit is used for each finger in a time division manner.
[0036]
FIG. 8 shows a configuration of a receiver for realizing the present embodiment. In the figure, 801 is the first finger of the demodulation system, 802 is the second finger of the demodulation system, 803 is the i-th finger of the demodulation system, 804 is the despreading section in each finger, and 805 is the detection in each finger. 806 is a selector for switching the timing for operating the DLL control unit, and 807 is a selector for returning the DLL determination result to each finger.
808 is a DLL control unit, 809 is a despreading processing unit in the DLL control unit, 810 is an intensity calculation unit in the DLL control unit, 811 is a selector for switching intensity calculation results of early timing and late timing, and 812 is in the DLL control unit A slot averaging unit, 813 is a selector for switching the slot averaged result for each finger, 814 is a storage means for holding the slot averaged result for each finger, and 815 is for switching the slot averaged result for each finger. 816 is a DLL determination unit, 817 is an accumulating unit for holding the early component intensity calculation result, 818 is an accumulating unit for holding the late component intensity calculation result, and 819 is an (early) component and (late). Subtractor for calculating component difference, 820 is a multi-slot frame A processing means for over the strength calculation result of power addition (accumulation).
[0037]
In this embodiment, since the DLL control unit conventionally provided for each finger is shared by a plurality of fingers, each finger 801, 802, 803 of the demodulation system has only a despreading block 804 and a detection block 805, respectively. , The block for the DLL function is not provided, and one DLL control block 808 performs time-division processing on the DLL control for i fingers.
[0038]
In the DLL control block 808, first, the despreading timing for each finger is selected from the selector 806 (early), the component is despread (809), the intensity calculation in-phase addition is performed (810), and the result is stored in the storage unit 817. To do. Next, the same processing is performed for the (late) component, and the calculation result is stored in the storage unit 818.
[0039]
Next, these values stored in the storage means 817 and 818 are extracted, and the difference between the (early) component and the (late) component is calculated (819). Further, this data is added between the slots (820), and the data after the addition is stored in the storage means 814 such as a memory for storing each finger via the selector 813. The above operation is performed for each of the plurality of fingers.
[0040]
Finally, since the inter-slot addition result of each finger is accumulated in the accumulating means 814, this is switched by the selector 815, DLL determination (816) is performed in a time division manner, and the result is sent to the respective units via the selector 807. Feedback to the despreading timing of the fingers. Note that the (late) component may be performed first for the calculation order of the (early) component and the (late) component.
[0041]
(Example 3)
FIG. 9 shows a receiver configuration in the third embodiment of the present invention. In the figure, 901 is a demodulation system finger # 1 (for antenna # 1 transmission pattern processing), 902 is a demodulation system finger # 1 (for antenna # 2 transmission pattern processing), and 903 is a demodulation system finger #I (antenna # 1 transmission pattern). 904 is a demodulation system finger #I (for antenna # 2 transmission pattern processing), and 905 is a storage means for holding each antenna pattern and the slot averaging result for each finger.
[0042]
In this embodiment, when the transmission diversity technique is operated in the base station, the time division processing in the first and second embodiments is applied to the terminal receiver.
[0043]
When the transmission diversity technique is operated in the base station, transmission data is modulated with a different pattern from a plurality of antennas (the number of antennas = T) and transmitted to the terminal. The terminal needs to demodulate the received data for each antenna, and a demodulation system (901, 902, 903, 904) must be prepared for each antenna and each finger.
[0044]
In the present embodiment, the terminal has one timing tracking control block, which is shared by a plurality of antennas and a plurality of fingers, and performs DLL control in a time division manner, whereby the circuit scale can be reduced.
[0045]
(Example 4)
FIG. 10 shows a receiver configuration in the fourth embodiment of the present invention. In this embodiment, the time division processing in the first to third embodiments is applied to a base station that accommodates a plurality of channels. In the figure, reference numeral 1001 denotes a demodulation system channel 1, 1002 a demodulation system channel 2, 1003 a demodulation system channel n, and 1004 an accumulation means for holding the slot averaging result for each channel and each finger.
[0046]
Since the base station apparatus processes data from a plurality of terminals, it is necessary to prepare demodulation systems 1001, 1002, 1003,... For each channel and each path. The base station has one or a plurality of timing tracking control blocks 808, which are shared by a plurality of channels and a plurality of paths, and the circuit scale can be reduced by performing DLL control in a time division manner.
[0047]
(Example 5)
FIG. 11 shows a receiver configuration in the fifth embodiment of the present invention. In this embodiment, the time division processing in the first to fourth embodiments is applied to a base station that is sectorized using a plurality of directional antennas. In the figure, 1101 is a demodulating system for sector 1, 1102 is a demodulating system for sector 2, 1103 is a demodulating system for sector s, 1104 is storage means for holding the slot averaging result for each sector, each channel, and each finger It is.
[0048]
In the case of soft handover in which data from a terminal is received in a plurality of sectors, the base station demodulates received data for a plurality of sectors and a plurality of paths, and synthesizes the received data called RAKE combining. It is necessary to prepare demodulation systems 1101, 1102, 1103. The base station has one or a plurality of timing tracking control blocks 808, which are shared by a plurality of sectors and a plurality of paths, and the DLL control is performed in a time-sharing manner, whereby the circuit scale can be reduced.
[0049]
(Example 6)
FIG. 12 shows a receiver configuration in the sixth embodiment of the present invention. In this embodiment, the time division processing in the first to third embodiments is applied to a mobile station to which antenna diversity using a plurality of antennas is applied. In the figure, reference numeral 1201 denotes a demodulating system for the receiving antenna 1, 1202 denotes a received signal from the receiving antenna 2, 1203 denotes a demodulating system for the receiving antenna 2, and 1204 denotes a slot averaging result for each finger of each receiving antenna. It is a storage means.
[0050]
When antenna diversity is applied, it is necessary to prepare demodulation systems 1201, 1202,... For each antenna and each path in order to demodulate received data for a plurality of paths for each of a plurality of antennas.
[0051]
The mobile station has one timing follow-up control block 808, which is shared by a plurality of antennas and a plurality of paths, and operated in a time division manner, thereby reducing the circuit scale.
[0052]
(Example 7)
In the seventh embodiment, in combination with the first to sixth embodiments, the path search accuracy in the path search by the synchronous system is lowered. Specifically, when the timing follow-up control DLL control by the demodulation system is operated, the number of times of power addition is reduced to about ½ that when the DLL control is not operating.
[0053]
For example, if the DLL control unit is not operated, assuming that it is necessary to perform power addition 32 times during 100 ms during path search by the synchronous system in order to increase the accuracy of the path timing, when operating the DLL control, In the path search by the synchronous system, power is added 16 times in 100 ms. When the DLL control is operated, even if the path search accuracy is somewhat poor, it can be corrected by the DLL control, and the power consumption can be reduced by reducing the number of times of power addition in the synchronous system.
[0054]
(Example 8)
FIG. 13 shows a receiver configuration in the eighth embodiment of the present invention. In the present embodiment, the despreading process calculated in the synchronous system and the despreading process calculated in the DLL control unit are overlapped as functions, and thus are shared. In the figure, reference numeral 1301 denotes a synchronization system 1302 is a despreading unit in the synchronization system, 1303 is an in-phase addition unit in the synchronization system, 1304 is a slot averaging unit in the synchronization system, 1305 is a peak detection unit in the synchronization system, and 1306 is A DLL control unit, 1307 is a selector for switching the in-phase addition result of early / late timing, 1308 is an accumulation unit for holding the in-phase result of each of the early timing and late timing, and 1309 is a DLL determination unit 1310 which is a DLL determination result. A selector for returning to each finger, 1311 is a difference calculation of the in-phase addition result of early / late timing, and 1312 is a power addition (averaging) unit of the difference calculation result.
[0055]
That is, as shown in FIG. 13, the DLL control unit 1306 includes a selector 1307 for switching the output from the synchronous system, storage means 1308 for holding the (early) timing slot averaging result and the (late) timing slot averaging result, and Only the DLL determination unit is included, and each process of despreading, in-phase addition processing, and slot averaging is performed in the synchronization system 1301.
[0056]
Originally, in the despreading process in the synchronization system 1301, a delay profile is acquired and peak detection is performed, so that the despread results at the timings before and after the timing to be despread, that is, early timing and late timing can be easily obtained. Is possible. This makes it possible to reduce the circuit scale for DLL control.
[0057]
【The invention's effect】
The receiver of the wireless communication device of the present invention shares the circuit of the reception timing tracking control (DLL control) unit between processes at a plurality of timings and processes in a time division manner, or shares the DLL control unit of a plurality of fingers. If this is processed in a time-sharing manner, the circuit scale can be greatly reduced.
[0058]
Further, by reducing the number of times of power addition in the synchronous system during the DLL control operation, it is possible to further reduce power consumption without deteriorating the synchronization tracking characteristic.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a communication apparatus in a conventional CDMA mobile communication system.
FIG. 2 is a block diagram showing a configuration of a receiver in a conventional CDMA mobile communication system.
FIG. 3 is a block diagram showing a detailed configuration of a conventional DLL control block.
FIG. 4 is an explanatory diagram showing how profiles are averaged by power addition.
FIG. 5 is an explanatory diagram showing a conventional DLL control operation.
FIG. 6 is an explanatory diagram showing a DLL control operation according to an embodiment of the present invention.
FIG. 7 is an explanatory diagram showing that DLL control is performed in a time division manner with a plurality of fingers.
FIG. 8 is a block diagram showing a configuration of a receiver according to a second embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a receiver according to a third embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a receiver according to a fourth embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of a receiver according to a fifth embodiment of the present invention.
FIG. 12 is a block diagram showing a configuration of a receiver according to a sixth embodiment of the present invention.
FIG. 13 is a block diagram showing a configuration of a receiver according to an eighth embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Antenna, 102 ... Radio | wireless part, 103 ... Baseband part, 104 ... Transmission part, 105 ... Synchronization system, 106 ... Demodulation system, 107 ... Error control system, 108 ... Interface, 109 ... Power control system, 110 ... Transmission / reception 111, control unit of wireless communication apparatus, 216, timing follow-up control unit (DLL control unit).

Claims (1)

In a communication apparatus in a code division multiple access (CDMA) system mobile communication system, a receiver
A radio unit that converts a received signal in a carrier frequency band received from a receiving antenna into a baseband spread spectrum signal; and
A synchronization system that performs correlation calculation between the baseband signal and the spread code, detects reception timing, establishes synchronization and acquires synchronization, and
A demodulation system finger is configured for each path of the multipath generated in the radio propagation path, and each demodulation system finger is a despread block that performs despreading at the reception timing detected by the synchronous system and a detection block that corrects phase rotation with the door, while have a demodulation system with the demodulation system despreading timing tracking control block which sequentially controls displacement high correlation output regardless of the reception timing to the timing obtained in the finger (DLL control block) And
The timing tracking control block, a despreading block for obtaining a despread results at two timings in which the synchronization system is different to the timing of detection, the intensity calculation block phase addition of despread results, said different A slot averaging block that calculates the difference between the in-phase addition results at two timings and adds power for a plurality of slots, and a timing tracking control determination block that performs timing tracking control determination based on the output from the slot averaging block The timing tracking control determination of the timing tracking control determination block is performed by time sharing of the despreading block and the intensity calculation block, and the movement of the path calculated by the moving speed of the receiver is determined by the timing tracking control block. A range that does not exceed a single pass timing move Communication apparatus and performs in one cycle per a plurality of frames of the inner.

Images