JP4225111B2 - Plasma display panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display panel (PDP) used for an image display device and the like, and a plasma display apparatus using the same.
[0002]
[Prior art]
In recent years, expectations for large screens and wall-mounted TVs have increased as interactive information terminals, and PDP is a promising candidate because it can display beautiful images with a self-luminous type and is easy to make large screens. Attention has been paid.
[0003]
PDPs are roughly classified into AC type and DC type in terms of driving, and there are surface discharge type and counter discharge type in terms of discharge type, but simple manufacturing due to high definition, large screen and simple structure. Therefore, at present, a surface discharge type PDP having a three-electrode structure is mainly used.
[0004]
A general structure of this PDP is shown in FIG. FIG. 9 is a cross-sectional perspective view showing a schematic configuration of the PDP.
[0005]
The front plate 2 of the PDP 1 is formed by forming a plurality of display electrodes 6 composed of scanning electrodes 4 and sustain electrodes 5 on a smooth, transparent and insulating substrate 3 such as float glass. A dielectric layer 7 is formed so as to cover, and a protective layer 8 made of MgO is further formed on the dielectric layer 7. Scan electrode 4 and sustain electrode 5 are transparent electrodes 4a and 5a serving as discharge electrodes, and bus electrodes 4b and 5b made of Cr / Cu / Cr, Ag, or the like electrically connected to transparent electrodes 4a and 5a, respectively. It consists of and.
[0006]
The back plate 9 has a plurality of address electrodes 11 formed on an insulating substrate 10 such as glass, and a dielectric layer 12 is formed so as to cover the address electrodes 11. A partition wall 13 is provided on the dielectric layer 12 at a position corresponding to between the address electrodes 11, and a phosphor layer 14 is provided between the surface of the dielectric layer 12 and the side surface of the partition wall 13. .
[0007]
The front plate 1 and the back plate 9 are disposed to face each other with the discharge space 15 interposed therebetween so that the display electrodes 6 and the address electrodes 11 are orthogonal to each other. The discharge space 15 is filled with at least one rare gas of helium, neon, argon, and xenon at a pressure of about 66500 Pa (500 Torr) as a discharge gas. The intersection of the scan electrode 4 and the sustain electrode 5 that are the display electrodes 6 operates as a discharge cell 16 that is a unit light emitting region.
[0008]
In this PDP 1, a discharge is generated by applying a periodic voltage to the address electrode 11 and the display electrode 6, and the phosphor layer 14 is irradiated with ultraviolet rays by the discharge to convert it into visible light, thereby displaying an image. .
[0009]
Here, in the conventional PDP 1, as described above, the display electrode 6 for performing the main discharge is covered with the dielectric layer 7, so that the memory can be driven. The voltage can be lowered. The protective layer 8 is intended to prevent the dielectric layer 7 from being altered by the ion bombardment that occurs during the main discharge and the drive voltage from rising, and is generally oxidized as described above. A substance having high sputtering resistance such as magnesium (MgO) is used (for example, see Non-Patent Document 1).
[0010]
[Non-Patent Document 1]
2001 FPD Technology Taizen, Electronic Journal, Inc., October 25, 2000, P543
[0011]
[Problems to be solved by the invention]
Here, when displaying a television image, it is necessary to finish all sequences within one field = 1/60 (s). However, in recent years, the number of scanning lines has increased with the increase in definition of a display image. Therefore, in order to meet this requirement, it is necessary to narrow the pulse width of the periodic voltage applied to the address electrodes 11 and the display electrodes 6 and perform high-speed driving. However, in reality, since there is a “discharge delay” in which discharge occurs after the rise of the voltage pulse, the probability that the discharge ends within the applied pulse width is low. In some cases, address discharge performed on the discharge cells 16 to be lit cannot be sufficiently performed, resulting in lighting failure. Here, the main cause of the delay in the discharge is that initial electrons that become a trigger when the discharge is started are not easily emitted from the protective layer 8 into the discharge space 15.
[0012]
The present invention has been made in view of such problems, and it is an object of the present invention to improve the responsiveness of occurrence of discharge with respect to an applied voltage and to suppress a delay in discharge, thereby enabling a good image display. .
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a plasma display panel according to the present invention includes a front plate provided with a dielectric layer covering a display electrode composed of a scan electrode and a sustain electrode, and a protective layer covering the dielectric layer. in panel, and wherein the whiskers of the tetrapod shape in the dielectric layer, the discharge space by mixing so as not to protrude, the electric field concentration due to the shape effect of the whisker in the dielectric layer was set to generate To do.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
That is, the invention described in claim 1 of the present invention is a plasma display panel having a front plate provided with a dielectric layer covering a display electrode composed of a scan electrode and a sustain electrode, and a protective layer covering the dielectric layer. in the whiskers tetrapod shape in the dielectric layer, the discharge space by mixing so as not to protrude, characterized in that the electric field concentration due to the shape effect of the whisker in the dielectric layer is adapted to generate It is a plasma display panel.
[0022]
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 is a cross-sectional perspective view showing a schematic structure of a PDP according to an embodiment of the present invention.
[0024]
The front plate 22 of the PDP 21 is formed with a plurality of display electrodes 26 composed of scan electrodes 24 and sustain electrodes 25 on a smooth, transparent and insulating substrate 23 such as float glass, and the display electrodes 26. A dielectric layer 27 is formed so as to cover, and a protective layer 28 made of MgO is further formed on the dielectric layer 27. Scan electrode 24 and sustain electrode 25 are transparent electrodes 24a and 25a serving as discharge electrodes, and bus electrodes 24b and 25b made of Cr / Cu / Cr or Ag electrically connected to transparent electrodes 24a and 25a, respectively. It consists of and. The dielectric layer 27 has a configuration in which whiskers 27a are mixed.
[0025]
The back plate 29 has a plurality of address electrodes 31 formed on an insulating substrate 30 such as glass, and a dielectric layer 32 is formed so as to cover the address electrodes 31. A partition 33 is provided on the dielectric layer 32 at a position corresponding to between the address electrodes 31, and a phosphor layer 34 is provided between the surface of the dielectric layer 32 and the side surface of the partition 33. .
[0026]
The front plate 21 and the back plate 29 are disposed to face each other with the discharge space 35 interposed therebetween so that the display electrodes 26 and the address electrodes 31 are orthogonal to each other. The discharge space 35 is filled with at least one rare gas of helium, neon, argon, and xenon as a discharge gas at a pressure of about 66500 Pa (500 Torr). The intersection of the scanning electrode 24 and the sustaining electrode 25 that are the display electrodes 26 operates as a discharge cell 36 that becomes a unit light emitting region.
[0027]
In this PDP 21, a discharge is generated by a periodic voltage applied to the address electrode 31 and the display electrode 26, and the phosphor layer 34 is irradiated with ultraviolet rays resulting from this discharge to convert it into visible light, thereby displaying an image. .
[0028]
Next, a method for driving the PDP 21 configured as described above will be described. FIG. 2 is a block diagram showing a schematic configuration of a plasma display device 100 having a PDP 21 and a drive circuit 41 for driving the PDP 21. As shown in FIG. The drive circuit 41 for driving the PDP 21 has a scan electrode driver 42, a sustain electrode driver 43, an address electrode driver 44, and a controller 45 that controls these operations. When the PDP 21 is driven, address discharge is performed by applying an address voltage between the scan electrode 24 and the address electrode 31 of the discharge cell 36 to be lit, and then between the scan electrode 24 and the sustain electrode 25. A sustain discharge is performed by applying a pulse voltage. Then, ultraviolet light is emitted along with the discharge in the discharge cell 36, and the ultraviolet light is converted into visible light in the phosphor layer 33 (FIG. 1), and the discharge cell 36 is turned on.
[0029]
Here, in the PDP, generally, a method of expressing gradation by dividing one frame of video into a plurality of subfields (SF) is used. In this method, 1 SF is further divided into four periods in order to control the discharge of the discharge gas in the discharge cell 36. FIG. 3 is a time chart in 1 SF of the waveform of the driving voltage of the plasma display device 100 output from the driving circuit 41.
[0030]
Each period shown in FIG. 3 will be described. The setup period 51 is for accumulating wall charges uniformly in all the discharge cells 36 (FIG. 1) in the PDP 21 (FIG. 1) in order to easily generate discharge. In the address period 52, the discharge discharge of the discharge cell 36 (FIG. 1) to be lit is performed. In the sustain period 53, the discharge cells 36 (FIG. 1) written in the address period 52 are turned on and kept on. In the erase period 54, lighting of the discharge cells 36 (FIG. 1) is stopped by erasing the wall charges.
[0031]
Next, a specific state in each period will be described with reference to FIGS. First, in the setup period 51, a voltage higher than that of the address electrode 31 and the sustain electrode 25 is applied to the scan electrode 24 to discharge the discharge gas in the discharge cell 36. The charges generated thereby are accumulated on the wall surface of the discharge cell 36 so as to cancel the potential difference among the address electrode 31, the scan electrode 24, and the sustain electrode 25. As a result, the surface of the protective layer 28 near the scan electrode 24 is negatively charged. It is considered that charges are accumulated as wall charges, and positive charges are accumulated as wall charges on the surface of the phosphor layer 34 near the address electrodes 31 and the surface of the protective layer 28 near the sustain electrodes 25. This wall charge is considered to generate a predetermined wall potential between the scan electrode 24 and the address electrode 31 and between the scan electrode 24 and the sustain electrode 25.
[0032]
Next, in the address period 52, a lower voltage than the address electrode 31 and the sustain electrode 25 is applied to the scan electrode 24 with respect to the discharge cell 36 to be lit. In other words, a voltage is applied between the scan electrode 24 and the address electrode 31 in the same direction as the wall potential, and a voltage is also applied between the scan electrode 24 and the sustain electrode 25 in the same direction as the wall potential. This causes an address discharge. As a result, it is considered that negative charges are accumulated on the surface of the phosphor layer 34 and the protective layer 28, and positive charges are accumulated as wall charges on the surface of the protective layer 28 in the vicinity of the scanning electrode 24. As a result, it is considered that a predetermined wall potential is generated between the sustain electrode 25 and the scan electrode 24. Here, a time delay from when a voltage is applied between the scan electrode 24 and the address electrode 31 to when an address discharge occurs is a “discharge delay”. Further, when the write discharge does not occur within the address time of each scanning electrode 24, it is a “write error”. In this case, no sustain discharge occurs, and the image display flickers. . Here, when the resolution is further increased, the address time assigned to each scan electrode 24 needs to be further shortened, so that the probability that a write error will occur further increases.
[0033]
In the sustain period 53, a higher voltage is applied to the scan electrode 24 than the sustain electrode 25. That is, a sustain discharge is generated by applying a voltage between the sustain electrode 25 and the scan electrode 24 in the same direction as the wall potential. As a result, lighting of the discharge cell 36 can be started. Then, by applying a voltage pulse so that the polarity is alternately switched between the sustain electrode 25 and the scan electrode 24, pulse light emission can be intermittently performed.
[0034]
In the erase period 54, an incomplete discharge is generated by applying a narrow erase pulse to the sustain electrode 25, and the wall charges are extinguished to erase the discharge.
[0035]
Here, the above-mentioned “discharge delay” and “write error” are mainly caused by the fact that initial electrons that become a trigger when discharge is started are not easily released from the protective layer 28 to the discharge space 35. Although it is conceivable, according to the PDP 21 according to the embodiment of the present invention, since the whisker 27a is mixed in the dielectric layer 27, the electric field concentration in the dielectric layer 27 is caused by the shape effect of the whisker 27a. It is considered that the electric field strength due to the applied voltage is increased and the amount of electrons emitted toward the discharge space 35 is increased. As a result, it is considered that initial electrons serving as a trigger are easily emitted, and discharge delay and writing mistake are suppressed.
[0036]
In order to confirm the effect of the PDP according to the embodiment of the present invention described above, the results of studies conducted by the present inventors are shown below.
[0037]
PDPs 21 having dielectric layers 27 with different amounts of whiskers 27a are manufactured, and voltage is applied to the respective PDPs 21 between the scan electrodes 24 and the address electrodes 31 in the address period until discharge occurs. The “discharge delay”, which is the time difference, was measured.
[0038]
Specifically, the time when the peak of discharge luminescence was shown was taken as the time when discharge occurred, and the delay time was measured 100 times and averaged.
[0039]
As a method for forming the dielectric layer 27, lead oxide (PbO), bismuth oxide (Bi ₂ O ₃ ), or phosphorus oxide (PO ₄ ) as a main component (for example, lead oxide (PbO) 70 wt%, oxidation Whisker 27a is mixed in a paste-like low-melting glass material made of boron (B ₂ O ₃ ) 15% by weight and silicon oxide (SiO ₂ ) 15% by weight, and formed into a thickness of 20 μm to 50 μm by die coating. Then, it was formed by drying and firing under the normal conditions for the low-melting glass material. The amount of whisker 27a mixed in the low melting point glass material was changed to 0% by weight, 0.1% by weight, 1% by weight, 10% by weight, 40% by weight, 60% by weight, and 80% by weight.
[0040]
The whisker 27a used was a tetrapot-shaped zinc oxide (ZnO) whisker produced by a thermal CVD method as shown in FIG. 4 (length of one whisker leg: 1 to 200 μm, core leg). Thickness: 0.01 to 10 μm, typically one leg length: 5 to 50 μm, core leg thickness: 0.05 to 5 μm). This is commercially available from Matsushita Amtech Co., Ltd. under the trade name “Panatetra”.
[0041]
FIG. 5 schematically shows an example of the presence state of the whiskers 27 a in the dielectric layer 27 as a partially enlarged sectional view of the front plate 22.
[0042]
And the evaluation result of discharge delay time is shown in FIG. As can be seen from FIG. 6, the discharge delay time is 2700 ns when the amount of whisker 27a is 0% by weight, whereas the discharge delay time is shortened as the amount of whisker is increased. I can confirm.
[0043]
In other words, it can be seen that by mixing the whisker 27a in the dielectric layer 27, it is possible to obtain a PDP in which a good image display with little flickering is suppressed with a delay in discharge being suppressed.
[0044]
However, if the mixing amount of the whisker 27a is 60% by weight or more, the transmittance as the dielectric layer 27 is remarkably lowered, and the image display is hindered. Therefore, the effect of the present invention is sufficiently exhibited. The amount of whisker 27a that can be produced is preferably 0.1% by weight or more and 60% by weight or less.
[0045]
Further, as a configuration that further exerts the effect of the present invention, the inventors have provided at least the projection shape of the whisker 27a through the protective layer 28 from the surface of the dielectric layer 27 to the discharge space 35 side as shown in FIG. A configuration in which a part of the image is projected (protruding or exposed) was examined. The result is shown in FIG. In contrast to the case where 1% by weight of whisker 27a is mixed, the discharge occurs when whisker 27a protrudes from the surface of dielectric layer 27 toward discharge space 35 through protective layer 28 and when it does not protrude. This is a comparison of delay times. From FIG. 8, it can be confirmed that the discharge delay time is further shortened by the configuration in which the whisker 27a protrudes, which is considered to be a result of an increase in the amount of electrons emitted toward the discharge space 35.
[0046]
Here, as a method of intentionally projecting the whisker 27a toward the discharge space 35, the whisker 27a has a leg longer than the thickness of the dielectric layer 27, or the dielectric layer 27 has a multilayer structure. A method of increasing the probability that the whisker 27a protrudes without changing the total thickness of the dielectric layer 27 by mixing the whisker 27a only when forming the outermost dielectric layer on the discharge space 35 side. Etc. In any case, it is desirable that the protruding amount is equal to or greater than the thickness of the protective layer 28 and protrudes from the dielectric layer 27 and also protrudes from the protective layer 28.
[0047]
In the above description, a tetrapot shape is given as an example as an example. However, the shape is not particularly limited to this, and even in the case of a needle shape or a mesh shape in which whiskers are intertwined in a plane, the shape described above is used. It is confirmed that the same effect can be obtained as well. However, the tetrapot shape is preferable because the presence state in the dielectric layer 27 increases the probability that the whisker protrusion shape “stands” toward the discharge space 35.
[0048]
Further, the composition is not limited to ZnO. For example, TiO ₂ , SiC, Si ₃ N ₄ , AlN, BN, or TiC can be used as long as the material produces whiskers in the same manner. Make sure you can get.
[0049]
【The invention's effect】
As described above, according to the plasma display panel of the present invention, the structure in which the whisker is mixed in the dielectric layer improves the responsiveness of the occurrence of discharge with respect to the applied voltage, and suppresses the discharge delay. A plasma display panel capable of displaying and a plasma display device using the same can be realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional perspective view showing a schematic configuration of a plasma display panel according to an embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a plasma display device using the plasma display panel according to an embodiment of the present invention. FIG. 3 is a time chart showing driving waveforms of a plasma display panel according to an embodiment of the present invention. FIG. 4 is a schematic diagram showing an example of the shape of a whisker. FIG. 5 is a plasma display according to an embodiment of the present invention. FIG. 6 is a partially enlarged cross-sectional view of a front plate showing an example of a state of whisker in a dielectric layer of the panel. FIG. 6 shows discharge of the plasma display panel according to the embodiment of the present invention with respect to the amount of whisker mixed in the dielectric layer. FIG. 7 is a graph showing a change in delay time. FIG. 7 is a diagram illustrating a plasma display panel according to another embodiment of the present invention. FIG. 8 is a partially enlarged cross-sectional view of a front plate showing an example of the presence of whiskers in a body layer. FIG. 8 is a diagram showing changes in discharge delay time due to protrusion of whiskers in a dielectric layer. Cross-sectional perspective view showing schematic configuration 【Explanation of symbols】
21 Plasma display panel (PDP)
22 Front plate 23 Substrate 24 Scan electrode 25 Sustain electrode 26 Display electrode 27 Dielectric layer 27a Whisker 28 Protective layer

Claims (1)

In a plasma display panel having a front plate provided with a dielectric layer covering a display electrode composed of a scan electrode and a sustain electrode, and a protective layer covering the dielectric layer , a tetrapot-shaped whisker is formed in the dielectric layer . A plasma display panel characterized in that electric field concentration occurs due to a whisker shape effect in a dielectric layer by mixing so as not to protrude into a discharge space .

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