JP4297195B1 - Laminated chip - Google Patents

Abstract

Provided is a laminated chip provided with an economical means for electrical connection between chips by a simple structure and process without providing a through via.
A multilayer chip according to the present invention includes a first chip having a plurality of first electrodes on one surface (front surface) of a substrate, a semiconductor element on the surface of a conductive substrate, and the substrate. Second chips each having a second electrode at a position corresponding to the first electrode on the surface, the first electrode of the first chip, and the other surface of the second chip (Back side) is bonded and laminated, and the first chip, the second electrode, and the area inside the substrate of the second chip sandwiched between the first and second electrodes, An electrical coupling means between the first chip and the second chip is used.
[Selection] Figure 1

Description

  The present invention relates to a multilayer chip, in particular, a multilayer chip in which a plurality of chips having electrical coupling paths between chips suitable for the multilayer chip are stacked.

In semiconductors, active areas consisting of elements such as transistors and wiring are formed all at once on the entire surface (surface) of a wafer with a diameter of several tens of centimeters, and then the wafer is cut vertically and horizontally to obtain a chip of several mm square. These are housed one by one in a package of several centimeters, and this system is mounted on a circuit board at a pitch of several centimeters to form a system.
Therefore, not only the integration density is reduced by about two orders of magnitude at the system level, but also the propagation time / power consumption product required for signal propagation between chips is also deteriorated by about two orders of magnitude compared to the inside of the chip. Low power consumption and size reduction were difficult.
Therefore, if a plurality of chips are stacked, that is, if they are accommodated in one package by overlapping in the thickness direction, the integration density and the signal propagation performance between the chips can be dramatically improved. It was a long-standing dream.

In order to stack chips, an electrical coupling structure between chips is a key.
As a realization method, for example, there is a method in which the size of the chip is sequentially reduced and superimposed in a tiered form, and bonding is performed using wires, bumps, or the like in the same manner as the connection between the chip and the package.
However, with this method, the structure itself prevents the integration density from being improved, and batch (simultaneous) processing is difficult, so productivity and reliability cannot be improved.

Therefore, various electrical coupling means that can be simultaneously formed by batch processing in or on the stacked first and second chips have been proposed.
Examples of the electrical coupling means include light, inductance means, capacitance means, and resistance (conductivity) means.
However, in any case, it is an obstacle that the thickness of the wafer, and thus the thickness of the chip, is required to be at least several tens of μm because of the requirement for handling the wafer.

For example, in Patent Document 1, a light emitting element is provided on the surface of a first chip, a light receiving element is provided on the surface of a second chip stacked thereon, and data is transmitted with light transmitted through the bulk of the second chip. A method of transmitting is disclosed.
However, in this method, at least in the case of silicon-based semiconductors which are currently mainstream, it is difficult to form an appropriate light emitting / receiving element for light that can be transmitted through the bulk of the chip.

  Next, an inductive means, that is, a method in which coils are formed on the surfaces of the first and second chips, and data is transmitted by mutual inductance coupling between the two coils via the silicon of the second chip, is proposed. However, according to this method, it is difficult to obtain an appropriate inductance value in a small area on the chip, and a large drive current is required.

  Further, a method of transmitting data by capacitance coupling using capacitance means, that is, a capacitor having a planar electrode on each of the surfaces of the first and second chips and using silicon of the second chip as a dielectric layer. However, this method also requires a large area on the chip, and it is difficult to supply power to the upper chip, and more than two layers are difficult to stack.

Therefore, various methods have been proposed and researched to provide resistive (conductive) means, that is, conductive means that penetrates the inside of the chip bulk in the thickness direction from the back surface to the front surface of the chip, called “through vias”. It has been.
For example, Patent Document 2 discloses a technique in which a through via is provided and a conductive pin is embedded therein.

However, the thickness of the semiconductor substrate is usually several 100 μm, and even when it is thinned by backside polishing, etc., it is several tens of μm. Therefore, this bulk can be obtained without damaging the surrounding silicon bulk and active region (semiconductor element / wiring formation region). Providing a “through via” that penetrates the chip does not increase accuracy even if a large area is required on the chip, even if mechanical drilling, chemical or physicochemical etching is used, and productivity is low. It was accompanied by a great deal of difficulty with high manufacturing costs.
Incidentally, the film thickness to be subjected to (physical) chemical etching used for forming the active region is at most about 1 μm.
Patent Application Publication No. 05-068105 Patent Application Publication No. 05-183019

  The problem to be solved by the present invention is to provide a laminated chip having an electrical coupling means between chips with a simple structure and process without providing a through via.

In order to solve the above problems, a multilayer chip according to an embodiment of the present invention includes: a first chip having a plurality of first electrodes on one surface (front surface) of a substrate; and a conductive semiconductor substrate. A semiconductor chip on the surface, and a second chip provided with a second electrode at a position corresponding to the first electrode on the surface of the substrate, the first electrode of the first chip, The other surface (back surface) of the two chips is bonded and formed in layers, and the first chip, the second electrode, and the second chip sandwiched between the first and second electrodes. A region inside the substrate is used as an electrical coupling means between the first and second chips without providing a through via in the substrate .

A laminated chip according to another embodiment of the present invention for solving the above problems includes a first chip having a plurality of first electrodes on one surface (front surface) of a substrate, and a conductive semiconductor substrate. A semiconductor chip on the surface of the substrate, and a second chip provided with a second electrode at a position corresponding to the first electrode on the surface of the substrate, and further on the back surface of the substrate of the second chip A third electrode is provided at each of the positions corresponding to the plurality of first electrodes, the first electrode and the corresponding third electrode are bonded to each other, stacked, and bonded to the first and second electrodes. A region inside the substrate of the second chip sandwiched between the third electrode, the second electrode, and the third and second electrodes can be formed without providing a through via on the substrate . And an electrical coupling means between the second chips.

  According to the present invention, since the substrate bulk region between both electrodes is made a resistive electrical coupling means only by providing electrodes on the front and back surfaces of the conductive substrate of the chip, without providing a through via on the substrate, With a simple structure and process, it is possible to provide a laminated chip provided with an economical means for electrical coupling between chips.

  In the design of digital systems, particularly high-performance processors, the CPU and (external cache) memory are “face-up” as before, that is, the chip surface (surface with the active area) is individually packaged. In this case, the signal propagation delay between the two has seriously lowered the system performance, and it has been eagerly desired to increase the speed of the signal propagation by making it wideband, that is, compact.

  In response to this request, there is a method of mounting the CPU / memory chip in a “face down” manner, that is, mounting the chip directly on the substrate with the surface of the chip (the surface having the active area) turned over, It was extremely expensive or difficult to ensure the reliability of the important chip (active area).

Since the trigger of the present invention was this request, in the following embodiments, the CPU and the memory will be described as representatives of the first chip and the second and third chips, respectively, but the scope of the present invention is limited to this. Needless to say, the present invention can be applied to a system (system) including a plurality of chips, such as a digital system including a plurality of CPUs, an analog system, and a digital / analog mixed system.
Hereinafter, advantages and features of the present invention and methods for achieving them will be described with reference to the drawings.
Note that the same reference numerals denote the same components throughout the specification.

FIG. 1 is a cross-sectional view of a multilayer chip according to an embodiment of the present invention, which is a basic two-layer stack.
The first chip (CPU) 10 has an electric circuit for CPU (not shown) made of a first semiconductor element inside a substrate 13 in contact with a first surface (hereinafter referred to as a surface) 16. The electrical connection with the second chip (memory) 20 is performed through a first plurality of electrodes 19 (usually circular or square and called a pad).
The first electrode 19 is metallic and made of, for example, aluminum, is provided on an insulating film 17 that covers the substrate 13, and is coupled to an electrical circuit in the substrate through a via 18.

On the other hand, the second chip 20 is also in contact with the first surface 26 of the substrate 23 along with an electric circuit for memory (not shown) made of a second semiconductor element, and the first chip of the first chip. The second electrode 25 is provided at a position immediately above the electrode 19.
The substrate 13 may be conductive or insulating, but the substrate 23 is a conductive semiconductor having a p-type or n-type dopant.
The second electrode 25 is composed of a dopant layer having the same conductivity type and high concentration as the dopant of the substrate 23, or a metal electrode having the same planar shape bonded thereto, and the planar shape is the first in this embodiment. Although it is the same shape as the electrode 19, it is not limited to this as described below.

Now, when the second chip is placed on the front surface side of the substrate of the first chip so that the back surface 21 of the substrate 24 is in contact therewith, and the first electrode 19 is adhered to the back surface 21 of the second chip, two-layer lamination A chip is obtained.
In this state, the first and second electrodes 19 and 25 are configured to have a region 24 (bulk region sandwiched by a one-dot chain line) inside the conductive substrate of the second chip sandwiched between the first and second electrodes. It is connected by a main resistor, and this can be used as an electrical coupling means between the first and second chips.

FIG. 2 is a cross-sectional view of a laminated chip according to another embodiment of the present invention, which is a case of three-layer lamination.
Compared with FIG. 1, in the present embodiment, a third chip 30 is interposed between the first chip 10 and the second chip 20.
The third chip includes the conductive substrate 33, the second electrode 35, the insulating film 37, the via 38, the first electrode 39, that is, the first and second chip components, and the upper and lower first, It has electrical coupling means with each second chip.
As a result, for example, the third chip (primary cache memory) and the second chip (secondary cache memory) can be sequentially compactly mounted on the first chip (CPU).
If a third chip is further inserted, it can be seen that four or more chips can be stacked.

  As described above, it has been found that any number of layers can be stacked on the basis of the case of two-layer stacking. Therefore, the following description is based on the two-layer stacking of FIG. Although the details of the electrical coupling means in 20 are mainly described, it will be apparent that these can be applied to the case of a laminated chip having three or more layers.

FIG. 3 is a first modification of one embodiment of the present invention.
Compared to FIG. 1, the second chip 20 has the same planar shape and a metallic third electrode on the back surface 21 of the substrate 23 at a position corresponding to the first electrode 19 of the first chip. 22 and the third electrode 22 corresponding to the first electrode 19 is bonded to form a laminated chip.
This reduces the contact resistance between the first electrode and the back surface of the substrate of the second chip, and the resistance value of the electrical coupling means between the first and second chips is determined by the bulk of the substrate. It can be stabilized to a relatively low value.

FIG. 4 is a second modification of one embodiment of the present invention.
Compared with FIG. 3, a portion of the second chip in contact with the third electrode 22 of the substrate 23 is provided with a dopant layer 22a having a higher concentration than the dopant concentration of the substrate. If the same conductivity type is used, ohmic contact with the substrate of the third electrode is facilitated, and the resistance value of the electrical coupling means can be stabilized to a lower value.

FIG. 5 shows a third modification of the embodiment of the present invention, in which the third electrode of the second chip is limited to gold and the conductivity type of the substrate is limited to p-type.
Compared with FIG. 4, a gold diffusion layer 22 b derived from the third electrode is formed in the portion of the back surface 21 of the substrate 23 of the second chip that is in contact with the third electrode 22, and the third electrode It is easy to make ohmic contact with the substrate, and at the same time, the bulk resistance value of the bulk region 24 of the electrical coupling means inside the substrate is lowered, and the resistance value of the electrical coupling means between the first and second chips is further reduced. Can be stabilized.

  In the following FIG. 6 and subsequent figures, as shown in FIGS. 3 to 5, it is limited to the case where there is a third electrode 22, but when there is no third electrode 22 as shown in FIGS. The third electrode 22 in FIG. 6 and subsequent figures is replaced with the first electrode of the same shape of the first chip after bonding.

FIG. 6 is an explanatory diagram of a method for calculating a signal transmission coefficient of the electrical coupling means.
FIG. 6A is a cross-sectional view of the portion of the second chip 20 common to the above-described laminated chip embodiment.
The bulk region 24 of the electrical coupling means is a three-dimensional structure composed of a main resistance from the third electrode 22 to the second electrode 25 and a parasitic resistance to the adjacent third electrode and the second electrode. It has a continuous resistance network.

  FIG. 6B is a plan view of the second chip portion. The planar shapes of the third electrode 22 and the second electrode 25 are both the same size, and the thickness of the second chip is t. The horizontal dimension of the second and third electrodes, i.e., here the diameter of the circle is d, the typical distance to the adjacent electrical coupling means, i.e. here the distance between the centers of the nearest circles. This is the case of L / 2.

  In this case, as shown in the equivalent circuit diagram of FIG. 6C, the adjacent third and second electrodes (there are eight pairs in the figure) are regarded as the node “O (O)” and The lumped constant is applied to the resistor between the three electrodes 22, the second electrode 25, and the three nodes of the node O.

Further, the signal conductance gc corresponding to the main resistance between the third electrode 22 and the second electrode 25 is approximated by the conductance between the parallel plate electrodes, and the parasitic resistance corresponding to the resistance between the third electrode 22 and the second electrode 25 and the node O is obtained. When the conductance 2gp is approximated by the conductance between coaxial cylindrical electrodes, an approximate number of the signal transmission coefficient Av from the third electrode 22 to the second electrode 25 is calculated by the following equation.
[Formula 1]
Av = gc / (gc + gp)
= 1 / (1+ (1 / ((d / 2t) ² · ln (L / d))))
However, where the specific resistance of the substrate is ρ,
[Formula 2]
gc = π · d · d / (4 · ρ · t)
2gp = 2 · π · t / (ρ · ln (L / d))

What is noticed by this estimation method is that the parasitic conductance gp, and thus the signal transfer coefficient Av, depends only logarithmically on the ratio of the electrode diameter (d) to the distance between adjacent electrodes (L / 2).
In other words, even when the electrode shape is different from a circle, or when the position and distance of adjacent electrodes vary, the approximate number of the signal transmission coefficient Av can be obtained relatively stably even if an appropriate representative value is used.

For example, when the substrate specific resistance ρ = 20 Ωcm, the substrate thickness t = 20 μm, the electrode diameter d = 40 μm, twice the distance between adjacent electrodes, and L = 120 μm, gc = gp = 0.63 mS, and the signal transmission coefficient Av = 0.5.
That is, the transmission signal on the first chip side is attenuated by half to become the reception signal on the second chip side.
For example, in the case of a digital signal, it can be understood that the original level can be sufficiently restored by the latch or the amplifier on the second chip side when the attenuation is about this level.

However, this estimation is based on the premise that all the signal voltages of neighboring neighboring electrodes are in a stationary state.
Actually, there may be a worst case in which the signal voltages of neighboring neighboring electrodes all move in the opposite direction to the signal voltage of the electrode of interest.

In that case, noise corresponding to the parasitic conductance of 2 gp is generated, and the noise transfer coefficient is Ag = gp / (gc + gp). Therefore, it is considered that the final signal transfer coefficient is Af = Av−Ag.
Therefore, from this estimation method, if gc / gp is set to 1 as described above, Af = 0, that is, the operation becomes impossible, and in order to enable the operation at Af = 1/3 to 1/2, gc / gp = It turns out that 2-3 is required.

FIG. 7 is an explanatory diagram of a method of shielding the electrical coupling means and a method of calculating a signal transmission coefficient in that case, and is applicable to any of the above-described laminated chip embodiments as in FIG. 6 (A). Is possible.
FIG. 7A is a partial cross-sectional view of the second chip 20, and FIG. 7B is a partial plan view of the second chip.

  The shield means includes an annular third shield electrode 42 and a second shield electrode 45 formed on the back surface 21 and the front surface 26 of the substrate, respectively, and a cylindrical bulk region 44 sandwiched therebetween. The cylindrical electrical coupling means comprising the circular third electrode 22, the bulk region 24, and the circular second electrode 25 is located at the center of the cylindrical shield means.

The diameters of the circular third electrode 22 and the second electrode 25 are d, and the typical distance from the shield means, that is, the median value of the diameter of the cylinder of the shield means is L.
Also in this case, as shown in the equivalent circuit diagram of FIG. 7C, the entire shield means is regarded as the node “G”, and the third electrode 22, the second electrode 25, and the three nodes of the node G are connected. Make a lumped constant in the resistor.

  In this case, since the node G of the shield means can be regarded as substantially stationary at the ground potential, the noise transfer coefficient is approximately zero in FIG. gc + gp), and the Af value can be increased even with the same gc / gp ratio as compared with the case where the shielding means is not applied.

FIG. 7 shows a case where one shield means is individually applied to one electrical coupling means. However, when shield means are provided to a plurality of adjacent electrical coupling means, the plane of the shield means is shown. The shape may be a grid made of a plurality of triangles, squares, or hexagons, and an electrical coupling means may be placed on each grid.
Thereby, since the adjacent electrical coupling means can share the shield means, the chip area can be made more efficient.

FIG. 8 is a cross-sectional view of one embodiment of the present invention in a triple well CMOS.
The triple well type CMOS is a device structure that has been used in recent high-performance digital semiconductor CMOS_LSI. As shown in FIG. 8, the second electrode 25 according to the present invention has n-type triple wells. -The MOST p-well and its contact p + layer can be diverted and formed in the same mask process without adding another process, and all the MOST elements are accommodated in the n-well. Even if a signal is applied to the electrical coupling means, it does not affect the MOST element as noise from the substrate side, which is convenient.

  The multilayer chip according to the present invention described above with reference to FIGS. 1 to 7 can be applied to a semiconductor LSI including digital, analog, or a combination of both. In this case, the electrical coupling means described above is a digital signal path that transmits a voltage or current corresponding to 0 or 1 that changes over time.

In this case, the digital signal path further includes a reference signal path for transmitting a voltage or current corresponding to an intermediate value between 0 and 1 for the single or plural digital signal paths. By differentially amplifying the reference signal, common mode noise can be suppressed.
In particular, when a reference signal path is provided on a one-to-one basis with respect to a digital signal path, noise interference with an adjacent digital signal path can be reduced by setting the reference signal in reverse phase to the digital signal.

FIG. 9 shows a fourth modification of the embodiment of the present invention. As shown in the sectional view of FIG. 9A, the size of the third electrode 22 is larger than that of the second electrode 25. ing.
Specifically, as shown in the plan view of FIG. 9B, the second electrode 25 is circular with a diameter dr, whereas the planar shape of the third electrode 22 is as shown in FIG. As shown in (D) and (E), the representative dimension dd is 5 times, for example, dr as shown in the figure.

  However, in the case of (C), the third electrode 22 is composed of five small electrodes having the same dimensions as the second electrode 25, and referring to FIG. Short-circuited by wiring (not shown) by the first electrode 19 of one chip or inside the first chip with respect to the via 18 of the first chip.

  Conversely, in the case of (D) and (E), the planar shape of the first electrode 19 of the first chip may be congruent with the third electrode 22, or smaller than the third electrode 22, For example, it may be the same size as the first electrode 19.

  In this way, the electrical coupling means with the enlarged third electrode can in particular increase the signal conductance gc and thus the final signal transfer coefficient Af, for example the signal path of a clock signal in a digital system. It is suitable as.

  Further, the above-described annular shield means is applied to the electrical coupling means for such a clock signal path, and at this time, the ring width of the annular shield electrode is set to be used for the annular shield of the electrical coupling means for the general signal path. If it is larger than the width of the ring of electrodes, distortion due to noise from neighboring signals in the waveform of the clock signal can be suppressed.

In the above description, the case of signal transmission from the first chip to the second chip has been dealt with. However, this electrical coupling means is bidirectional, and the second chip is exchanged between the transmission side and the reception side. The signal transmission from the first chip to the first chip can be handled in the same manner including calculation of the signal transmission coefficients Av and Af.
However, in the case of the fourth modified example, the size of the second electrode 25 (transmission side) is made larger than the sizes of the third and first electrodes (reception side).

Further, in the above embodiments, the case where the electrodes and the semiconductor elements are provided on the surface of the substrate of all layers of the chip has been described. However, the substrate of the chips of some layers may lack the semiconductor elements.
For example, the substrate of the lowermost chip of a laminated chip of two layers or three or more layers may lack a semiconductor element and include only an electrode. In this case, the substrate of the lowermost chip is connected to the electrode. It becomes a dedicated board.
In that case, a passive element including a semiconductor element, a resistor, or a capacitor of another chip may be mounted on the substrate of the lowermost chip by a well-known wire bond or flip chip bond.

It is sectional drawing of the laminated chip by one Embodiment of this invention. (2-layer lamination) It is sectional drawing of the laminated chip by other embodiment of this invention. (3-layer lamination) It is a 1st modification of one Embodiment of this invention. (Third electrode) It is a 2nd modification of one Embodiment of this invention. (Third electrode and high-concentration dopant layer) It is a 3rd modification of one Embodiment of this invention. (Third electrode and gold diffusion layer) It is explanatory drawing of the calculation method of the signal transmission coefficient of an electrical coupling means, (A) is a fragmentary sectional view of a 2nd chip | tip, (B) is a partial top view of a 2nd chip | tip, (C) is a signal transmission coefficient. FIG. It is explanatory drawing of the method of providing a shield to an electrical coupling means, and the calculation method of the signal transmission coefficient in that case, (A) is a fragmentary sectional view of a 2nd chip | tip, (B) is a partial plane of a 2nd chip | tip. FIG. 4C is an equivalent circuit diagram of the signal transfer coefficient. It is sectional drawing of one Embodiment of this invention in a triple well type | mold CMOS. It is the 4th modification of one Embodiment of this invention (size expansion of a 3rd electrode), (A) is a fragmentary sectional view of a 2nd chip | tip, (B) is a top view of a 2nd electrode, (C (D) (E) are plan views of the third electrode.

Explanation of symbols

10, 20, 30 First, second, third chip 11, 21, 31 Back surface of substrate 12, 22, 32 Third electrode
22a High concentration dopant layer
22b Gold diffusion layer 13, 23, 33 Substrate 14, 24, 34 Bulk region 15, 25, 35 Second electrode 16, 26, 36 Surface of substrate 17, 27, 37 Insulating film 18, 28, 38 Via 19, 29, 39 First electrode 42, 44, 45 Third shield electrode, bulk region, second shield electrode

Claims (11)

A first chip having a plurality of first electrodes on one surface (front surface) of the substrate, a semiconductor element on the surface of the conductive semiconductor substrate, and the first electrode on the surface of the substrate. A second chip, each having a second electrode in position,
The first electrode of the first chip and the surface (back surface) on the other side of the second chip are adhered and laminated,
A region inside the substrate of the second chip sandwiched between the first electrode, the second electrode, and the first and second electrodes can be formed without providing a through via on the substrate. A laminated chip, characterized in that the second chip is electrically coupled. A first chip having a plurality of first electrodes on one surface (front surface) of the substrate, a semiconductor element on the surface of the conductive semiconductor substrate, and the first electrode on the surface of the substrate. A second chip, each having a second electrode in position,
And a third electrode at a position corresponding to the plurality of first electrodes on the back surface of the substrate of the second chip,
The first electrode and the corresponding third electrode are bonded to form a laminate,
A region inside the substrate of the second chip sandwiched between the first and third electrodes, the second electrode, and the third and second electrodes that are bonded together, and a through via is formed in the substrate A multilayer chip characterized in that it is an electrical coupling means between the first and second chips without being provided .   3. The dopant layer having the same conductivity type as the substrate of the chip and having a higher concentration than the substrate is provided on the back surface of the second chip, the portion including the third electrode. The laminated chip described.   The third electrode is made of gold, and a gold diffusion layer derived from the third electrode is formed on the back surface of the (p-type) substrate of the second chip. Item 3. The laminated chip according to Item 2. In the electrical coupling means, the thickness of the second chip is t, the horizontal dimension of the first and second electrodes is d, and the horizontal dimension of the electrical coupling means that surrounds the adjacent electrodes is horizontal. Assuming that the representative distance is L / 2, the signal conductance gc is approximated by the conductance between the parallel plate electrodes, and the parasitic conductance 2gp is approximated by the conductance between the coaxial cylindrical electrodes. The multilayer chip according to claim 1, wherein the multilayer chip is calculated.
[Formula 1]
Av = 1 / (1+ (gp / gc))
= 1 / (1+ (1 / ((d / 2t) 2 · ln (L / d))))   2. The multilayer chip according to claim 1, wherein each of the first electrode and the second electrode is surrounded by an annular shield electrode.   3. The multilayer chip according to claim 2, wherein each of the first, second, and third electrodes is surrounded by an annular shield electrode.   3. The multilayer chip according to claim 1, wherein the electrical coupling means is a digital signal path that transmits a voltage or current corresponding to 0 or 1 that changes over time.   The electrical coupling means further includes a reference signal path for transmitting a voltage or current corresponding to an intermediate value between 0 and 1 with respect to one or a plurality of the digital signal paths. The multilayer chip according to 8.   The digital signal comprises a clock signal and a general signal, and at least the area of the first electrode of the electrical coupling means for the clock signal path is equal to that of the second electrode of the electrical coupling means for the general signal path. The multilayer chip according to claim 8, wherein the multilayer chip is larger than an area. The digital signal is composed of a clock signal and a general signal, and the width of the ring of the annular shield electrode of the electrical coupling means with respect to the clock signal path is the width of the ring of the annular shield electrode of the electrical coupling means with respect to the general signal path. The multilayer chip according to claim 8, which is larger than the width of the multilayer chip.

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