JP4291429B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices, and more particularly to a method of manufacturing a semiconductor device having a so-called epitaxial substrate in which a semiconductor layer is epitaxially grown on a semiconductor substrate.
Due to advances in miniaturization technology, miniaturization of semiconductor devices is progressing year by year. However, in recent so-called sub-half-micron devices, even low-density crystal defects contained in commercially available high-quality Si substrates can operate. Since an adverse effect is exerted, a Si layer is epitaxially grown on such a Si substrate, and a semiconductor device is being formed thereon.
[0002]
In particular, in a conventional Si substrate, when a CMOS device is formed, it is inevitable that a parasitic thyristor including a diffusion region of the CMOS device is formed in the substrate. However, such a parasitic thyristor is easily latched up by noise or the like. As a result, the normal operation of the semiconductor device is hindered. Such latch-up appears particularly prominently in a miniaturized semiconductor device in which diffusion regions on a substrate are formed close to each other. However, when the epitaxial substrate is used, the latch-up problem can be effectively suppressed. It becomes possible. Further, by using the epitaxial substrate, the leakage current characteristics of the formed semiconductor device are greatly improved.
[0003]
[Prior art]
FIG. 1 shows the principle of preventing latch-up of a CMOS integrated circuit using such an epitaxial substrate.
Referring to FIG. ⁺ A p-type Si layer 1A is epitaxially formed on the Si substrate 1 and an n-channel MOS transistor T is formed on the Si layer 1A. ₁ Diffusion regions 3 and 5 to be source regions or drain regions are formed. Further, the n-channel MOS transistor T is included in the Si layer 1A. ₁ An n-type well 2 is formed adjacent to the p-channel MOS transistor T in the well 2. ₂ Diffusion regions 4 and 6 to be source regions or drain regions are formed.
[0004]
Further, in the CMOS integrated circuit of FIG. 1, the MOS transistor T ₁ Corresponding to the channel region, a gate insulating film 7 and a gate electrode 9 are formed on the Si epitaxial layer 1A, and further, on the n-type well 2, the MOS transistor T ₂ A gate insulating film 8 and a gate electrode 10 are formed corresponding to the channel region. Further, in order to stabilize the potentials of the Si epitaxial layer 1A and the n-type well 2, the layers 1A and 2 have p ⁺ Mold diffusion region 11 and n ⁺ A mold diffusion region 12 is formed.
[0005]
In such a configuration, the p-type Si epitaxial layer 1A itself is a base, n ⁺ A parasitic npn bipolar transistor 13 having a type diffusion region 3 as an emitter and an n well 2 as a collector, and the n type well 2 itself as a base, p ⁺ A parasitic thyristor composed of a parasitic pnp bipolar transistor 14 having a type diffusion region 4 as an emitter and a p-type Si epitaxial layer 1A as a collector is formed. A low resistance p is formed under the Si layer 1A. ⁺ By providing the type Si substrate 1, the resistance R1 between the base and the emitter of the transistor 13 is reduced, and the transistor 13 and therefore the parasitic thyristor is hardly turned on. This is because the low resistance Si substrate 1 forms a low resistance current path between the base and emitter of the transistor 13.
[0006]
[Problems to be solved by the invention]
On the other hand, in general, in a semiconductor integrated circuit, a protection circuit is often formed on a part of a substrate in order to prevent a voltage surge from being applied to an internal element and electrostatic breakdown. In general, such a protection circuit is often formed near the input / output pad. However, in a semiconductor integrated circuit formed on an epitaxial substrate, a voltage surge is applied when a low-resistance Si substrate exists under the epitaxial layer. Even if this is done, the protection circuit is difficult to turn on, and charges are likely to accumulate in the internal elements. Such charge is locally discharged and causes thermal destruction.
[0007]
FIG. 2 shows an example in which a protection circuit used in a conventional semiconductor integrated circuit is applied to the epitaxial substrate of FIG. However, in FIG. 2, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.
Referring to FIG. ^- A p-type well 21 is formed in the p-type Si epitaxial layer 1A. In the p-type well 21, n connected to the external terminal 20 via a line 20a is formed. ⁺ Mold diffusion region 21A and another n ⁺ A mold diffusion region 21B is formed with a field oxide film 22 interposed therebetween, and the diffusion region 21B is grounded. Further, a grounded p-type diffusion region 21C is formed in the p-type well 21 in order to keep the potential of the well 21 at the ground potential. A signal that has entered the external terminal 20 reaches the diffusion region 21A once via the line 20a, and then is transmitted to an internal circuit (not shown) via another line 20b. The internal circuit may be, for example, a CMOS circuit shown in FIG.
[0008]
In the protection circuit of FIG. 2, n in the p-type well 21. ⁺ Type diffusion region 21B as an emitter, n ⁺ A lateral bipolar transistor 21a is formed using the type diffusion region 21A as a collector. When a large positive surge is applied to the external terminal 20, the lateral bipolar transistor 21a conducts and releases the surge to the ground. On the other hand, when a large negative surge is applied to the external terminal, the n ⁺ The pn junction between the type diffusion region 21A and the p-type well 21 is forward biased, and the surge is released from the diffusion region 21A through the well 21 and further through the diffusion region 21C to the ground.
[0009]
On the other hand, when the protection circuit of FIG. 2 is formed on the epitaxial substrate in this way, it has been found that ESD (electrostatic discharge) of the semiconductor device constituting the internal circuit is remarkably deteriorated.
As shown in FIG. 3, when forming a semiconductor integrated circuit on the epitaxial layer 1A, the p-type dopant diffuses from the low-resistance substrate 1 doped at a high concentration as a result of the heat treatment to the epitaxial layer 1A. As a result, it is considered that the impurity concentration in the epitaxial layer 1A increases. That is, as the impurity concentration in the epitaxial layer 1A increases, the resistance value of the epitaxial layer 1A decreases, and the base and emitter of the lateral bipolar transistor 21a become close to a connected state. For this reason, even if a large positive voltage surge is applied to the external terminal 20, the transistor 21a is not easily turned on, and the surge is applied to the protection circuit and the internal circuit without being dissipated, thereby electrostatically destroying it. Furthermore, the electric charge accompanying the surge is accumulated in the diffusion region 21A and destroys the lateral transistor 21a. When a large negative voltage surge is applied to the external terminal 20, a large current flows through the p-well 21 because the p-well 21 has a low resistance, and the protection circuit is destroyed by the Joule heat.
[0010]
FIG. 4 shows p doped with B ⁺ 3 shows diffusion of B from the Si substrate to the epitaxial layer when an epitaxial substrate in which a p-type Si epitaxial layer having a thickness of 2 microns is formed on a type Si substrate is heat-treated at 1000 ° C. for 30 minutes.
Referring to FIG. 4, B is about 1 × 10 6 in the Si substrate. ¹⁹ cm ^-3 While the epitaxial layer on the Si substrate is substantially undoped and the B concentration immediately after formation is about 1 × 10 ¹⁵ cm ^-3 As described below, the concentration change of B, which was very steep at the interface between the Si substrate and the epitaxial layer before the heat treatment, becomes gentle as a result of the thermal diffusion of B after the heat treatment. It turns out that it has spread | diffused in the epitaxial layer. In the illustrated example, the B concentration is 1 × 10. ¹⁹ cm ^-3 It can be seen that this region penetrates about 1 micron into the epitaxial layer.
[0011]
FIG. 5 shows the results of measuring the resistance value of the p-type well 21 in the epitaxial layer 1A while varying the thickness of the epitaxial layer 1A in the epitaxial substrate of FIG.
Referring to FIG. 5, when a simple p-type Si substrate described as BULK is used as the p-type well 21, in other words, when the thickness of the p-type epitaxial layer 1A is considered to be infinite. While the resistance value of the p-type well 21 is about 3500Ω, the resistance value of the p-type well 21 decreases as the thickness of the epitaxial layer 1A decreases, and when the thickness is about 2 microns, the resistance value is 100Ω. Although it decreases to the following, this is the same as the p described with reference to FIG. ⁺ It shows that substantial diffusion of B from the type Si substrate 1 occurs.
[0012]
FIG. 6 shows the relationship between the voltage at which the protection circuit is electrostatically broken and the thickness of the p-type epitaxial layer 1A in the epitaxial substrate of FIG. However, in the electrostatic breakdown test of FIG. 6, a positive or negative surge voltage is accumulated in a capacitor having a capacity of 200 pF, and this is applied to the protection circuit five times at intervals of 0.5 seconds, and then the leakage current generated It was performed by measuring.
[0013]
Referring to FIG. 6, the voltage at which electrostatic breakdown occurs (failure voltage) decreases as the thickness of the epitaxial layer 1A decreases with respect to both positive and negative surge voltages. It can be seen that the thickness drops to about 200 V when the thickness is 2 μm. From this, p explained in FIG. ⁺ It can be seen that the diffusion of B from the type Si substrate 1 into the epitaxial layer 1A has a serious effect on the operation of the semiconductor integrated circuit formed on the epitaxial substrate.
[0014]
SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a new and useful semiconductor device and a method for manufacturing the same that solve the above-described problems.
A more specific problem of the present invention is that, in an epitaxial substrate in which a low concentration epitaxial layer is formed on a high concentration substrate, a high resistance region is formed in the vicinity of the interface between the high concentration substrate and the low concentration epitaxial layer, The object is to reliably operate the surge protection circuit formed on the substrate.
[0015]
[Means for Solving the Problems]
The present invention solves the above-described problems by providing a substrate containing a first impurity element at a first concentration and a second concentration formed on the substrate, the first impurity element being lower than the first concentration. In the method of manufacturing a semiconductor device on an epitaxial substrate including an epitaxial layer including the first impurity element in a region near the interface between the substrate and the epitaxial layer in the epitaxial substrate. Second impurity element introduced by ion implantation And form a high-resistance region Including the process of In the epitaxial layer, there is formed a protection circuit for preventing electrostatic breakdown that turns on when a surge current comes in and releases the surge current to the ground. According to a method of manufacturing a semiconductor device , Solution Decide.
[0016]
Referring to FIG. 7, in the present invention, a high resistance layer 1B is formed in the vicinity of the interface between the heavily doped substrate 1 and the lightly doped epitaxial layer 1A thereon to prevent electrostatic breakdown described in FIG. The p-type well 21 in which the protection circuit is formed is formed on the high resistance layer 1B. With this configuration, the protection circuit formed in the p-type well 21 is easily turned on when a surge current comes in, and the surge current is immediately released to ground. For this reason, the internal circuit of the semiconductor integrated circuit and further the protection circuit itself are not destroyed by the surge voltage accompanying the surge current.
[0017]
The high resistance layer 1B is sufficient to cancel carriers formed by impurity elements in the heavily doped substrate 1 in the vicinity of the interface between the heavily doped substrate 1 and the epitaxial layer 1A in the epitaxial substrate, for example. It can be formed by introducing an impurity element of an opposite conductivity type in an amount sufficient to invert the conductivity type or by ion implantation.
[0018]
Further, the high resistance layer 1B is formed by a diffusion barrier layer that blocks diffusion of an impurity element from the heavily doped substrate 1 to the epitaxial layer 1A, in this case B, indicated by an arrow in FIG. It may be formed. Also in this case, a decrease in the resistance value of the epitaxial layer 1A is suppressed, and normal operation of the protection circuit is guaranteed. Further, the high resistance layer 1B may be formed by epitaxially growing a region in which the conductivity type is reversed with that of the substrate 1 at the interface between the substrate 1 and the epitaxial layer 1A.
[0019]
The high resistance layer 1B is preferably formed locally immediately below the protection circuit.
FIG. 8 is a diagram showing the concentration distribution in the depth direction of P in the epitaxial substrate when the high resistance layer 1B of FIG. 7 is formed by ion implantation of P. However, as in the case of FIG. 4 described above, the thickness of the epitaxial layer 1A is 2 μm.
[0020]
Referring to FIG. 8, in the Si substrate 1, as described above with reference to FIG. ¹⁹ cm ^-3 The ion implantation of P is about 1.5 × 10 MeV acceleration energy and about 1 × 10 ¹³ cm ^-2 After the thermal diffusion step at 1000 ° C. for 30 minutes, the Si substrate 1 and the epitaxial layer 1A are formed as shown in FIG. The P concentration distribution peak is located slightly shallower than the interface, and the P concentration in the peak is about 2 × 10 ¹⁷ cm ^-3 It turns out that it becomes. The concentration of P is the concentration of B in the Si substrate 1, 1 × 10 ¹⁹ cm ^-3 Although it is lower, the concentration is almost the same as the concentration of B diffused from the substrate 1 at the same depth.
[0021]
FIG. 9 shows the profile of the hole concentration in the depth direction in the epitaxial substrate in which P in FIG. 8 is deeply doped.
Referring to FIG. 9, a region slightly above the interface between the Si substrate 1 and the epitaxial layer 1A where the concentration of the ion-implanted P exceeds the concentration of B diffused from the substrate 1, that is, the high resistance of FIG. It can be seen that there is a significant depletion of holes in the region corresponding to layer 1B.
[0022]
In the ion implantation step of FIG. 8, the dose of P introduced may be further increased. In this case, the conductivity type is reversed in the high resistance layer 1B, and the high resistance layer 1B becomes n-type. ⁺ A depletion layer associated with a pn junction formed between the Si substrate 1 and the type Si substrate 1 functions as a high resistance layer.
In the ion implantation process of FIG. 8, the dose of P is set so that the concentration of P on the surface is about 1 × so that the conductivity type of the p-type well on the surface of the epitaxial substrate, that is, the surface of the epitaxial layer 1A does not change. 10 ¹⁴ cm ^-2 However, this is not essential. When the dose of P is further increased and the conductivity type on the surface of the epitaxial layer 1A is changed, a well having a predetermined conductivity type may be formed again.
[0023]
Further, as described above, the high resistance layer 1B may be formed by a diffusion barrier that blocks diffusion of impurity elements from the substrate 1.
FIG. 10 shows n doped with P as the Si substrate 1 at a high concentration. ⁺ N-type Si substrate ⁺ In the epitaxial substrate configured to form a p-type Si epitaxial layer on the Si substrate 1 as the epitaxial layer 1A, the high resistance layer 1B has a thickness of about
2 shows a P and B concentration distribution profile in the depth direction of an epitaxial substrate after a 0.05 μm SiN layer is formed and heat-treated at 1000 ° C. for 30 minutes.
[0024]
Referring to FIG. ⁺ Type Si substrate is about 3 × 10 ¹⁴ cm ^-3 However, the diffusion of P into the epitaxial layer 1A is substantially completely suppressed only by forming the SiN layer 1B on the Si substrate 1 to a thickness of about 0.05 μm. You can see that Further, the diffusion of B from the epitaxial layer 1A into the Si substrate 1 is substantially completely suppressed. Thus, the high resistance layer 1B functions as an effective diffusion barrier.
[0025]
On the other hand, FIG. ⁺ 1 shows a concentration distribution of P and B when a p-type Si epitaxial layer 1A is formed on a Si substrate 1 without forming a high-resistance layer 1B and is heat-treated at 1000 ° C. for 30 minutes.
Referring to FIG. 11, a substantial amount of P diffuses from the Si substrate 1 in the epitaxial layer 1A, and a substantial amount of B from the epitaxial layer 1A also enters the Si substrate 1. It can be seen that diffusion occurs. When a protective circuit for preventing electrostatic breakdown is formed in such an epitaxial layer 1A, the protective circuit does not function as described above, and the internal circuit formed on the epitaxial substrate and the protective circuit itself are also surged. Damaged by surge voltage associated with current.
[0026]
FIG. 12 shows an SiO 2 substrate having the same thickness of about 0.05 μm as the high resistance layer 1B instead of the SiN layer in the epitaxial substrate having the structure shown in FIG. ₂ The density | concentration distribution of P and B to the depth direction in an epitaxial substrate at the time of forming a layer is shown.
Referring to FIG. 12, the high resistance layer 1B is made of SiO. ₂ Even when layers are used, the diffusion of P from the Si substrate 1 to the epitaxial layer 1A and the diffusion of B from the epitaxial layer 1A to the Si substrate 1 are effectively suppressed.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
[First embodiment]
FIG. 13 shows the configuration of the semiconductor device according to the first embodiment of the present invention.
Referring to FIG. 13, B is approximately 1 × 10 ¹⁹ cm ^-3 Highly doped p ⁺ Although the type Si substrate 31 has a very low specific resistance value of about 0.01 Ω · cm, the semiconductor device according to this example has a specific resistance value of about 10 Ω · cm on the low resistance Si substrate 31. P lightly doped with B ^- A type epitaxial Si layer 31A is formed on an epitaxial substrate having a thickness of about 5 μm.
[0028]
P ^- A p-type well 41 is formed on the p-type epitaxial Si layer 31A. ⁺ Mold diffusion regions 41A and 41B are formed with field oxide film 42 therebetween. Further, a p-type diffusion region 41C is formed in the p-type well 41, and the n-type well 41c is formed. ⁺ Type diffusion region 41B and p type diffusion region 41C are grounded. That is, in the p-type well 41, a protection circuit for preventing electrostatic breakdown similar to that described in FIG. 2 is formed.
[0029]
Meanwhile, the n ⁺ The mold diffusion region 41A is connected to the external terminal 43 through the conductor pattern 43a, and is further connected to an internal circuit including the CMOS circuit shown in FIG. 1 through the conductor pattern 43b.
In the semiconductor device of this embodiment, an SiN pattern 31B having a thickness of about 0.1 μm is formed immediately below the diffusion region 41 on the low resistance Si substrate 31 constituting the epitaxial substrate. SiO with a thickness of about 0.1 μm to cover ₂ The pattern 31C is formed as the high resistance layer 1B described above with reference to FIG. The patterns 31B and 31C themselves have a high resistance, and effectively suppress the diffusion of B from the Si substrate 31 to the epitaxial layer 31A indicated by an arrow in FIG.
[0030]
SiN pattern 31B and SiO ₂ The pattern 31C is formed by a normal CVD method, and the p ^- The type epitaxial layer 31A is formed by epitaxial growth of the Si layer in the lateral direction (ELO: epiaxial axial overgrowth). More specifically, the SiN pattern 31B and SiO on the Si substrate 31. ₂ After forming the pattern 31C, 1 × 10 B is formed on the Si substrate 31 by the CVD method. ¹⁴ cm ^-3 P including degree ^- A type Si layer is formed epitaxially. At that time, the epitaxial Si layer is formed of the SiO. ₂ Although not deposited on the pattern 31C, the epitaxial Si layer is deposited on the SiO. ₂ By growing beyond the thickness of the pattern 31C, the SiO layer is included in the epitaxial Si layer. ₂ A recess surrounding the pattern 31C is formed. Therefore, the Si layer is further epitaxially grown from the side wall surface defining the concave portion to the side, and the surface is flattened, whereby the SiO layer is planarized. ₂ An epitaxial layer 31A covering pattern 31C is formed.
[0031]
14A to 14C show various modifications of the semiconductor device according to the first embodiment of the present invention. However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.
Referring to FIG. 14 (A), the p ⁺ In the Si substrate 31, a refractory metal silicide corresponding to the p-type well 41, for example, CoSi ₂ A diffusion barrier layer 31D made of high-resistance SiO is formed thereon. ₂ A pattern 31E is formed. In the configuration of FIG. 14A, the diffusion of B from the Si substrate 31 to the epitaxial layer 31A is blocked by the diffusion barrier layer 31D, while a low-resistance current path directly below the p-type well 41 where the protection circuit is formed. SiO ₂ It is blocked by the pattern 31E.
[0032]
The modification of FIG. 14B has a configuration in which the low-resistance silicide layer 31D is omitted from the configuration of FIG. ₂ The pattern 31E functions as a diffusion barrier layer and a low resistance layer. As the silicide layer 31D, CoSi ₂ In addition to TiSi ₂ , MoSi ₂ , WSi ₂ Etc. are possible.
Furthermore, in the modified example of FIG. ⁺ N doped at a high concentration with P or As on the p-type well 41 on the p-type Si substrate 31 ⁺ A type Si pattern 31F is formed, and the epitaxial layer 31A is formed so as to cover the Si pattern 31F.
[0033]
In the configuration of FIG. ⁺ The type Si pattern 31F does not function as an impurity element diffusion region, but is adjacent to p ⁺ Mold substrate 31 or p ^- A high resistance depletion layer associated with the pn junction is formed between the epitaxial layer 31A and the epitaxial layer 31A. The n ⁺ The n-type impurity element diffuses toward the substrate surface as a result of the heat treatment from the type region 31F. The n-type impurity element neutralizes doping generated in the epitaxial layer 31A by the p-type impurity element diffused from the substrate 31. As a result, the n ⁺ A high resistance region having a low carrier concentration is formed so as to substantially overlap with the mold region 31F.
[0034]
Even in such a configuration, normal operation of the protection circuit formed in the p-type well 41 is ensured.
[Second Embodiment]
15A to 15C show a manufacturing process of a semiconductor device according to the second embodiment of the present invention. However, the parts described above are denoted by the same reference numerals, and description thereof is omitted.
[0035]
Referring to FIG. 15A, the p ⁺ P on mold substrate 31 ^- The type epitaxial layer 31A typically has a thickness of 2 μm, and a resist pattern 51 having an opening 51A formed on the epitaxial layer 31A typically has a thickness of 2.5 to 2.6 μm. Formed. The resist pattern is preferably one that can stably maintain the pattern even when the film thickness is increased. For example, PF147B (trade name) commercially available from Sumitomo Chemical Co., Ltd. or commercially available from Nippon Synthetic Rubber Co., Ltd. The PFR7300 (trade name) system is convenient.
[0036]
Next, in the step of FIG. 15B, with the resist pattern 51 as a mask, P is typically 1.5 MeV acceleration energy and about 1 × 10 × 10. ¹³ cm ^-2 Ion implantation at a dose of about ^- In the epitaxial epitaxial layer 31A, P is introduced in the vicinity of the interface between the layer 31A and the underlying Si substrate 31. As an apparatus for performing ion implantation at such high energy, for example, a G1520 (trade name) ion implantation apparatus manufactured by Genus Corporation can be used.
[0037]
Further, in the step of FIG. 15C, the resist pattern 51 is removed, and typically after heat treatment at 1000 ° C. for about 30 minutes, a slightly shallow position near the interface between the layer 31A and the substrate 31 is obtained. A high resistance region 31H corresponding to the high resistance region described above with reference to FIG. 9 is formed. Further, in the step of FIG. 15B, by performing ion implantation of B in the vicinity of the surface of the epitaxial layer 31A using the resist pattern 51 as a mask, the heat treatment step of FIG. At the same time, the p-type well 41 can be formed.
[0038]
As described above with reference to FIGS. 8 and 9, the ion implantation of P in the step of FIG. 15B diffuses the dose from the substrate 31 to the layer 31A in the high resistance region 31H. The value is set so that the formation of holes due to B is substantially compensated. At that time, the dose is excessively compensated for the formation of the holes, and is n-type or n-type corresponding to the high resistance region 31H. ⁺ You may set so that a type | mold area | region may be formed. In this case, the formed n-type or n-type ⁺ P adjacent to the mold region ^- Type epitaxial layer 31A or p ⁺ In order to form a depletion layer with the mold substrate 31, a high resistance region is formed anyway. Even when the dose is small and insufficient to compensate for the hole formation, the effect of reducing the resistance value of the epitaxial layer 31A in the region immediately below the p-type well 41 can be obtained.
[0039]
In the present embodiment, the high resistance region 31H can be formed as necessary after manufacturing the epitaxial substrate. In addition, a process such as LEO is not required for forming the high resistance region 31H.
In the first and second embodiments of the present invention, as described above with reference to FIGS. 10 to 12, the present invention is established even if the conductivity type is switched between the p-type and the n-type.
[0040]
Furthermore, in the present invention, the protection circuit is not limited to that shown in FIG. 13, and for example, the protection circuit shown in FIG. 16 can be used. However, the parts described previously in FIG. 16 are denoted by the same reference numerals, and the description thereof is omitted.
Referring to FIG. 16, in the protection circuit shown in FIG. 13, the field oxide film 42 is constituted by a gate insulating film 42A and a gate electrode 42B in the protection circuit of FIG. 13, and the gate electrode 42B is grounded together with the diffusion region 41B. Also good.
[0041]
Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the claims.
[0042]
【The invention's effect】
According to the features of the present invention described in claims 1 to 7, in an epitaxial substrate comprising a highly doped substrate and a lightly doped epitaxial layer formed on the heavily doped substrate, A high resistance region is formed in the vicinity of the interface by introducing an impurity element having a conductivity type opposite to that of the heavily doped substrate in the vicinity of the interface with the concentration epitaxial layer, and is formed in the low concentration epitaxial layer. The protection circuit operates reliably against a voltage surge.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining latch-up in a conventional CMOS integrated circuit using an epitaxial substrate.
FIG. 2 is a diagram showing a configuration of a protection circuit of an integrated circuit formed on a conventional epitaxial substrate.
FIG. 3 is a diagram for explaining problems that occur in a conventional epitaxial substrate.
FIG. 4 is a diagram showing a problem of impurity element diffusion from a heavily doped substrate to a lightly doped epitaxial layer, which occurs in a conventional epitaxial substrate.
FIG. 5 is a diagram (part 1) for explaining a problem caused by diffusion of an impurity element that occurs in a conventional epitaxial substrate.
FIG. 6 is a diagram (part 2) for explaining a problem caused by diffusion of an impurity element generated in a conventional epitaxial substrate.
FIG. 7 is a diagram (part 1) for explaining the principle of the present invention;
FIG. 8 is a diagram (part 2) for explaining the principle of the present invention;
FIG. 9 is a diagram (part 3) for explaining the principle of the present invention;
FIG. 10 is a diagram (part 4) for explaining the principle of the present invention;
FIG. 11 is a diagram (part 5) for explaining the principle of the present invention;
FIG. 12 is a diagram (part 6) for explaining the principle of the present invention;
FIG. 13 is a diagram showing a configuration of a semiconductor device according to a first example of the present invention.
FIGS. 14A to 14C are diagrams showing modifications of the first embodiment of the present invention.
FIGS. 15A to 15C are views showing a method of manufacturing a semiconductor device according to a second embodiment of the invention. FIGS.
FIG. 16 is a diagram showing a configuration of a semiconductor device provided with another protection circuit applicable to the present invention.
[Explanation of symbols]
1,31 Highly doped substrate
1A, 31A epitaxial layer
1B, 31H High resistance region
2 n-type well
3, 5, 12, 21A, 21B, 41A, 41B n ⁺ Mold diffusion region
4,6,11,21C, 41C p ⁺ Mold diffusion region
7, 8, 42A Gate insulation film
9, 10, 42B Gate electrode
13,14 Parasitic bipolar transistor
20, 43 External terminal
20a, 20b, 43a, 43b Conductor pattern
21 p-type well
21a Lateral bipolar transistor
22 Field insulating film
31B SiN pattern
31C, 31E SiO ₂ pattern
31D refractory silicide pattern
31F n ⁺ Mold pattern
31G implanted P ion
31H high resistance region
51 resist pattern
51A opening

Claims (8)

An epitaxial substrate comprising: a substrate containing a first impurity element at a first concentration; and an epitaxial layer formed on the substrate and containing the first impurity element at a second concentration lower than the first concentration. In the semiconductor device manufacturing method above,
In the epitaxial substrate, a second impurity element having a conductivity type opposite to that of the first impurity element is introduced into a region near the interface between the substrate and the epitaxial layer by ion implantation to form a high resistance region . the process only contains,
A method of manufacturing a semiconductor device, wherein a protective circuit for preventing electrostatic breakdown is formed in the epitaxial layer to turn on when a surge current comes in and to release the surge current to ground .   2. The semiconductor device according to claim 1, wherein in the ion implantation step, the second impurity element is introduced at a dose such that carrier depletion occurs in a region into which the second impurity element is introduced. Production method.   3. The semiconductor according to claim 1, wherein the ion implantation step is performed with an acceleration energy such that the second impurity element is introduced to a depth in the vicinity of an interface between the substrate and the epitaxial layer. Device manufacturing method.   2. The ion implantation process is performed such that the second impurity element is introduced in a region near the interface between the substrate and the epitaxial layer and shallower than the interface. The manufacturing method of the semiconductor device as described in any one of 1-4.   The ion implantation step is performed at a dose such that the concentration of the second impurity element is higher than the concentration of the first impurity element in the region into which the second impurity element is introduced. A method for manufacturing a semiconductor device according to claim 1.   The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation step is locally performed using a resist mask formed on the epitaxial layer. Moreover, the on epitaxial layer, on the second region to which an impurity element is introduced, the semiconductor device according to claim 6, characterized in that it comprises a step of forming a protective circuit for preventing the electrostatic breakdown Production method. The method of manufacturing a semiconductor device according to claim 1, wherein the protection circuit for preventing electrostatic breakdown includes a lateral bipolar transistor that conducts when a surge voltage is applied. .

Images